include/configs/MPC8540ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8540ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_SERVERIP, etc in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 #define CONFIG_SYS_GENERIC_BOARD
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 /* High Level Configuration Options */
  25 #define CONFIG_BOOKE            1       /* BOOKE */
  26 #define CONFIG_E500             1       /* BOOKE e500 family */
  27 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  28 #define CONFIG_MPC8540ADS       1       /* MPC8540ADS board specific */
  29
  30 /*
  31  * default CCARBAR is at 0xff700000
  32  * assume U-Boot is less than 0.5MB
  33  */
  34 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  35
  36 #ifndef CONFIG_HAS_FEC
  37 #define CONFIG_HAS_FEC          1       /* 8540 has FEC */
  38 #endif
  39
  40 #define CONFIG_PCI
  41 #define CONFIG_PCI_INDIRECT_BRIDGE
  42 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  43 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  44 #define CONFIG_ENV_OVERWRITE
  45 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  46
  47 /*
  48  * sysclk for MPC85xx
  49  *
  50  * Two valid values are:
  51  *    33000000
  52  *    66000000
  53  *
  54  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  55  * is likely the desired value here, so that is now the default.
  56  * The board, however, can run at 66MHz.  In any event, this value
  57  * must match the settings of some switches.  Details can be found
  58  * in the README.mpc85xxads.
  59  *
  60  * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
  61  * 33MHz to accommodate, based on a PCI pin.
  62  * Note that PCI-X won't work at 33MHz.
  63  */
  64
  65 #ifndef CONFIG_SYS_CLK_FREQ
  66 #define CONFIG_SYS_CLK_FREQ     33000000
  67 #endif
  68
  69
  70 /*
  71  * These can be toggled for performance analysis, otherwise use default.
  72  */
  73 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  74 #define CONFIG_BTB                      /* toggle branch predition */
  75
  76 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  77 #define CONFIG_SYS_MEMTEST_END          0x00400000
  78
  79 #define CONFIG_SYS_CCSRBAR              0xe0000000
  80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  81
  82 /* DDR Setup */
  83 #define CONFIG_SYS_FSL_DDR1
  84 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  85 #define CONFIG_DDR_SPD
  86 #undef CONFIG_FSL_DDR_INTERACTIVE
  87
  88 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  89
  90 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  92
  93 #define CONFIG_NUM_DDR_CONTROLLERS      1
  94 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  95 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  96
  97 /* I2C addresses of SPD EEPROMs */
  98 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  99
 100 /* These are used when DDR doesn't use SPD. */
 101 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
 102 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
 103 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
 104 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 105 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 106 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 107 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 108 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 109
 110 /*
 111  * SDRAM on the Local Bus
 112  */
 113 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 114 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 115
 116 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 117 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 118
 119 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 120 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 121 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 122 #undef  CONFIG_SYS_FLASH_CHECKSUM
 123 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 124 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 125
 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 127
 128 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 129 #define CONFIG_SYS_RAMBOOT
 130 #else
 131 #undef  CONFIG_SYS_RAMBOOT
 132 #endif
 133
 134 #define CONFIG_FLASH_CFI_DRIVER
 135 #define CONFIG_SYS_FLASH_CFI
 136 #define CONFIG_SYS_FLASH_EMPTY_INFO
 137
 138 #undef CONFIG_CLOCKS_IN_MHZ
 139
 140
 141 /*
 142  * Local Bus Definitions
 143  */
 144
 145 /*
 146  * Base Register 2 and Option Register 2 configure SDRAM.
 147  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 148  *
 149  * For BR2, need:
 150  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 151  *    port-size = 32-bits = BR2[19:20] = 11
 152  *    no parity checking = BR2[21:22] = 00
 153  *    SDRAM for MSEL = BR2[24:26] = 011
 154  *    Valid = BR[31] = 1
 155  *
 156  * 0    4    8    12   16   20   24   28
 157  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 158  *
 159  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 160  * FIXME: the top 17 bits of BR2.
 161  */
 162
 163 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 164
 165 /*
 166  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 167  *
 168  * For OR2, need:
 169  *    64MB mask for AM, OR2[0:7] = 1111 1100
 170  *                 XAM, OR2[17:18] = 11
 171  *    9 columns OR2[19-21] = 010
 172  *    13 rows   OR2[23-25] = 100
 173  *    EAD set for extra time OR[31] = 1
 174  *
 175  * 0    4    8    12   16   20   24   28
 176  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 177  */
 178
 179 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 180
 181 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 182 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 183 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 184 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 185
 186 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 187                                 | LSDMR_RFCR5           \
 188                                 | LSDMR_PRETOACT3       \
 189                                 | LSDMR_ACTTORW3        \
 190                                 | LSDMR_BL8             \
 191                                 | LSDMR_WRC2            \
 192                                 | LSDMR_CL3             \
 193                                 | LSDMR_RFEN            \
 194                                 )
 195
 196 /*
 197  * SDRAM Controller configuration sequence.
 198  */
 199 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 200 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 201 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 202 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 203 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 204
 205
 206 /*
 207  * 32KB, 8-bit wide for ADS config reg
 208  */
 209 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 210 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 211 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 212
 213 #define CONFIG_SYS_INIT_RAM_LOCK        1
 214 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 215 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 216
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 218 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 219
 220 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 221 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 222
 223 /* Serial Port */
 224 #define CONFIG_CONS_INDEX     1
 225 #define CONFIG_SYS_NS16550
 226 #define CONFIG_SYS_NS16550_SERIAL
 227 #define CONFIG_SYS_NS16550_REG_SIZE    1
 228 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 229
 230 #define CONFIG_SYS_BAUDRATE_TABLE  \
 231         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 232
 233 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 234 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 235
 236 /* Use the HUSH parser */
 237 #define CONFIG_SYS_HUSH_PARSER
 238 #ifdef  CONFIG_SYS_HUSH_PARSER
 239 #endif
 240
 241 /* pass open firmware flat tree */
 242 #define CONFIG_OF_LIBFDT                1
 243 #define CONFIG_OF_BOARD_SETUP           1
 244 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 245
 246 /*
 247  * I2C
 248  */
 249 #define CONFIG_SYS_I2C
 250 #define CONFIG_SYS_I2C_FSL
 251 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 252 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 253 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 254 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 255
 256 /* RapidIO MMU */
 257 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 258 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 259 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 260 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 261
 262 /*
 263  * General PCI
 264  * Memory space is mapped 1-1, but I/O space must start from 0.
 265  */
 266 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 267 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 268 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 269 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 270 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 271 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 272 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 273 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 274
 275 #if defined(CONFIG_PCI)
 276
 277 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 278
 279 #undef CONFIG_EEPRO100
 280 #undef CONFIG_TULIP
 281
 282 #if !defined(CONFIG_PCI_PNP)
 283     #define PCI_ENET0_IOADDR    0xe0000000
 284     #define PCI_ENET0_MEMADDR   0xe0000000
 285     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 286 #endif
 287
 288 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 289 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 290
 291 #endif  /* CONFIG_PCI */
 292
 293
 294 #if defined(CONFIG_TSEC_ENET)
 295
 296 #define CONFIG_MII              1       /* MII PHY management */
 297 #define CONFIG_TSEC1    1
 298 #define CONFIG_TSEC1_NAME       "TSEC0"
 299 #define CONFIG_TSEC2    1
 300 #define CONFIG_TSEC2_NAME       "TSEC1"
 301 #define TSEC1_PHY_ADDR          0
 302 #define TSEC2_PHY_ADDR          1
 303 #define TSEC1_PHYIDX            0
 304 #define TSEC2_PHYIDX            0
 305 #define TSEC1_FLAGS             TSEC_GIGABIT
 306 #define TSEC2_FLAGS             TSEC_GIGABIT
 307
 308
 309 #if CONFIG_HAS_FEC
 310 #define CONFIG_MPC85XX_FEC      1
 311 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 312 #define FEC_PHY_ADDR            3
 313 #define FEC_PHYIDX              0
 314 #define FEC_FLAGS               0
 315 #endif
 316
 317 /* Options are: TSEC[0-1], FEC */
 318 #define CONFIG_ETHPRIME         "TSEC0"
 319
 320 #endif  /* CONFIG_TSEC_ENET */
 321
 322
 323 /*
 324  * Environment
 325  */
 326 #ifndef CONFIG_SYS_RAMBOOT
 327   #define CONFIG_ENV_IS_IN_FLASH        1
 328   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 329   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 330   #define CONFIG_ENV_SIZE               0x2000
 331 #else
 332   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 333   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 334   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 335   #define CONFIG_ENV_SIZE               0x2000
 336 #endif
 337
 338 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 339 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 340
 341
 342 /*
 343  * BOOTP options
 344  */
 345 #define CONFIG_BOOTP_BOOTFILESIZE
 346 #define CONFIG_BOOTP_BOOTPATH
 347 #define CONFIG_BOOTP_GATEWAY
 348 #define CONFIG_BOOTP_HOSTNAME
 349
 350
 351 /*
 352  * Command line configuration.
 353  */
 354 #define CONFIG_CMD_PING
 355 #define CONFIG_CMD_I2C
 356 #define CONFIG_CMD_IRQ
 357
 358 #if defined(CONFIG_PCI)
 359     #define CONFIG_CMD_PCI
 360 #endif
 361
 362 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 363
 364 /*
 365  * Miscellaneous configurable options
 366  */
 367 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 368 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 369 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 370 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 371
 372 #if defined(CONFIG_CMD_KGDB)
 373     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 374 #else
 375     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 376 #endif
 377
 378 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 379 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 380 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 381
 382 /*
 383  * For booting Linux, the board info and command line data
 384  * have to be in the first 64 MB of memory, since this is
 385  * the maximum mapped by the Linux kernel during initialization.
 386  */
 387 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 388 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 389
 390 #if defined(CONFIG_CMD_KGDB)
 391 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 392 #endif
 393
 394
 395 /*
 396  * Environment Configuration
 397  */
 398
 399 /* The mac addresses for all ethernet interface */
 400 #if defined(CONFIG_TSEC_ENET)
 401 #define CONFIG_HAS_ETH0
 402 #define CONFIG_HAS_ETH1
 403 #define CONFIG_HAS_ETH2
 404 #endif
 405
 406 #define CONFIG_IPADDR    192.168.1.253
 407
 408 #define CONFIG_HOSTNAME         unknown
 409 #define CONFIG_ROOTPATH         "/nfsroot"
 410 #define CONFIG_BOOTFILE         "your.uImage"
 411
 412 #define CONFIG_SERVERIP  192.168.1.1
 413 #define CONFIG_GATEWAYIP 192.168.1.1
 414 #define CONFIG_NETMASK   255.255.255.0
 415
 416 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 417
 418 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 419 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 420
 421 #define CONFIG_BAUDRATE 115200
 422
 423 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 424    "netdev=eth0\0"                                                      \
 425    "consoledev=ttyS0\0"                                                 \
 426    "ramdiskaddr=1000000\0"                                              \
 427    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 428    "fdtaddr=400000\0"                                                   \
 429    "fdtfile=your.fdt.dtb\0"
 430
 431 #define CONFIG_NFSBOOTCOMMAND                                           \
 432    "setenv bootargs root=/dev/nfs rw "                                  \
 433       "nfsroot=$serverip:$rootpath "                                    \
 434       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 435       "console=$consoledev,$baudrate $othbootargs;"                     \
 436    "tftp $loadaddr $bootfile;"                                          \
 437    "tftp $fdtaddr $fdtfile;"                                            \
 438    "bootm $loadaddr - $fdtaddr"
 439
 440 #define CONFIG_RAMBOOTCOMMAND \
 441    "setenv bootargs root=/dev/ram rw "                                  \
 442       "console=$consoledev,$baudrate $othbootargs;"                     \
 443    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 444    "tftp $loadaddr $bootfile;"                                          \
 445    "tftp $fdtaddr $fdtfile;"                                            \
 446    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 447
 448 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 449
 450 #endif  /* __CONFIG_H */