include/configs/MPC8540ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8540ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /* High Level Configuration Options */
  22 #define CONFIG_BOOKE            1       /* BOOKE */
  23 #define CONFIG_E500             1       /* BOOKE e500 family */
  24 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  25 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  26 #define CONFIG_MPC8540ADS       1       /* MPC8540ADS board specific */
  27
  28 /*
  29  * default CCARBAR is at 0xff700000
  30  * assume U-Boot is less than 0.5MB
  31  */
  32 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  33
  34 #ifndef CONFIG_HAS_FEC
  35 #define CONFIG_HAS_FEC          1       /* 8540 has FEC */
  36 #endif
  37
  38 #define CONFIG_PCI
  39 #define CONFIG_PCI_INDIRECT_BRIDGE
  40 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  41 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  42 #define CONFIG_ENV_OVERWRITE
  43 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  44
  45 /*
  46  * sysclk for MPC85xx
  47  *
  48  * Two valid values are:
  49  *    33000000
  50  *    66000000
  51  *
  52  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  53  * is likely the desired value here, so that is now the default.
  54  * The board, however, can run at 66MHz.  In any event, this value
  55  * must match the settings of some switches.  Details can be found
  56  * in the README.mpc85xxads.
  57  *
  58  * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
  59  * 33MHz to accommodate, based on a PCI pin.
  60  * Note that PCI-X won't work at 33MHz.
  61  */
  62
  63 #ifndef CONFIG_SYS_CLK_FREQ
  64 #define CONFIG_SYS_CLK_FREQ     33000000
  65 #endif
  66
  67
  68 /*
  69  * These can be toggled for performance analysis, otherwise use default.
  70  */
  71 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  72 #define CONFIG_BTB                      /* toggle branch predition */
  73
  74 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  75 #define CONFIG_SYS_MEMTEST_END          0x00400000
  76
  77 #define CONFIG_SYS_CCSRBAR              0xe0000000
  78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  79
  80 /* DDR Setup */
  81 #define CONFIG_FSL_DDR1
  82 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  83 #define CONFIG_DDR_SPD
  84 #undef CONFIG_FSL_DDR_INTERACTIVE
  85
  86 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  87
  88 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  89 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  90
  91 #define CONFIG_NUM_DDR_CONTROLLERS      1
  92 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  93 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  94
  95 /* I2C addresses of SPD EEPROMs */
  96 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  97
  98 /* These are used when DDR doesn't use SPD. */
  99 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
 100 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
 101 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
 102 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 103 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 104 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 105 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 106 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 107
 108 /*
 109  * SDRAM on the Local Bus
 110  */
 111 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 112 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 113
 114 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 115 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 116
 117 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 118 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 119 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 120 #undef  CONFIG_SYS_FLASH_CHECKSUM
 121 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 122 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 123
 124 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 125
 126 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 127 #define CONFIG_SYS_RAMBOOT
 128 #else
 129 #undef  CONFIG_SYS_RAMBOOT
 130 #endif
 131
 132 #define CONFIG_FLASH_CFI_DRIVER
 133 #define CONFIG_SYS_FLASH_CFI
 134 #define CONFIG_SYS_FLASH_EMPTY_INFO
 135
 136 #undef CONFIG_CLOCKS_IN_MHZ
 137
 138
 139 /*
 140  * Local Bus Definitions
 141  */
 142
 143 /*
 144  * Base Register 2 and Option Register 2 configure SDRAM.
 145  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 146  *
 147  * For BR2, need:
 148  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 149  *    port-size = 32-bits = BR2[19:20] = 11
 150  *    no parity checking = BR2[21:22] = 00
 151  *    SDRAM for MSEL = BR2[24:26] = 011
 152  *    Valid = BR[31] = 1
 153  *
 154  * 0    4    8    12   16   20   24   28
 155  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 156  *
 157  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 158  * FIXME: the top 17 bits of BR2.
 159  */
 160
 161 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 162
 163 /*
 164  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 165  *
 166  * For OR2, need:
 167  *    64MB mask for AM, OR2[0:7] = 1111 1100
 168  *                 XAM, OR2[17:18] = 11
 169  *    9 columns OR2[19-21] = 010
 170  *    13 rows   OR2[23-25] = 100
 171  *    EAD set for extra time OR[31] = 1
 172  *
 173  * 0    4    8    12   16   20   24   28
 174  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 175  */
 176
 177 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 178
 179 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 180 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 181 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 182 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 183
 184 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 185                                 | LSDMR_RFCR5           \
 186                                 | LSDMR_PRETOACT3       \
 187                                 | LSDMR_ACTTORW3        \
 188                                 | LSDMR_BL8             \
 189                                 | LSDMR_WRC2            \
 190                                 | LSDMR_CL3             \
 191                                 | LSDMR_RFEN            \
 192                                 )
 193
 194 /*
 195  * SDRAM Controller configuration sequence.
 196  */
 197 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 198 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 199 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 200 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 201 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 202
 203
 204 /*
 205  * 32KB, 8-bit wide for ADS config reg
 206  */
 207 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 208 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 209 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 210
 211 #define CONFIG_SYS_INIT_RAM_LOCK        1
 212 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 213 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 214
 215 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 216 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 217
 218 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 219 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 220
 221 /* Serial Port */
 222 #define CONFIG_CONS_INDEX     1
 223 #define CONFIG_SYS_NS16550
 224 #define CONFIG_SYS_NS16550_SERIAL
 225 #define CONFIG_SYS_NS16550_REG_SIZE    1
 226 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 227
 228 #define CONFIG_SYS_BAUDRATE_TABLE  \
 229         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 230
 231 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 232 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 233
 234 /* Use the HUSH parser */
 235 #define CONFIG_SYS_HUSH_PARSER
 236 #ifdef  CONFIG_SYS_HUSH_PARSER
 237 #endif
 238
 239 /* pass open firmware flat tree */
 240 #define CONFIG_OF_LIBFDT                1
 241 #define CONFIG_OF_BOARD_SETUP           1
 242 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 243
 244 /*
 245  * I2C
 246  */
 247 #define CONFIG_SYS_I2C
 248 #define CONFIG_SYS_I2C_FSL
 249 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 250 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 251 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 252 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 253
 254 /* RapidIO MMU */
 255 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 256 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 257 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 258 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 259
 260 /*
 261  * General PCI
 262  * Memory space is mapped 1-1, but I/O space must start from 0.
 263  */
 264 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 265 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 266 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 267 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 268 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 269 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 270 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 271 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 272
 273 #if defined(CONFIG_PCI)
 274
 275 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 276
 277 #undef CONFIG_EEPRO100
 278 #undef CONFIG_TULIP
 279
 280 #if !defined(CONFIG_PCI_PNP)
 281     #define PCI_ENET0_IOADDR    0xe0000000
 282     #define PCI_ENET0_MEMADDR   0xe0000000
 283     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 284 #endif
 285
 286 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 287 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 288
 289 #endif  /* CONFIG_PCI */
 290
 291
 292 #if defined(CONFIG_TSEC_ENET)
 293
 294 #define CONFIG_MII              1       /* MII PHY management */
 295 #define CONFIG_TSEC1    1
 296 #define CONFIG_TSEC1_NAME       "TSEC0"
 297 #define CONFIG_TSEC2    1
 298 #define CONFIG_TSEC2_NAME       "TSEC1"
 299 #define TSEC1_PHY_ADDR          0
 300 #define TSEC2_PHY_ADDR          1
 301 #define TSEC1_PHYIDX            0
 302 #define TSEC2_PHYIDX            0
 303 #define TSEC1_FLAGS             TSEC_GIGABIT
 304 #define TSEC2_FLAGS             TSEC_GIGABIT
 305
 306
 307 #if CONFIG_HAS_FEC
 308 #define CONFIG_MPC85XX_FEC      1
 309 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 310 #define FEC_PHY_ADDR            3
 311 #define FEC_PHYIDX              0
 312 #define FEC_FLAGS               0
 313 #endif
 314
 315 /* Options are: TSEC[0-1], FEC */
 316 #define CONFIG_ETHPRIME         "TSEC0"
 317
 318 #endif  /* CONFIG_TSEC_ENET */
 319
 320
 321 /*
 322  * Environment
 323  */
 324 #ifndef CONFIG_SYS_RAMBOOT
 325   #define CONFIG_ENV_IS_IN_FLASH        1
 326   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 327   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 328   #define CONFIG_ENV_SIZE               0x2000
 329 #else
 330   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 331   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 332   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 333   #define CONFIG_ENV_SIZE               0x2000
 334 #endif
 335
 336 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 337 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 338
 339
 340 /*
 341  * BOOTP options
 342  */
 343 #define CONFIG_BOOTP_BOOTFILESIZE
 344 #define CONFIG_BOOTP_BOOTPATH
 345 #define CONFIG_BOOTP_GATEWAY
 346 #define CONFIG_BOOTP_HOSTNAME
 347
 348
 349 /*
 350  * Command line configuration.
 351  */
 352 #include <config_cmd_default.h>
 353
 354 #define CONFIG_CMD_PING
 355 #define CONFIG_CMD_I2C
 356 #define CONFIG_CMD_ELF
 357 #define CONFIG_CMD_IRQ
 358 #define CONFIG_CMD_SETEXPR
 359
 360 #if defined(CONFIG_PCI)
 361     #define CONFIG_CMD_PCI
 362 #endif
 363
 364 #if defined(CONFIG_SYS_RAMBOOT)
 365     #undef CONFIG_CMD_SAVEENV
 366     #undef CONFIG_CMD_LOADS
 367 #endif
 368
 369
 370 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 371
 372 /*
 373  * Miscellaneous configurable options
 374  */
 375 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 376 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 377 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 378 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 379 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 380
 381 #if defined(CONFIG_CMD_KGDB)
 382     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 383 #else
 384     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 385 #endif
 386
 387 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 388 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 389 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 390 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 391
 392 /*
 393  * For booting Linux, the board info and command line data
 394  * have to be in the first 64 MB of memory, since this is
 395  * the maximum mapped by the Linux kernel during initialization.
 396  */
 397 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 398 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 399
 400 #if defined(CONFIG_CMD_KGDB)
 401 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 402 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 403 #endif
 404
 405
 406 /*
 407  * Environment Configuration
 408  */
 409
 410 /* The mac addresses for all ethernet interface */
 411 #if defined(CONFIG_TSEC_ENET)
 412 #define CONFIG_HAS_ETH0
 413 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 414 #define CONFIG_HAS_ETH1
 415 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 416 #define CONFIG_HAS_ETH2
 417 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 418 #endif
 419
 420 #define CONFIG_IPADDR    192.168.1.253
 421
 422 #define CONFIG_HOSTNAME         unknown
 423 #define CONFIG_ROOTPATH         "/nfsroot"
 424 #define CONFIG_BOOTFILE         "your.uImage"
 425
 426 #define CONFIG_SERVERIP  192.168.1.1
 427 #define CONFIG_GATEWAYIP 192.168.1.1
 428 #define CONFIG_NETMASK   255.255.255.0
 429
 430 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 431
 432 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 433 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 434
 435 #define CONFIG_BAUDRATE 115200
 436
 437 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 438    "netdev=eth0\0"                                                      \
 439    "consoledev=ttyS0\0"                                                 \
 440    "ramdiskaddr=1000000\0"                                              \
 441    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 442    "fdtaddr=400000\0"                                                   \
 443    "fdtfile=your.fdt.dtb\0"
 444
 445 #define CONFIG_NFSBOOTCOMMAND                                           \
 446    "setenv bootargs root=/dev/nfs rw "                                  \
 447       "nfsroot=$serverip:$rootpath "                                    \
 448       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 449       "console=$consoledev,$baudrate $othbootargs;"                     \
 450    "tftp $loadaddr $bootfile;"                                          \
 451    "tftp $fdtaddr $fdtfile;"                                            \
 452    "bootm $loadaddr - $fdtaddr"
 453
 454 #define CONFIG_RAMBOOTCOMMAND \
 455    "setenv bootargs root=/dev/ram rw "                                  \
 456       "console=$consoledev,$baudrate $othbootargs;"                     \
 457    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 458    "tftp $loadaddr $bootfile;"                                          \
 459    "tftp $fdtaddr $fdtfile;"                                            \
 460    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 461
 462 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 463
 464 #endif  /* __CONFIG_H */