include/configs/MPC8540EVAL.h

   1 /*
   2  * (C) Copyright 2002,2003 Motorola,Inc.
   3  * Modified by Lunsheng Wang, lunsheng@sohu.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* mpc8540eval board configuration file */
  25 /* please refer to doc/README.mpc85xxads for more info */
  26 /* make sure you change the MAC address and other network params first,
  27  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1           /* BOOKE                    */
  34 #define CONFIG_E500             1           /* BOOKE e500 family        */
  35 #define CONFIG_MPC85xx          1           /* MPC8540/MPC8560          */
  36 #define CONFIG_MPC8540          1           /* MPC8540 specific         */
  37 #define CONFIG_MPC8540EVAL      1           /* MPC8540EVAL board specific */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  40
  41 #undef  CONFIG_PCI                          /* pci ethernet support     */
  42 #define CONFIG_TSEC_ENET                    /* tsec ethernet support  */
  43 #define CONFIG_ENV_OVERWRITE
  44
  45 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  46
  47 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  48  * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  49  * Not availabe for EVAL board
  50  */
  51 #undef CONFIG_RAM_AS_FLASH
  52
  53 /* sysclk for MPC8540EVAL */
  54 #if defined(CONFIG_SYSCLK_66M)
  55         /*
  56          * the oscillator on board is 66Mhz
  57          * can also get 66M clock from external PCI
  58          */
  59         #define CONFIG_SYS_CLK_FREQ   66000000
  60 #else
  61         #define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
  62 #endif
  63
  64 /* below can be toggled for performance analysis. otherwise use default */
  65 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  66 #undef  CONFIG_BTB                          /* toggle branch predition */
  67
  68 #define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
  69
  70 #undef  CONFIG_SYS_DRAM_TEST                        /* memory test, takes time  */
  71 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on     */
  72 #define CONFIG_SYS_MEMTEST_END          0x00400000
  73
  74 #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
  75 #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
  76 #endif
  77
  78 /*
  79  * Base addresses -- Note these are effective addresses where the
  80  * actual resources get mapped (not physical addresses)
  81  */
  82 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default      */
  83 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR    */
  84 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  85 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
  86
  87 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is now 256MB     */
  88
  89 #if defined(CONFIG_RAM_AS_FLASH)
  90 #define CONFIG_SYS_LBC_SDRAM_BASE       0xfc000000      /* Localbus SDRAM */
  91 #else
  92 #define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
  93 #endif
  94 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 0MB     */
  95
  96 #if defined(CONFIG_RAM_AS_FLASH)
  97 #define CONFIG_SYS_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
  98 #define CONFIG_SYS_BR0_PRELIM          0xf8001801      /* port size 32bit */
  99 #else /* Boot from real Flash */
 100 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of FLASH 8M    */
 101 #define CONFIG_SYS_BR0_PRELIM           0xff801001      /* port size 16bit      */
 102 #endif
 103
 104 #define CONFIG_SYS_OR0_PRELIM           0xff806f67      /* 8MB Flash            */
 105 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks      */
 106 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device   */
 107 #undef  CONFIG_SYS_FLASH_CHECKSUM
 108 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Timeout for Flash Erase (in ms)*/
 109 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)*/
 110 #define CONFIG_SYS_FLASH_CFI            1
 111
 112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 113
 114 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 115 #define CONFIG_SYS_RAMBOOT
 116 #else
 117 #undef  CONFIG_SYS_RAMBOOT
 118 #endif
 119
 120 /* DDR Setup */
 121 #define CONFIG_FSL_DDR1
 122 #undef CONFIG_FSL_DDR_INTERACTIVE
 123 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 124 #define CONFIG_DDR_SPD
 125 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 126
 127 #undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
 128 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
 129 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 130
 131 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 132 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 133 #define CONFIG_VERY_BIG_RAM
 134
 135 #define CONFIG_NUM_DDR_CONTROLLERS      1
 136 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 137 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 138
 139 /* I2C addresses of SPD EEPROMs */
 140 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 141
 142 #undef CONFIG_CLOCKS_IN_MHZ
 143
 144 /* local bus definitions */
 145 #define CONFIG_SYS_BR2_PRELIM           0xf0001861      /* 64MB localbus SDRAM  */
 146 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 147 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* local bus freq divider*/
 148 #define CONFIG_SYS_LBC_LBCR             0x00000000
 149 #define CONFIG_SYS_LBC_LSRT             0x20000000
 150 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 151 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 152 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 153 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 154 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 155 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 156
 157 #if defined(CONFIG_RAM_AS_FLASH)
 158 #define CONFIG_SYS_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 159 #else
 160 #define CONFIG_SYS_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 161 #endif
 162 #define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
 163 #define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 164
 165 #define CONFIG_SYS_INIT_RAM_LOCK        1
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000      /* Initial RAM address  */
 167 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 168
 169 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 171 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 172
 173 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 174 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 175
 176 /* Serial Port */
 177 #define CONFIG_CONS_INDEX     1
 178 #define CONFIG_SYS_NS16550
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE    1
 181 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 182 #define CONFIG_BAUDRATE         115200
 183
 184 #define CONFIG_SYS_BAUDRATE_TABLE  \
 185         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 186
 187 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 188 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 189
 190 /* Use the HUSH parser */
 191 #define CONFIG_SYS_HUSH_PARSER
 192 #ifdef  CONFIG_SYS_HUSH_PARSER
 193 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 194 #endif
 195
 196 /*
 197  * I2C
 198  */
 199 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 200 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 201 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 202 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 203 #define CONFIG_SYS_I2C_SLAVE            0x7F
 204 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 205 #define CONFIG_SYS_I2C_OFFSET           0x3000
 206
 207 /* General PCI */
 208 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
 209 #define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
 210 #define CONFIG_SYS_PCI_MEM_SIZE 0x20000000
 211 #define CONFIG_SYS_PCI_IO_BASE         0xe2000000
 212
 213 #if defined(CONFIG_PCI)
 214 #define CONFIG_NET_MULTI
 215 #undef CONFIG_EEPRO100
 216 #define CONFIG_TULIP
 217 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 218 #if !defined(CONFIG_PCI_PNP)
 219 #define PCI_ENET0_IOADDR      0xe0000000
 220 #define PCI_ENET0_MEMADDR     0xe0000000
 221 #define PCI_IDSEL_NUMBER      0x0c      /*slot0->3(IDSEL)=12->15*/
 222 #endif
 223 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 224 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 225 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008
 226 #elif defined(CONFIG_TSEC_ENET)
 227 #define CONFIG_NET_MULTI        1
 228 #define CONFIG_MII              1       /* MII PHY management   */
 229 #define CONFIG_TSEC1    1
 230 #define CONFIG_HAS_ETH0
 231 #define CONFIG_TSEC1_NAME      "TSEC0"
 232 #define CONFIG_TSEC2    1
 233 #define CONFIG_HAS_ETH1
 234 #define CONFIG_TSEC2_NAME      "TSEC1"
 235 #define CONFIG_MPC85XX_FEC      1
 236 #define CONFIG_HAS_ETH2
 237 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 238 #define TSEC1_PHY_ADDR          7
 239 #define TSEC2_PHY_ADDR          4
 240 #define FEC_PHY_ADDR            2
 241 #define TSEC1_PHYIDX            0
 242 #define TSEC2_PHYIDX            0
 243 #define FEC_PHYIDX              0
 244 #define TSEC1_FLAGS             TSEC_GIGABIT
 245 #define TSEC2_FLAGS             TSEC_GIGABIT
 246 #define FEC_FLAGS               0
 247
 248 /* Options are: TSEC[0-1], FEC */
 249 #define CONFIG_ETHPRIME                "TSEC0"
 250
 251 #define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
 252 #define INTEL_LXT971_PHY        1
 253 #endif
 254
 255 /* Environment */
 256 #ifndef CONFIG_SYS_RAMBOOT
 257 #if defined(CONFIG_RAM_AS_FLASH)
 258 #define CONFIG_ENV_IS_NOWHERE
 259 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x100000)
 260 #define CONFIG_ENV_SIZE         0x2000
 261 #else
 262 #define CONFIG_ENV_IS_IN_FLASH  1
 263 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 264 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 265 #endif
 266 #define CONFIG_ENV_SIZE         0x2000
 267 #else
 268 /* #define CONFIG_SYS_NO_FLASH          1 */    /* Flash is not usable now      */
 269 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only     */
 270 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 271 #define CONFIG_ENV_SIZE         0x2000
 272 #endif
 273
 274 #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
 275 #define CONFIG_BOOTCOMMAND      "bootm 0xff800000 0xffa00000"
 276 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 277
 278 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 279 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 280
 281
 282 /*
 283  * BOOTP options
 284  */
 285 #define CONFIG_BOOTP_BOOTFILESIZE
 286 #define CONFIG_BOOTP_BOOTPATH
 287 #define CONFIG_BOOTP_GATEWAY
 288 #define CONFIG_BOOTP_HOSTNAME
 289
 290
 291 /*
 292  * Command line configuration.
 293  */
 294 #include <config_cmd_default.h>
 295
 296 #define CONFIG_CMD_PING
 297 #define CONFIG_CMD_I2C
 298 #define CONFIG_CMD_REGINFO
 299
 300 #if defined(CONFIG_PCI)
 301     #define CONFIG_CMD_PCI
 302 #endif
 303
 304 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
 305     #undef CONFIG_CMD_SAVEENV
 306     #undef CONFIG_CMD_LOADS
 307 #endif
 308
 309
 310 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 311
 312 /*
 313  * Miscellaneous configurable options
 314  */
 315 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 316 #define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
 317 #define CONFIG_SYS_PROMPT       "MPC8540EVAL=> "/* Monitor Command Prompt       */
 318 #if defined(CONFIG_CMD_KGDB)
 319 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 320 #else
 321 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 322 #endif
 323 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 324 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 325 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 326 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 327
 328 /*
 329  * For booting Linux, the board info and command line data
 330  * have to be in the first 8 MB of memory, since this is
 331  * the maximum mapped by the Linux kernel during initialization.
 332  */
 333 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 334
 335 /*
 336  * Internal Definitions
 337  *
 338  * Boot Flags
 339  */
 340 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 341 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 342
 343 #if defined(CONFIG_CMD_KGDB)
 344 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 345 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 346 #endif
 347
 348 /*****************************/
 349 /* Environment Configuration */
 350 /*****************************/
 351 /* The mac addresses for all ethernet interface */
 352 /* NOTE: change below for your network setting!!! */
 353 #if defined(CONFIG_TSEC_ENET)
 354 #define CONFIG_ETHADDR  00:01:af:07:9b:8a
 355 #define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
 356 #define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
 357 #endif
 358
 359 #define CONFIG_ROOTPATH  /nfsroot
 360 #define CONFIG_BOOTFILE  your.uImage
 361
 362 #define CONFIG_SERVERIP         192.168.101.1
 363 #define CONFIG_IPADDR           192.168.101.11
 364 #define CONFIG_GATEWAYIP        192.168.101.0
 365 #define CONFIG_NETMASK          255.255.255.0
 366
 367 #define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
 368
 369 #define CONFIG_HOSTNAME         MPC8540EVAL
 370
 371 #endif  /* __CONFIG_H */