include/configs/MPC8541CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8541cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_BOOKE            1       /* BOOKE */
  20 #define CONFIG_E500             1       /* BOOKE e500 family */
  21 #define CONFIG_CPM2             1       /* has CPM2 */
  22 #define CONFIG_MPC8541          1       /* MPC8541 specific */
  23 #define CONFIG_MPC8541CDS       1       /* MPC8541CDS board specific */
  24
  25 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  26
  27 #define CONFIG_PCI
  28 #define CONFIG_PCI_INDIRECT_BRIDGE
  29 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  30 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  31 #define CONFIG_ENV_OVERWRITE
  32
  33 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  34
  35 #define CONFIG_FSL_VIA
  36
  37 #ifndef __ASSEMBLY__
  38 extern unsigned long get_clock_freq(void);
  39 #endif
  40 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  41
  42 /*
  43  * These can be toggled for performance analysis, otherwise use default.
  44  */
  45 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  46 #define CONFIG_BTB                          /* toggle branch predition */
  47
  48 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  49 #define CONFIG_SYS_MEMTEST_END          0x00400000
  50
  51 #define CONFIG_SYS_CCSRBAR              0xe0000000
  52 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  53
  54 /* DDR Setup */
  55 #define CONFIG_SYS_FSL_DDR1
  56 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  57 #define CONFIG_DDR_SPD
  58 #undef CONFIG_FSL_DDR_INTERACTIVE
  59
  60 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  61
  62 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  63 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  64
  65 #define CONFIG_NUM_DDR_CONTROLLERS      1
  66 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  67 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  68
  69 /* I2C addresses of SPD EEPROMs */
  70 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  71
  72 /*
  73  * Make sure required options are set
  74  */
  75 #ifndef CONFIG_SPD_EEPROM
  76 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  77 #endif
  78
  79 #undef CONFIG_CLOCKS_IN_MHZ
  80
  81 /*
  82  * Local Bus Definitions
  83  */
  84
  85 /*
  86  * FLASH on the Local Bus
  87  * Two banks, 8M each, using the CFI driver.
  88  * Boot from BR0/OR0 bank at 0xff00_0000
  89  * Alternate BR1/OR1 bank at 0xff80_0000
  90  *
  91  * BR0, BR1:
  92  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  93  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  94  *    Port Size = 16 bits = BRx[19:20] = 10
  95  *    Use GPCM = BRx[24:26] = 000
  96  *    Valid = BRx[31] = 1
  97  *
  98  * 0    4    8    12   16   20   24   28
  99  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 100  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 101  *
 102  * OR0, OR1:
 103  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 104  *    Reserved ORx[17:18] = 11, confusion here?
 105  *    CSNT = ORx[20] = 1
 106  *    ACS = half cycle delay = ORx[21:22] = 11
 107  *    SCY = 6 = ORx[24:27] = 0110
 108  *    TRLX = use relaxed timing = ORx[29] = 1
 109  *    EAD = use external address latch delay = OR[31] = 1
 110  *
 111  * 0    4    8    12   16   20   24   28
 112  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 113  */
 114
 115 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 116
 117 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 118 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 119
 120 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 121 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 122
 123 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 126 #undef  CONFIG_SYS_FLASH_CHECKSUM
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 128 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 129
 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 131
 132 #define CONFIG_FLASH_CFI_DRIVER
 133 #define CONFIG_SYS_FLASH_CFI
 134 #define CONFIG_SYS_FLASH_EMPTY_INFO
 135
 136
 137 /*
 138  * SDRAM on the Local Bus
 139  */
 140 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 141 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 142
 143 /*
 144  * Base Register 2 and Option Register 2 configure SDRAM.
 145  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 146  *
 147  * For BR2, need:
 148  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 149  *    port-size = 32-bits = BR2[19:20] = 11
 150  *    no parity checking = BR2[21:22] = 00
 151  *    SDRAM for MSEL = BR2[24:26] = 011
 152  *    Valid = BR[31] = 1
 153  *
 154  * 0    4    8    12   16   20   24   28
 155  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 156  *
 157  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 158  * FIXME: the top 17 bits of BR2.
 159  */
 160
 161 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 162
 163 /*
 164  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 165  *
 166  * For OR2, need:
 167  *    64MB mask for AM, OR2[0:7] = 1111 1100
 168  *                 XAM, OR2[17:18] = 11
 169  *    9 columns OR2[19-21] = 010
 170  *    13 rows   OR2[23-25] = 100
 171  *    EAD set for extra time OR[31] = 1
 172  *
 173  * 0    4    8    12   16   20   24   28
 174  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 175  */
 176
 177 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 178
 179 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 180 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 181 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 182 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 183
 184 /*
 185  * Common settings for all Local Bus SDRAM commands.
 186  * At run time, either BSMA1516 (for CPU 1.1)
 187  *                  or BSMA1617 (for CPU 1.0) (old)
 188  * is OR'ed in too.
 189  */
 190 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 191                                 | LSDMR_PRETOACT7       \
 192                                 | LSDMR_ACTTORW7        \
 193                                 | LSDMR_BL8             \
 194                                 | LSDMR_WRC4            \
 195                                 | LSDMR_CL3             \
 196                                 | LSDMR_RFEN            \
 197                                 )
 198
 199 /*
 200  * The CADMUS registers are connected to CS3 on CDS.
 201  * The new memory map places CADMUS at 0xf8000000.
 202  *
 203  * For BR3, need:
 204  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 205  *    port-size = 8-bits  = BR[19:20] = 01
 206  *    no parity checking  = BR[21:22] = 00
 207  *    GPMC for MSEL       = BR[24:26] = 000
 208  *    Valid               = BR[31]    = 1
 209  *
 210  * 0    4    8    12   16   20   24   28
 211  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 212  *
 213  * For OR3, need:
 214  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 215  *    disable buffer ctrl OR[19]    = 0
 216  *    CSNT                OR[20]    = 1
 217  *    ACS                 OR[21:22] = 11
 218  *    XACS                OR[23]    = 1
 219  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 220  *    SETA                OR[28]    = 0
 221  *    TRLX                OR[29]    = 1
 222  *    EHTR                OR[30]    = 1
 223  *    EAD extra time      OR[31]    = 1
 224  *
 225  * 0    4    8    12   16   20   24   28
 226  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 227  */
 228
 229 #define CONFIG_FSL_CADMUS
 230
 231 #define CADMUS_BASE_ADDR 0xf8000000
 232 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 233 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 234
 235 #define CONFIG_SYS_INIT_RAM_LOCK        1
 236 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 237 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 238
 239 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241
 242 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 243 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 244
 245 /* Serial Port */
 246 #define CONFIG_CONS_INDEX     2
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #define CONFIG_SYS_NS16550_REG_SIZE    1
 249 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 250
 251 #define CONFIG_SYS_BAUDRATE_TABLE  \
 252         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 253
 254 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 255 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 256
 257 /* Use the HUSH parser */
 258 #define CONFIG_SYS_HUSH_PARSER
 259 #ifdef  CONFIG_SYS_HUSH_PARSER
 260 #endif
 261
 262 /*
 263  * I2C
 264  */
 265 #define CONFIG_SYS_I2C
 266 #define CONFIG_SYS_I2C_FSL
 267 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 268 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 269 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 270 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 271
 272 /* EEPROM */
 273 #define CONFIG_ID_EEPROM
 274 #define CONFIG_SYS_I2C_EEPROM_CCID
 275 #define CONFIG_SYS_ID_EEPROM
 276 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 277 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 278
 279 /*
 280  * General PCI
 281  * Memory space is mapped 1-1, but I/O space must start from 0.
 282  */
 283 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 284 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 285 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 286 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 287 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 288 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 289 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 290 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 291
 292 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 293 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 294 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 295 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 296 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 297 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 298 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 299 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000        /* 1M */
 300
 301 #ifdef CONFIG_LEGACY
 302 #define BRIDGE_ID 17
 303 #define VIA_ID 2
 304 #else
 305 #define BRIDGE_ID 28
 306 #define VIA_ID 4
 307 #endif
 308
 309 #if defined(CONFIG_PCI)
 310
 311 #define CONFIG_MPC85XX_PCI2
 312 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 313
 314 #undef CONFIG_EEPRO100
 315 #undef CONFIG_TULIP
 316
 317 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 318 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 319
 320 #endif  /* CONFIG_PCI */
 321
 322
 323 #if defined(CONFIG_TSEC_ENET)
 324
 325 #define CONFIG_MII              1       /* MII PHY management */
 326 #define CONFIG_TSEC1    1
 327 #define CONFIG_TSEC1_NAME       "TSEC0"
 328 #define CONFIG_TSEC2    1
 329 #define CONFIG_TSEC2_NAME       "TSEC1"
 330 #define TSEC1_PHY_ADDR          0
 331 #define TSEC2_PHY_ADDR          1
 332 #define TSEC1_PHYIDX            0
 333 #define TSEC2_PHYIDX            0
 334 #define TSEC1_FLAGS             TSEC_GIGABIT
 335 #define TSEC2_FLAGS             TSEC_GIGABIT
 336
 337 /* Options are: TSEC[0-1] */
 338 #define CONFIG_ETHPRIME         "TSEC0"
 339
 340 #endif  /* CONFIG_TSEC_ENET */
 341
 342 /*
 343  * Environment
 344  */
 345 #define CONFIG_ENV_IS_IN_FLASH  1
 346 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 347 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 348 #define CONFIG_ENV_SIZE         0x2000
 349
 350 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 351 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 352
 353 /*
 354  * BOOTP options
 355  */
 356 #define CONFIG_BOOTP_BOOTFILESIZE
 357 #define CONFIG_BOOTP_BOOTPATH
 358 #define CONFIG_BOOTP_GATEWAY
 359 #define CONFIG_BOOTP_HOSTNAME
 360
 361
 362 /*
 363  * Command line configuration.
 364  */
 365 #define CONFIG_CMD_PING
 366 #define CONFIG_CMD_I2C
 367 #define CONFIG_CMD_MII
 368 #define CONFIG_CMD_IRQ
 369 #define CONFIG_CMD_REGINFO
 370
 371 #if defined(CONFIG_PCI)
 372     #define CONFIG_CMD_PCI
 373 #endif
 374
 375
 376 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 377
 378 /*
 379  * Miscellaneous configurable options
 380  */
 381 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 382 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 383 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 384 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 385 #if defined(CONFIG_CMD_KGDB)
 386 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 387 #else
 388 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 389 #endif
 390 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 391 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 392 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 393
 394 /*
 395  * For booting Linux, the board info and command line data
 396  * have to be in the first 64 MB of memory, since this is
 397  * the maximum mapped by the Linux kernel during initialization.
 398  */
 399 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 400 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 401
 402 #if defined(CONFIG_CMD_KGDB)
 403 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 404 #endif
 405
 406 /*
 407  * Environment Configuration
 408  */
 409
 410 /* The mac addresses for all ethernet interface */
 411 #if defined(CONFIG_TSEC_ENET)
 412 #define CONFIG_HAS_ETH0
 413 #define CONFIG_HAS_ETH1
 414 #define CONFIG_HAS_ETH2
 415 #endif
 416
 417 #define CONFIG_IPADDR    192.168.1.253
 418
 419 #define CONFIG_HOSTNAME  unknown
 420 #define CONFIG_ROOTPATH  "/nfsroot"
 421 #define CONFIG_BOOTFILE  "your.uImage"
 422
 423 #define CONFIG_SERVERIP  192.168.1.1
 424 #define CONFIG_GATEWAYIP 192.168.1.1
 425 #define CONFIG_NETMASK   255.255.255.0
 426
 427 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 428
 429 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 430 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 431
 432 #define CONFIG_BAUDRATE 115200
 433
 434 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 435    "netdev=eth0\0"                                                      \
 436    "consoledev=ttyS1\0"                                                 \
 437    "ramdiskaddr=600000\0"                                               \
 438    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 439    "fdtaddr=400000\0"                                                   \
 440    "fdtfile=your.fdt.dtb\0"
 441
 442 #define CONFIG_NFSBOOTCOMMAND                                           \
 443    "setenv bootargs root=/dev/nfs rw "                                  \
 444       "nfsroot=$serverip:$rootpath "                                    \
 445       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 446       "console=$consoledev,$baudrate $othbootargs;"                     \
 447    "tftp $loadaddr $bootfile;"                                          \
 448    "tftp $fdtaddr $fdtfile;"                                            \
 449    "bootm $loadaddr - $fdtaddr"
 450
 451 #define CONFIG_RAMBOOTCOMMAND \
 452    "setenv bootargs root=/dev/ram rw "                                  \
 453       "console=$consoledev,$baudrate $othbootargs;"                     \
 454    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 455    "tftp $loadaddr $bootfile;"                                          \
 456    "bootm $loadaddr $ramdiskaddr"
 457
 458 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 459
 460 #endif  /* __CONFIG_H */