include/configs/MPC8541CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8541cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41 */
  36 #define CONFIG_CPM2             1       /* has CPM2 */
  37 #define CONFIG_MPC8541          1       /* MPC8541 specific */
  38 #define CONFIG_MPC8541CDS       1       /* MPC8541CDS board specific */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  41
  42 #define CONFIG_PCI
  43 #define CONFIG_PCI_INDIRECT_BRIDGE
  44 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  49
  50 #define CONFIG_FSL_VIA
  51
  52 #ifndef __ASSEMBLY__
  53 extern unsigned long get_clock_freq(void);
  54 #endif
  55 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  61 #define CONFIG_BTB                          /* toggle branch predition */
  62
  63 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  64 #define CONFIG_SYS_MEMTEST_END          0x00400000
  65
  66 #define CONFIG_SYS_CCSRBAR              0xe0000000
  67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  68
  69 /* DDR Setup */
  70 #define CONFIG_FSL_DDR1
  71 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  72 #define CONFIG_DDR_SPD
  73 #undef CONFIG_FSL_DDR_INTERACTIVE
  74
  75 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  76
  77 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  78 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  79
  80 #define CONFIG_NUM_DDR_CONTROLLERS      1
  81 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  82 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  83
  84 /* I2C addresses of SPD EEPROMs */
  85 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  86
  87 /*
  88  * Make sure required options are set
  89  */
  90 #ifndef CONFIG_SPD_EEPROM
  91 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  92 #endif
  93
  94 #undef CONFIG_CLOCKS_IN_MHZ
  95
  96 /*
  97  * Local Bus Definitions
  98  */
  99
 100 /*
 101  * FLASH on the Local Bus
 102  * Two banks, 8M each, using the CFI driver.
 103  * Boot from BR0/OR0 bank at 0xff00_0000
 104  * Alternate BR1/OR1 bank at 0xff80_0000
 105  *
 106  * BR0, BR1:
 107  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 108  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 109  *    Port Size = 16 bits = BRx[19:20] = 10
 110  *    Use GPCM = BRx[24:26] = 000
 111  *    Valid = BRx[31] = 1
 112  *
 113  * 0    4    8    12   16   20   24   28
 114  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 115  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 116  *
 117  * OR0, OR1:
 118  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 119  *    Reserved ORx[17:18] = 11, confusion here?
 120  *    CSNT = ORx[20] = 1
 121  *    ACS = half cycle delay = ORx[21:22] = 11
 122  *    SCY = 6 = ORx[24:27] = 0110
 123  *    TRLX = use relaxed timing = ORx[29] = 1
 124  *    EAD = use external address latch delay = OR[31] = 1
 125  *
 126  * 0    4    8    12   16   20   24   28
 127  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 128  */
 129
 130 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 131
 132 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 133 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 134
 135 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 136 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 137
 138 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 139 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 140 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 141 #undef  CONFIG_SYS_FLASH_CHECKSUM
 142 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 143 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 144
 145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 146
 147 #define CONFIG_FLASH_CFI_DRIVER
 148 #define CONFIG_SYS_FLASH_CFI
 149 #define CONFIG_SYS_FLASH_EMPTY_INFO
 150
 151
 152 /*
 153  * SDRAM on the Local Bus
 154  */
 155 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 156 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 157
 158 /*
 159  * Base Register 2 and Option Register 2 configure SDRAM.
 160  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 161  *
 162  * For BR2, need:
 163  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 164  *    port-size = 32-bits = BR2[19:20] = 11
 165  *    no parity checking = BR2[21:22] = 00
 166  *    SDRAM for MSEL = BR2[24:26] = 011
 167  *    Valid = BR[31] = 1
 168  *
 169  * 0    4    8    12   16   20   24   28
 170  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 171  *
 172  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 173  * FIXME: the top 17 bits of BR2.
 174  */
 175
 176 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 177
 178 /*
 179  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 180  *
 181  * For OR2, need:
 182  *    64MB mask for AM, OR2[0:7] = 1111 1100
 183  *                 XAM, OR2[17:18] = 11
 184  *    9 columns OR2[19-21] = 010
 185  *    13 rows   OR2[23-25] = 100
 186  *    EAD set for extra time OR[31] = 1
 187  *
 188  * 0    4    8    12   16   20   24   28
 189  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 190  */
 191
 192 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 193
 194 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 195 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 196 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 197 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 198
 199 /*
 200  * Common settings for all Local Bus SDRAM commands.
 201  * At run time, either BSMA1516 (for CPU 1.1)
 202  *                  or BSMA1617 (for CPU 1.0) (old)
 203  * is OR'ed in too.
 204  */
 205 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 206                                 | LSDMR_PRETOACT7       \
 207                                 | LSDMR_ACTTORW7        \
 208                                 | LSDMR_BL8             \
 209                                 | LSDMR_WRC4            \
 210                                 | LSDMR_CL3             \
 211                                 | LSDMR_RFEN            \
 212                                 )
 213
 214 /*
 215  * The CADMUS registers are connected to CS3 on CDS.
 216  * The new memory map places CADMUS at 0xf8000000.
 217  *
 218  * For BR3, need:
 219  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 220  *    port-size = 8-bits  = BR[19:20] = 01
 221  *    no parity checking  = BR[21:22] = 00
 222  *    GPMC for MSEL       = BR[24:26] = 000
 223  *    Valid               = BR[31]    = 1
 224  *
 225  * 0    4    8    12   16   20   24   28
 226  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 227  *
 228  * For OR3, need:
 229  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 230  *    disable buffer ctrl OR[19]    = 0
 231  *    CSNT                OR[20]    = 1
 232  *    ACS                 OR[21:22] = 11
 233  *    XACS                OR[23]    = 1
 234  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 235  *    SETA                OR[28]    = 0
 236  *    TRLX                OR[29]    = 1
 237  *    EHTR                OR[30]    = 1
 238  *    EAD extra time      OR[31]    = 1
 239  *
 240  * 0    4    8    12   16   20   24   28
 241  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 242  */
 243
 244 #define CONFIG_FSL_CADMUS
 245
 246 #define CADMUS_BASE_ADDR 0xf8000000
 247 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 248 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 249
 250 #define CONFIG_SYS_INIT_RAM_LOCK        1
 251 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 252 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 253
 254 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 255 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 256
 257 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 258 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 259
 260 /* Serial Port */
 261 #define CONFIG_CONS_INDEX     2
 262 #define CONFIG_SYS_NS16550
 263 #define CONFIG_SYS_NS16550_SERIAL
 264 #define CONFIG_SYS_NS16550_REG_SIZE    1
 265 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 266
 267 #define CONFIG_SYS_BAUDRATE_TABLE  \
 268         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 269
 270 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 271 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 272
 273 /* Use the HUSH parser */
 274 #define CONFIG_SYS_HUSH_PARSER
 275 #ifdef  CONFIG_SYS_HUSH_PARSER
 276 #endif
 277
 278 /* pass open firmware flat tree */
 279 #define CONFIG_OF_LIBFDT                1
 280 #define CONFIG_OF_BOARD_SETUP           1
 281 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 282
 283 /*
 284  * I2C
 285  */
 286 #define CONFIG_SYS_I2C
 287 #define CONFIG_SYS_I2C_FSL
 288 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 289 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 290 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 291 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 292
 293 /* EEPROM */
 294 #define CONFIG_ID_EEPROM
 295 #define CONFIG_SYS_I2C_EEPROM_CCID
 296 #define CONFIG_SYS_ID_EEPROM
 297 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 298 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 299
 300 /*
 301  * General PCI
 302  * Memory space is mapped 1-1, but I/O space must start from 0.
 303  */
 304 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 305 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 306 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 307 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 308 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 309 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 310 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 311 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 312
 313 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 314 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 315 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 316 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 317 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 318 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 319 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 320 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000        /* 1M */
 321
 322 #ifdef CONFIG_LEGACY
 323 #define BRIDGE_ID 17
 324 #define VIA_ID 2
 325 #else
 326 #define BRIDGE_ID 28
 327 #define VIA_ID 4
 328 #endif
 329
 330 #if defined(CONFIG_PCI)
 331
 332 #define CONFIG_MPC85XX_PCI2
 333 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 334
 335 #undef CONFIG_EEPRO100
 336 #undef CONFIG_TULIP
 337
 338 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 339 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 340
 341 #endif  /* CONFIG_PCI */
 342
 343
 344 #if defined(CONFIG_TSEC_ENET)
 345
 346 #define CONFIG_MII              1       /* MII PHY management */
 347 #define CONFIG_TSEC1    1
 348 #define CONFIG_TSEC1_NAME       "TSEC0"
 349 #define CONFIG_TSEC2    1
 350 #define CONFIG_TSEC2_NAME       "TSEC1"
 351 #define TSEC1_PHY_ADDR          0
 352 #define TSEC2_PHY_ADDR          1
 353 #define TSEC1_PHYIDX            0
 354 #define TSEC2_PHYIDX            0
 355 #define TSEC1_FLAGS             TSEC_GIGABIT
 356 #define TSEC2_FLAGS             TSEC_GIGABIT
 357
 358 /* Options are: TSEC[0-1] */
 359 #define CONFIG_ETHPRIME         "TSEC0"
 360
 361 #endif  /* CONFIG_TSEC_ENET */
 362
 363 /*
 364  * Environment
 365  */
 366 #define CONFIG_ENV_IS_IN_FLASH  1
 367 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 368 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 369 #define CONFIG_ENV_SIZE         0x2000
 370
 371 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 372 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 373
 374 /*
 375  * BOOTP options
 376  */
 377 #define CONFIG_BOOTP_BOOTFILESIZE
 378 #define CONFIG_BOOTP_BOOTPATH
 379 #define CONFIG_BOOTP_GATEWAY
 380 #define CONFIG_BOOTP_HOSTNAME
 381
 382
 383 /*
 384  * Command line configuration.
 385  */
 386 #include <config_cmd_default.h>
 387
 388 #define CONFIG_CMD_PING
 389 #define CONFIG_CMD_I2C
 390 #define CONFIG_CMD_MII
 391 #define CONFIG_CMD_ELF
 392 #define CONFIG_CMD_IRQ
 393 #define CONFIG_CMD_SETEXPR
 394 #define CONFIG_CMD_REGINFO
 395
 396 #if defined(CONFIG_PCI)
 397     #define CONFIG_CMD_PCI
 398 #endif
 399
 400
 401 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 402
 403 /*
 404  * Miscellaneous configurable options
 405  */
 406 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 407 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 408 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 409 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 410 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 411 #if defined(CONFIG_CMD_KGDB)
 412 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 413 #else
 414 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 415 #endif
 416 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 417 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 418 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 419 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 420
 421 /*
 422  * For booting Linux, the board info and command line data
 423  * have to be in the first 64 MB of memory, since this is
 424  * the maximum mapped by the Linux kernel during initialization.
 425  */
 426 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 427 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 428
 429 #if defined(CONFIG_CMD_KGDB)
 430 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 431 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 432 #endif
 433
 434 /*
 435  * Environment Configuration
 436  */
 437
 438 /* The mac addresses for all ethernet interface */
 439 #if defined(CONFIG_TSEC_ENET)
 440 #define CONFIG_HAS_ETH0
 441 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 442 #define CONFIG_HAS_ETH1
 443 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 444 #define CONFIG_HAS_ETH2
 445 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 446 #endif
 447
 448 #define CONFIG_IPADDR    192.168.1.253
 449
 450 #define CONFIG_HOSTNAME  unknown
 451 #define CONFIG_ROOTPATH  "/nfsroot"
 452 #define CONFIG_BOOTFILE  "your.uImage"
 453
 454 #define CONFIG_SERVERIP  192.168.1.1
 455 #define CONFIG_GATEWAYIP 192.168.1.1
 456 #define CONFIG_NETMASK   255.255.255.0
 457
 458 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 459
 460 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 461 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 462
 463 #define CONFIG_BAUDRATE 115200
 464
 465 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 466    "netdev=eth0\0"                                                      \
 467    "consoledev=ttyS1\0"                                                 \
 468    "ramdiskaddr=600000\0"                                               \
 469    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 470    "fdtaddr=400000\0"                                                   \
 471    "fdtfile=your.fdt.dtb\0"
 472
 473 #define CONFIG_NFSBOOTCOMMAND                                           \
 474    "setenv bootargs root=/dev/nfs rw "                                  \
 475       "nfsroot=$serverip:$rootpath "                                    \
 476       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 477       "console=$consoledev,$baudrate $othbootargs;"                     \
 478    "tftp $loadaddr $bootfile;"                                          \
 479    "tftp $fdtaddr $fdtfile;"                                            \
 480    "bootm $loadaddr - $fdtaddr"
 481
 482 #define CONFIG_RAMBOOTCOMMAND \
 483    "setenv bootargs root=/dev/ram rw "                                  \
 484       "console=$consoledev,$baudrate $othbootargs;"                     \
 485    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 486    "tftp $loadaddr $bootfile;"                                          \
 487    "bootm $loadaddr $ramdiskaddr"
 488
 489 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 490
 491 #endif  /* __CONFIG_H */