include/configs/MPC8541CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8541cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_SYS_GENERIC_BOARD
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_BOOKE            1       /* BOOKE */
  21 #define CONFIG_E500             1       /* BOOKE e500 family */
  22 #define CONFIG_CPM2             1       /* has CPM2 */
  23 #define CONFIG_MPC8541          1       /* MPC8541 specific */
  24 #define CONFIG_MPC8541CDS       1       /* MPC8541CDS board specific */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  27
  28 #define CONFIG_PCI
  29 #define CONFIG_PCI_INDIRECT_BRIDGE
  30 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  31 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  32 #define CONFIG_ENV_OVERWRITE
  33
  34 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  35
  36 #define CONFIG_FSL_VIA
  37
  38 #ifndef __ASSEMBLY__
  39 extern unsigned long get_clock_freq(void);
  40 #endif
  41 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  42
  43 /*
  44  * These can be toggled for performance analysis, otherwise use default.
  45  */
  46 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  47 #define CONFIG_BTB                          /* toggle branch predition */
  48
  49 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  50 #define CONFIG_SYS_MEMTEST_END          0x00400000
  51
  52 #define CONFIG_SYS_CCSRBAR              0xe0000000
  53 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  54
  55 /* DDR Setup */
  56 #define CONFIG_SYS_FSL_DDR1
  57 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  58 #define CONFIG_DDR_SPD
  59 #undef CONFIG_FSL_DDR_INTERACTIVE
  60
  61 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  62
  63 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  65
  66 #define CONFIG_NUM_DDR_CONTROLLERS      1
  67 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  68 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  69
  70 /* I2C addresses of SPD EEPROMs */
  71 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  72
  73 /*
  74  * Make sure required options are set
  75  */
  76 #ifndef CONFIG_SPD_EEPROM
  77 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  78 #endif
  79
  80 #undef CONFIG_CLOCKS_IN_MHZ
  81
  82 /*
  83  * Local Bus Definitions
  84  */
  85
  86 /*
  87  * FLASH on the Local Bus
  88  * Two banks, 8M each, using the CFI driver.
  89  * Boot from BR0/OR0 bank at 0xff00_0000
  90  * Alternate BR1/OR1 bank at 0xff80_0000
  91  *
  92  * BR0, BR1:
  93  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  94  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  95  *    Port Size = 16 bits = BRx[19:20] = 10
  96  *    Use GPCM = BRx[24:26] = 000
  97  *    Valid = BRx[31] = 1
  98  *
  99  * 0    4    8    12   16   20   24   28
 100  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 101  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 102  *
 103  * OR0, OR1:
 104  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 105  *    Reserved ORx[17:18] = 11, confusion here?
 106  *    CSNT = ORx[20] = 1
 107  *    ACS = half cycle delay = ORx[21:22] = 11
 108  *    SCY = 6 = ORx[24:27] = 0110
 109  *    TRLX = use relaxed timing = ORx[29] = 1
 110  *    EAD = use external address latch delay = OR[31] = 1
 111  *
 112  * 0    4    8    12   16   20   24   28
 113  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 114  */
 115
 116 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 117
 118 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 119 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 120
 121 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 122 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 123
 124 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 126 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 127 #undef  CONFIG_SYS_FLASH_CHECKSUM
 128 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 129 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 130
 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 132
 133 #define CONFIG_FLASH_CFI_DRIVER
 134 #define CONFIG_SYS_FLASH_CFI
 135 #define CONFIG_SYS_FLASH_EMPTY_INFO
 136
 137
 138 /*
 139  * SDRAM on the Local Bus
 140  */
 141 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 142 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 143
 144 /*
 145  * Base Register 2 and Option Register 2 configure SDRAM.
 146  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 147  *
 148  * For BR2, need:
 149  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 150  *    port-size = 32-bits = BR2[19:20] = 11
 151  *    no parity checking = BR2[21:22] = 00
 152  *    SDRAM for MSEL = BR2[24:26] = 011
 153  *    Valid = BR[31] = 1
 154  *
 155  * 0    4    8    12   16   20   24   28
 156  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 157  *
 158  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 159  * FIXME: the top 17 bits of BR2.
 160  */
 161
 162 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 163
 164 /*
 165  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 166  *
 167  * For OR2, need:
 168  *    64MB mask for AM, OR2[0:7] = 1111 1100
 169  *                 XAM, OR2[17:18] = 11
 170  *    9 columns OR2[19-21] = 010
 171  *    13 rows   OR2[23-25] = 100
 172  *    EAD set for extra time OR[31] = 1
 173  *
 174  * 0    4    8    12   16   20   24   28
 175  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 176  */
 177
 178 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 179
 180 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 181 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 182 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 183 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 184
 185 /*
 186  * Common settings for all Local Bus SDRAM commands.
 187  * At run time, either BSMA1516 (for CPU 1.1)
 188  *                  or BSMA1617 (for CPU 1.0) (old)
 189  * is OR'ed in too.
 190  */
 191 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 192                                 | LSDMR_PRETOACT7       \
 193                                 | LSDMR_ACTTORW7        \
 194                                 | LSDMR_BL8             \
 195                                 | LSDMR_WRC4            \
 196                                 | LSDMR_CL3             \
 197                                 | LSDMR_RFEN            \
 198                                 )
 199
 200 /*
 201  * The CADMUS registers are connected to CS3 on CDS.
 202  * The new memory map places CADMUS at 0xf8000000.
 203  *
 204  * For BR3, need:
 205  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 206  *    port-size = 8-bits  = BR[19:20] = 01
 207  *    no parity checking  = BR[21:22] = 00
 208  *    GPMC for MSEL       = BR[24:26] = 000
 209  *    Valid               = BR[31]    = 1
 210  *
 211  * 0    4    8    12   16   20   24   28
 212  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 213  *
 214  * For OR3, need:
 215  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 216  *    disable buffer ctrl OR[19]    = 0
 217  *    CSNT                OR[20]    = 1
 218  *    ACS                 OR[21:22] = 11
 219  *    XACS                OR[23]    = 1
 220  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 221  *    SETA                OR[28]    = 0
 222  *    TRLX                OR[29]    = 1
 223  *    EHTR                OR[30]    = 1
 224  *    EAD extra time      OR[31]    = 1
 225  *
 226  * 0    4    8    12   16   20   24   28
 227  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 228  */
 229
 230 #define CONFIG_FSL_CADMUS
 231
 232 #define CADMUS_BASE_ADDR 0xf8000000
 233 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 234 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 235
 236 #define CONFIG_SYS_INIT_RAM_LOCK        1
 237 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 238 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 239
 240 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 241 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 242
 243 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 244 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 245
 246 /* Serial Port */
 247 #define CONFIG_CONS_INDEX     2
 248 #define CONFIG_SYS_NS16550
 249 #define CONFIG_SYS_NS16550_SERIAL
 250 #define CONFIG_SYS_NS16550_REG_SIZE    1
 251 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 252
 253 #define CONFIG_SYS_BAUDRATE_TABLE  \
 254         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 255
 256 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 257 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 258
 259 /* Use the HUSH parser */
 260 #define CONFIG_SYS_HUSH_PARSER
 261 #ifdef  CONFIG_SYS_HUSH_PARSER
 262 #endif
 263
 264 /* pass open firmware flat tree */
 265 #define CONFIG_OF_LIBFDT                1
 266 #define CONFIG_OF_BOARD_SETUP           1
 267 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 268
 269 /*
 270  * I2C
 271  */
 272 #define CONFIG_SYS_I2C
 273 #define CONFIG_SYS_I2C_FSL
 274 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 275 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 276 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 277 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 278
 279 /* EEPROM */
 280 #define CONFIG_ID_EEPROM
 281 #define CONFIG_SYS_I2C_EEPROM_CCID
 282 #define CONFIG_SYS_ID_EEPROM
 283 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 284 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 285
 286 /*
 287  * General PCI
 288  * Memory space is mapped 1-1, but I/O space must start from 0.
 289  */
 290 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 291 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 292 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 293 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 294 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 295 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 296 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 297 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 298
 299 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 300 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 301 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 302 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 303 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 304 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 305 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 306 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000        /* 1M */
 307
 308 #ifdef CONFIG_LEGACY
 309 #define BRIDGE_ID 17
 310 #define VIA_ID 2
 311 #else
 312 #define BRIDGE_ID 28
 313 #define VIA_ID 4
 314 #endif
 315
 316 #if defined(CONFIG_PCI)
 317
 318 #define CONFIG_MPC85XX_PCI2
 319 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 320
 321 #undef CONFIG_EEPRO100
 322 #undef CONFIG_TULIP
 323
 324 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 325 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 326
 327 #endif  /* CONFIG_PCI */
 328
 329
 330 #if defined(CONFIG_TSEC_ENET)
 331
 332 #define CONFIG_MII              1       /* MII PHY management */
 333 #define CONFIG_TSEC1    1
 334 #define CONFIG_TSEC1_NAME       "TSEC0"
 335 #define CONFIG_TSEC2    1
 336 #define CONFIG_TSEC2_NAME       "TSEC1"
 337 #define TSEC1_PHY_ADDR          0
 338 #define TSEC2_PHY_ADDR          1
 339 #define TSEC1_PHYIDX            0
 340 #define TSEC2_PHYIDX            0
 341 #define TSEC1_FLAGS             TSEC_GIGABIT
 342 #define TSEC2_FLAGS             TSEC_GIGABIT
 343
 344 /* Options are: TSEC[0-1] */
 345 #define CONFIG_ETHPRIME         "TSEC0"
 346
 347 #endif  /* CONFIG_TSEC_ENET */
 348
 349 /*
 350  * Environment
 351  */
 352 #define CONFIG_ENV_IS_IN_FLASH  1
 353 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 354 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 355 #define CONFIG_ENV_SIZE         0x2000
 356
 357 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 358 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 359
 360 /*
 361  * BOOTP options
 362  */
 363 #define CONFIG_BOOTP_BOOTFILESIZE
 364 #define CONFIG_BOOTP_BOOTPATH
 365 #define CONFIG_BOOTP_GATEWAY
 366 #define CONFIG_BOOTP_HOSTNAME
 367
 368
 369 /*
 370  * Command line configuration.
 371  */
 372 #define CONFIG_CMD_PING
 373 #define CONFIG_CMD_I2C
 374 #define CONFIG_CMD_MII
 375 #define CONFIG_CMD_ELF
 376 #define CONFIG_CMD_IRQ
 377 #define CONFIG_CMD_REGINFO
 378
 379 #if defined(CONFIG_PCI)
 380     #define CONFIG_CMD_PCI
 381 #endif
 382
 383
 384 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 385
 386 /*
 387  * Miscellaneous configurable options
 388  */
 389 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 390 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 391 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 392 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 393 #if defined(CONFIG_CMD_KGDB)
 394 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 395 #else
 396 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 397 #endif
 398 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 399 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 400 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 401
 402 /*
 403  * For booting Linux, the board info and command line data
 404  * have to be in the first 64 MB of memory, since this is
 405  * the maximum mapped by the Linux kernel during initialization.
 406  */
 407 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 408 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 409
 410 #if defined(CONFIG_CMD_KGDB)
 411 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 412 #endif
 413
 414 /*
 415  * Environment Configuration
 416  */
 417
 418 /* The mac addresses for all ethernet interface */
 419 #if defined(CONFIG_TSEC_ENET)
 420 #define CONFIG_HAS_ETH0
 421 #define CONFIG_HAS_ETH1
 422 #define CONFIG_HAS_ETH2
 423 #endif
 424
 425 #define CONFIG_IPADDR    192.168.1.253
 426
 427 #define CONFIG_HOSTNAME  unknown
 428 #define CONFIG_ROOTPATH  "/nfsroot"
 429 #define CONFIG_BOOTFILE  "your.uImage"
 430
 431 #define CONFIG_SERVERIP  192.168.1.1
 432 #define CONFIG_GATEWAYIP 192.168.1.1
 433 #define CONFIG_NETMASK   255.255.255.0
 434
 435 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 436
 437 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 438 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 439
 440 #define CONFIG_BAUDRATE 115200
 441
 442 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 443    "netdev=eth0\0"                                                      \
 444    "consoledev=ttyS1\0"                                                 \
 445    "ramdiskaddr=600000\0"                                               \
 446    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 447    "fdtaddr=400000\0"                                                   \
 448    "fdtfile=your.fdt.dtb\0"
 449
 450 #define CONFIG_NFSBOOTCOMMAND                                           \
 451    "setenv bootargs root=/dev/nfs rw "                                  \
 452       "nfsroot=$serverip:$rootpath "                                    \
 453       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 454       "console=$consoledev,$baudrate $othbootargs;"                     \
 455    "tftp $loadaddr $bootfile;"                                          \
 456    "tftp $fdtaddr $fdtfile;"                                            \
 457    "bootm $loadaddr - $fdtaddr"
 458
 459 #define CONFIG_RAMBOOTCOMMAND \
 460    "setenv bootargs root=/dev/ram rw "                                  \
 461       "console=$consoledev,$baudrate $othbootargs;"                     \
 462    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 463    "tftp $loadaddr $bootfile;"                                          \
 464    "bootm $loadaddr $ramdiskaddr"
 465
 466 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 467
 468 #endif  /* __CONFIG_H */