include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8544ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8544          1
  35 #define CONFIG_MPC8544DS        1
  36
  37 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  38 #define CONFIG_PCI1             1       /* PCI controller 1 */
  39 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  40 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  41 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  42 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  43 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  44 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  45
  46 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  47
  48 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  51
  52 /*
  53  * When initializing flash, if we cannot find the manufacturer ID,
  54  * assume this is the AMD flash associated with the CDS board.
  55  * This allows booting from a promjet.
  56  */
  57 #define CONFIG_ASSUME_AMD_FLASH
  58
  59 #ifndef __ASSEMBLY__
  60 extern unsigned long get_board_sys_clk(unsigned long dummy);
  61 #endif
  62 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  63
  64 /*
  65  * These can be toggled for performance analysis, otherwise use default.
  66  */
  67 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  68 #define CONFIG_BTB                      /* toggle branch predition */
  69
  70 /*
  71  * Only possible on E500 Version 2 or newer cores.
  72  */
  73 #define CONFIG_ENABLE_36BIT_PHYS        1
  74
  75 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  76 #define CONFIG_SYS_MEMTEST_END          0x00400000
  77 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  78
  79 /*
  80  * Base addresses -- Note these are effective addresses where the
  81  * actual resources get mapped (not physical addresses)
  82  */
  83 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  84 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  85 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  86 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  87
  88 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR+0x8000)
  89 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
  90 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
  91 #define CONFIG_SYS_PCIE3_ADDR           (CONFIG_SYS_CCSRBAR+0xb000)
  92
  93 /* DDR Setup */
  94 #define CONFIG_FSL_DDR2
  95 #undef CONFIG_FSL_DDR_INTERACTIVE
  96 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  97 #define CONFIG_DDR_SPD
  98
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 100 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 101
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104 #define CONFIG_VERY_BIG_RAM
 105
 106 #define CONFIG_NUM_DDR_CONTROLLERS      1
 107 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 108 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 109
 110 /* I2C addresses of SPD EEPROMs */
 111 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 112
 113 /* Make sure required options are set */
 114 #ifndef CONFIG_SPD_EEPROM
 115 #error ("CONFIG_SPD_EEPROM is required")
 116 #endif
 117
 118 #undef CONFIG_CLOCKS_IN_MHZ
 119
 120 /*
 121  * Memory map
 122  *
 123  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 124  *
 125  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 126  *
 127  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 128  *
 129  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
 130  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 131  *
 132  * Localbus cacheable
 133  *
 134  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
 135  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
 136  *
 137  * Localbus non-cacheable
 138  *
 139  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
 140  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
 141  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
 142  *
 143  */
 144
 145 /*
 146  * Local Bus Definitions
 147  */
 148 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* boot TLB */
 149
 150 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of FLASH 8M */
 151
 152 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 153 #define CONFIG_SYS_BR1_PRELIM           0xfe801001
 154
 155 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 156 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 157
 158 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 159
 160 #define CONFIG_SYS_FLASH_QUIET_TEST
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 162 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 163 #undef  CONFIG_SYS_FLASH_CHECKSUM
 164 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 165 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 166 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 167
 168 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 169
 170 #define CONFIG_FLASH_CFI_DRIVER
 171 #define CONFIG_SYS_FLASH_CFI
 172 #define CONFIG_SYS_FLASH_EMPTY_INFO
 173
 174 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000
 175
 176 #define CONFIG_SYS_BR2_PRELIM           0xf8201001      /* port size 16bit */
 177 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 178
 179 #define CONFIG_SYS_BR3_PRELIM           0xf8100801      /* port size 8bit */
 180 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 181
 182 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 183 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 184 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 185 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 186 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 187 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 188 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 189                                          * register */
 190 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 191 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 192 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 193 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 194 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 195 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 196 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 197 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 198 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 199 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 200 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 201 #define PIXIS_VSPEED2           0x1d    /* VELA VSpeed 2 */
 202 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 203 #define PIXIS_VSPEED2_TSEC1SER  0x2
 204 #define PIXIS_VSPEED2_TSEC3SER  0x1
 205 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 206 #define PIXIS_VCFGEN1_TSEC3SER  0x40
 207 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
 208 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 209
 210
 211 #define CONFIG_SYS_INIT_RAM_LOCK      1
 212 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 213 #define CONFIG_SYS_INIT_RAM_END       0x00004000      /* End of used area in RAM */
 214
 215
 216 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 218 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 219
 220 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 221 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 222
 223 /* Serial Port - controlled on board with jumper J8
 224  * open - index 2
 225  * shorted - index 1
 226  */
 227 #define CONFIG_CONS_INDEX       1
 228 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 229 #define CONFIG_SYS_NS16550
 230 #define CONFIG_SYS_NS16550_SERIAL
 231 #define CONFIG_SYS_NS16550_REG_SIZE     1
 232 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 233
 234 #define CONFIG_SYS_BAUDRATE_TABLE       \
 235         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 236
 237 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 238 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 239
 240 /* Use the HUSH parser */
 241 #define CONFIG_SYS_HUSH_PARSER
 242 #ifdef  CONFIG_SYS_HUSH_PARSER
 243 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 244 #endif
 245
 246 /* pass open firmware flat tree */
 247 #define CONFIG_OF_LIBFDT                1
 248 #define CONFIG_OF_BOARD_SETUP           1
 249 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 250
 251 #define CONFIG_SYS_64BIT_STRTOUL                1
 252 #define CONFIG_SYS_64BIT_VSPRINTF               1
 253
 254 /* I2C */
 255 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 256 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 257 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 258 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 260 #define CONFIG_SYS_I2C_SLAVE            0x7F
 261 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 262 #define CONFIG_SYS_I2C_OFFSET           0x3100
 263
 264 /*
 265  * General PCI
 266  * Memory space is mapped 1-1, but I/O space must start from 0.
 267  */
 268 #define CONFIG_SYS_PCIE_VIRT            0x80000000      /* 1G PCIE TLB */
 269 #define CONFIG_SYS_PCIE_PHYS            0x80000000      /* 1G PCIE TLB */
 270 #define CONFIG_SYS_PCI_VIRT             0xc0000000      /* 512M PCI TLB */
 271 #define CONFIG_SYS_PCI_PHYS             0xc0000000      /* 512M PCI TLB */
 272
 273 #define CONFIG_SYS_PCI1_MEM_VIRT        0xc0000000
 274 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
 275 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc0000000
 276 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 277 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 278 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 279 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 280 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64k */
 281
 282 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 283 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x80000000
 284 #define CONFIG_SYS_PCIE2_MEM_BUS        0x80000000
 285 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x80000000
 286 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 287 #define CONFIG_SYS_PCIE2_IO_VIRT        0xe1010000
 288 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 289 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe1010000
 290 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 291
 292 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 293 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 294 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 295 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 296 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 297 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe1020000
 298 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 299 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe1020000
 300 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 301
 302 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 303 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 304 #define CONFIG_SYS_PCIE3_MEM_BUS        0xb0000000
 305 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xb0000000
 306 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x00100000      /* 1M */
 307 #define CONFIG_SYS_PCIE3_IO_VIRT        0xb0100000      /* reuse mem LAW */
 308 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 309 #define CONFIG_SYS_PCIE3_IO_PHYS        0xb0100000      /* reuse mem LAW */
 310 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00100000      /* 1M */
 311 #define CONFIG_SYS_PCIE3_MEM_VIRT2      0xb0200000
 312 #define CONFIG_SYS_PCIE3_MEM_BUS2       0xb0200000
 313 #define CONFIG_SYS_PCIE3_MEM_PHYS2      0xb0200000
 314 #define CONFIG_SYS_PCIE3_MEM_SIZE2      0x00200000      /* 1M */
 315
 316 #if defined(CONFIG_PCI)
 317
 318 /*PCIE video card used*/
 319 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 320
 321 /*PCI video card used*/
 322 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 323
 324 /* video */
 325 #define CONFIG_VIDEO
 326
 327 #if defined(CONFIG_VIDEO)
 328 #define CONFIG_BIOSEMU
 329 #define CONFIG_CFB_CONSOLE
 330 #define CONFIG_VIDEO_SW_CURSOR
 331 #define CONFIG_VGA_AS_SINGLE_DEVICE
 332 #define CONFIG_ATI_RADEON_FB
 333 #define CONFIG_VIDEO_LOGO
 334 /*#define CONFIG_CONSOLE_CURSOR*/
 335 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 336 #endif
 337
 338 #define CONFIG_NET_MULTI
 339 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 340
 341 #undef CONFIG_EEPRO100
 342 #undef CONFIG_TULIP
 343 #define CONFIG_RTL8139
 344
 345 #ifndef CONFIG_PCI_PNP
 346         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 347         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 348         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 349 #endif
 350
 351 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 352 #define CONFIG_DOS_PARTITION
 353 #define CONFIG_SCSI_AHCI
 354
 355 #ifdef CONFIG_SCSI_AHCI
 356 #define CONFIG_SATA_ULI5288
 357 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 358 #define CONFIG_SYS_SCSI_MAX_LUN 1
 359 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 360 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 361 #endif /* SCSCI */
 362
 363 #endif  /* CONFIG_PCI */
 364
 365
 366 #if defined(CONFIG_TSEC_ENET)
 367
 368 #ifndef CONFIG_NET_MULTI
 369 #define CONFIG_NET_MULTI        1
 370 #endif
 371
 372 #define CONFIG_MII              1       /* MII PHY management */
 373 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 374 #define CONFIG_TSEC1    1
 375 #define CONFIG_TSEC1_NAME       "eTSEC1"
 376 #define CONFIG_TSEC3    1
 377 #define CONFIG_TSEC3_NAME       "eTSEC3"
 378
 379 #define CONFIG_PIXIS_SGMII_CMD
 380 #define CONFIG_FSL_SGMII_RISER  1
 381 #define SGMII_RISER_PHY_OFFSET  0x1c
 382
 383 #define TSEC1_PHY_ADDR          0
 384 #define TSEC3_PHY_ADDR          1
 385
 386 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 387 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 388
 389 #define TSEC1_PHYIDX            0
 390 #define TSEC3_PHYIDX            0
 391
 392 #define CONFIG_ETHPRIME         "eTSEC1"
 393
 394 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 395 #endif  /* CONFIG_TSEC_ENET */
 396
 397 /*
 398  * Environment
 399  */
 400 #define CONFIG_ENV_IS_IN_FLASH  1
 401 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 402 #define CONFIG_ENV_ADDR         0xfff80000
 403 #else
 404 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x70000)
 405 #endif
 406 #define CONFIG_ENV_SIZE         0x2000
 407 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) */
 408
 409 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 410 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 411
 412 /*
 413  * BOOTP options
 414  */
 415 #define CONFIG_BOOTP_BOOTFILESIZE
 416 #define CONFIG_BOOTP_BOOTPATH
 417 #define CONFIG_BOOTP_GATEWAY
 418 #define CONFIG_BOOTP_HOSTNAME
 419
 420
 421 /*
 422  * Command line configuration.
 423  */
 424 #include <config_cmd_default.h>
 425
 426 #define CONFIG_CMD_PING
 427 #define CONFIG_CMD_I2C
 428 #define CONFIG_CMD_MII
 429 #define CONFIG_CMD_ELF
 430 #define CONFIG_CMD_IRQ
 431 #define CONFIG_CMD_SETEXPR
 432
 433 #if defined(CONFIG_PCI)
 434     #define CONFIG_CMD_PCI
 435     #define CONFIG_CMD_BEDBUG
 436     #define CONFIG_CMD_NET
 437     #define CONFIG_CMD_SCSI
 438     #define CONFIG_CMD_EXT2
 439 #endif
 440
 441
 442 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 443
 444 /*
 445  * Miscellaneous configurable options
 446  */
 447 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 448 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 449 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 450 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 451 #if defined(CONFIG_CMD_KGDB)
 452 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 453 #else
 454 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 455 #endif
 456 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 457 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 458 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 459 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 460
 461 /*
 462  * For booting Linux, the board info and command line data
 463  * have to be in the first 16 MB of memory, since this is
 464  * the maximum mapped by the Linux kernel during initialization.
 465  */
 466 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 467
 468 /*
 469  * Internal Definitions
 470  *
 471  * Boot Flags
 472  */
 473 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 474 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 475
 476 #if defined(CONFIG_CMD_KGDB)
 477 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 478 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 479 #endif
 480
 481 /*
 482  * Environment Configuration
 483  */
 484
 485 /* The mac addresses for all ethernet interface */
 486 #if defined(CONFIG_TSEC_ENET)
 487 #define CONFIG_HAS_ETH0
 488 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 489 #define CONFIG_HAS_ETH1
 490 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 491 #endif
 492
 493 #define CONFIG_IPADDR   192.168.1.251
 494
 495 #define CONFIG_HOSTNAME 8544ds_unknown
 496 #define CONFIG_ROOTPATH /nfs/mpc85xx
 497 #define CONFIG_BOOTFILE 8544ds/uImage.uboot
 498 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 499
 500 #define CONFIG_SERVERIP 192.168.1.1
 501 #define CONFIG_GATEWAYIP 192.168.1.1
 502 #define CONFIG_NETMASK  255.255.0.0
 503
 504 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 505
 506 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 507 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 508
 509 #define CONFIG_BAUDRATE 115200
 510
 511 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 512  "netdev=eth0\0"                                                \
 513  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 514  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 515         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 516         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 517         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 518         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 519         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 520  "consoledev=ttyS0\0"                           \
 521  "ramdiskaddr=2000000\0"                        \
 522  "ramdiskfile=8544ds/ramdisk.uboot\0"           \
 523  "fdtaddr=c00000\0"                             \
 524  "fdtfile=8544ds/mpc8544ds.dtb\0"               \
 525  "bdev=sda3\0"
 526
 527 #define CONFIG_NFSBOOTCOMMAND           \
 528  "setenv bootargs root=/dev/nfs rw "    \
 529  "nfsroot=$serverip:$rootpath "         \
 530  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 531  "console=$consoledev,$baudrate $othbootargs;"  \
 532  "tftp $loadaddr $bootfile;"            \
 533  "tftp $fdtaddr $fdtfile;"              \
 534  "bootm $loadaddr - $fdtaddr"
 535
 536 #define CONFIG_RAMBOOTCOMMAND           \
 537  "setenv bootargs root=/dev/ram rw "    \
 538  "console=$consoledev,$baudrate $othbootargs;"  \
 539  "tftp $ramdiskaddr $ramdiskfile;"      \
 540  "tftp $loadaddr $bootfile;"            \
 541  "tftp $fdtaddr $fdtfile;"              \
 542  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 543
 544 #define CONFIG_BOOTCOMMAND              \
 545  "setenv bootargs root=/dev/$bdev rw "  \
 546  "console=$consoledev,$baudrate $othbootargs;"  \
 547  "tftp $loadaddr $bootfile;"            \
 548  "tftp $fdtaddr $fdtfile;"              \
 549  "bootm $loadaddr - $fdtaddr"
 550
 551 #endif  /* __CONFIG_H */