include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8544ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_BOOKE            1       /* BOOKE */
  16 #define CONFIG_E500             1       /* BOOKE e500 family */
  17 #define CONFIG_MPC8544          1
  18 #define CONFIG_MPC8544DS        1
  19
  20 #ifndef CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  22 #endif
  23
  24 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  25 #define CONFIG_PCI1             1       /* PCI controller 1 */
  26 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  27 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  28 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  29 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  30 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  31 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  32 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  33
  34 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  35 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  36
  37 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  38 #define CONFIG_ENV_OVERWRITE
  39 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  40
  41 #ifndef __ASSEMBLY__
  42 extern unsigned long get_board_sys_clk(unsigned long dummy);
  43 #endif
  44 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  45
  46 /*
  47  * These can be toggled for performance analysis, otherwise use default.
  48  */
  49 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  50 #define CONFIG_BTB                      /* toggle branch predition */
  51
  52 /*
  53  * Only possible on E500 Version 2 or newer cores.
  54  */
  55 #define CONFIG_ENABLE_36BIT_PHYS        1
  56
  57 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  58 #define CONFIG_SYS_MEMTEST_END          0x00400000
  59 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  60
  61 #define CONFIG_SYS_CCSRBAR              0xe0000000
  62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  63
  64 /* DDR Setup */
  65 #define CONFIG_SYS_FSL_DDR2
  66 #undef CONFIG_FSL_DDR_INTERACTIVE
  67 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  68 #define CONFIG_DDR_SPD
  69
  70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  71 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  72
  73 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  75 #define CONFIG_VERY_BIG_RAM
  76
  77 #define CONFIG_NUM_DDR_CONTROLLERS      1
  78 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  79 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  80
  81 /* I2C addresses of SPD EEPROMs */
  82 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  83
  84 /* Make sure required options are set */
  85 #ifndef CONFIG_SPD_EEPROM
  86 #error ("CONFIG_SPD_EEPROM is required")
  87 #endif
  88
  89 #undef CONFIG_CLOCKS_IN_MHZ
  90
  91 /*
  92  * Memory map
  93  *
  94  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  95  *
  96  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  97  *
  98  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  99  *
 100  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
 101  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 102  *
 103  * Localbus cacheable
 104  *
 105  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
 106  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
 107  *
 108  * Localbus non-cacheable
 109  *
 110  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
 111  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
 112  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
 113  *
 114  */
 115
 116 /*
 117  * Local Bus Definitions
 118  */
 119 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* boot TLB */
 120
 121 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of FLASH 8M */
 122
 123 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 124 #define CONFIG_SYS_BR1_PRELIM           0xfe801001
 125
 126 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 127 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 128
 129 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 130
 131 #define CONFIG_SYS_FLASH_QUIET_TEST
 132 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 133 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 134 #undef  CONFIG_SYS_FLASH_CHECKSUM
 135 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 136 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 137 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 138
 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 140
 141 #define CONFIG_FLASH_CFI_DRIVER
 142 #define CONFIG_SYS_FLASH_CFI
 143 #define CONFIG_SYS_FLASH_EMPTY_INFO
 144
 145 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000
 146
 147 #define CONFIG_SYS_BR2_PRELIM           0xf8201001      /* port size 16bit */
 148 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 149
 150 #define CONFIG_SYS_BR3_PRELIM           0xf8100801      /* port size 8bit */
 151 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 152
 153 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 154 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 155 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 156 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 157 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 158 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 159 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 160                                          * register */
 161 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 162 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 163 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 164 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 165 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 166 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 167 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 168 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 169 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 170 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 171 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 172 #define PIXIS_VSPEED2           0x1d    /* VELA VSpeed 2 */
 173 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 174 #define PIXIS_VSPEED2_TSEC1SER  0x2
 175 #define PIXIS_VSPEED2_TSEC3SER  0x1
 176 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 177 #define PIXIS_VCFGEN1_TSEC3SER  0x40
 178 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
 179 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 180
 181
 182 #define CONFIG_SYS_INIT_RAM_LOCK      1
 183 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 184 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
 185
 186
 187 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 188 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 189
 190 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 191 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 192
 193 /* Serial Port - controlled on board with jumper J8
 194  * open - index 2
 195  * shorted - index 1
 196  */
 197 #define CONFIG_CONS_INDEX       1
 198 #define CONFIG_SYS_NS16550
 199 #define CONFIG_SYS_NS16550_SERIAL
 200 #define CONFIG_SYS_NS16550_REG_SIZE     1
 201 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 202
 203 #define CONFIG_SYS_BAUDRATE_TABLE       \
 204         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 205
 206 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 207 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 208
 209 /* Use the HUSH parser */
 210 #define CONFIG_SYS_HUSH_PARSER
 211
 212 /* pass open firmware flat tree */
 213 #define CONFIG_OF_LIBFDT                1
 214 #define CONFIG_OF_BOARD_SETUP           1
 215 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 216
 217 /* I2C */
 218 #define CONFIG_SYS_I2C
 219 #define CONFIG_SYS_I2C_FSL
 220 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 221 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 222 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 223 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 224 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 225
 226 /*
 227  * General PCI
 228  * Memory space is mapped 1-1, but I/O space must start from 0.
 229  */
 230 #define CONFIG_SYS_PCIE_VIRT            0x80000000      /* 1G PCIE TLB */
 231 #define CONFIG_SYS_PCIE_PHYS            0x80000000      /* 1G PCIE TLB */
 232 #define CONFIG_SYS_PCI_VIRT             0xc0000000      /* 512M PCI TLB */
 233 #define CONFIG_SYS_PCI_PHYS             0xc0000000      /* 512M PCI TLB */
 234
 235 #define CONFIG_SYS_PCI1_MEM_VIRT        0xc0000000
 236 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
 237 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc0000000
 238 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 239 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 240 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 241 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 242 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64k */
 243
 244 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 245 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 246 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x80000000
 247 #define CONFIG_SYS_PCIE2_MEM_BUS        0x80000000
 248 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x80000000
 249 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 250 #define CONFIG_SYS_PCIE2_IO_VIRT        0xe1010000
 251 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 252 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe1010000
 253 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 254
 255 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 256 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 257 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 258 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 259 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 260 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 261 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe1020000
 262 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 263 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe1020000
 264 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 265
 266 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 267 #define CONFIG_SYS_PCIE3_NAME           "ULI"
 268 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 269 #define CONFIG_SYS_PCIE3_MEM_BUS        0xb0000000
 270 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xb0000000
 271 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x00100000      /* 1M */
 272 #define CONFIG_SYS_PCIE3_IO_VIRT        0xb0100000      /* reuse mem LAW */
 273 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 274 #define CONFIG_SYS_PCIE3_IO_PHYS        0xb0100000      /* reuse mem LAW */
 275 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00100000      /* 1M */
 276 #define CONFIG_SYS_PCIE3_MEM_VIRT2      0xb0200000
 277 #define CONFIG_SYS_PCIE3_MEM_BUS2       0xb0200000
 278 #define CONFIG_SYS_PCIE3_MEM_PHYS2      0xb0200000
 279 #define CONFIG_SYS_PCIE3_MEM_SIZE2      0x00200000      /* 1M */
 280
 281 #if defined(CONFIG_PCI)
 282
 283 /*PCIE video card used*/
 284 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 285
 286 /*PCI video card used*/
 287 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 288
 289 /* video */
 290 #define CONFIG_VIDEO
 291
 292 #if defined(CONFIG_VIDEO)
 293 #define CONFIG_BIOSEMU
 294 #define CONFIG_CFB_CONSOLE
 295 #define CONFIG_VIDEO_SW_CURSOR
 296 #define CONFIG_VGA_AS_SINGLE_DEVICE
 297 #define CONFIG_ATI_RADEON_FB
 298 #define CONFIG_VIDEO_LOGO
 299 /*#define CONFIG_CONSOLE_CURSOR*/
 300 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 301 #endif
 302
 303 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 304
 305 #undef CONFIG_EEPRO100
 306 #undef CONFIG_TULIP
 307 #define CONFIG_RTL8139
 308
 309 #ifndef CONFIG_PCI_PNP
 310         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 311         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 312         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 313 #endif
 314
 315 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 316 #define CONFIG_DOS_PARTITION
 317 #define CONFIG_SCSI_AHCI
 318
 319 #ifdef CONFIG_SCSI_AHCI
 320 #define CONFIG_LIBATA
 321 #define CONFIG_SATA_ULI5288
 322 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 323 #define CONFIG_SYS_SCSI_MAX_LUN 1
 324 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 325 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 326 #endif /* SCSCI */
 327
 328 #endif  /* CONFIG_PCI */
 329
 330
 331 #if defined(CONFIG_TSEC_ENET)
 332
 333 #define CONFIG_MII              1       /* MII PHY management */
 334 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 335 #define CONFIG_TSEC1    1
 336 #define CONFIG_TSEC1_NAME       "eTSEC1"
 337 #define CONFIG_TSEC3    1
 338 #define CONFIG_TSEC3_NAME       "eTSEC3"
 339
 340 #define CONFIG_PIXIS_SGMII_CMD
 341 #define CONFIG_FSL_SGMII_RISER  1
 342 #define SGMII_RISER_PHY_OFFSET  0x1c
 343
 344 #define TSEC1_PHY_ADDR          0
 345 #define TSEC3_PHY_ADDR          1
 346
 347 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 348 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 349
 350 #define TSEC1_PHYIDX            0
 351 #define TSEC3_PHYIDX            0
 352
 353 #define CONFIG_ETHPRIME         "eTSEC1"
 354
 355 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 356 #endif  /* CONFIG_TSEC_ENET */
 357
 358 /*
 359  * Environment
 360  */
 361 #define CONFIG_ENV_IS_IN_FLASH  1
 362 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 363 #define CONFIG_ENV_ADDR         0xfff80000
 364 #else
 365 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x70000)
 366 #endif
 367 #define CONFIG_ENV_SIZE         0x2000
 368 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) */
 369
 370 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 371 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 372
 373 /*
 374  * BOOTP options
 375  */
 376 #define CONFIG_BOOTP_BOOTFILESIZE
 377 #define CONFIG_BOOTP_BOOTPATH
 378 #define CONFIG_BOOTP_GATEWAY
 379 #define CONFIG_BOOTP_HOSTNAME
 380
 381
 382 /*
 383  * Command line configuration.
 384  */
 385 #include <config_cmd_default.h>
 386
 387 #define CONFIG_CMD_PING
 388 #define CONFIG_CMD_I2C
 389 #define CONFIG_CMD_MII
 390 #define CONFIG_CMD_ELF
 391 #define CONFIG_CMD_IRQ
 392 #define CONFIG_CMD_SETEXPR
 393 #define CONFIG_CMD_REGINFO
 394
 395 #if defined(CONFIG_PCI)
 396     #define CONFIG_CMD_PCI
 397     #define CONFIG_CMD_NET
 398     #define CONFIG_CMD_SCSI
 399     #define CONFIG_CMD_EXT2
 400 #endif
 401
 402 /*
 403  * USB
 404  */
 405 #define CONFIG_USB_EHCI
 406
 407 #ifdef CONFIG_USB_EHCI
 408 #define CONFIG_CMD_USB
 409 #define CONFIG_USB_EHCI_PCI
 410 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 411 #define CONFIG_USB_STORAGE
 412 #define CONFIG_PCI_EHCI_DEVICE                  0
 413 #endif
 414
 415 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 416
 417 /*
 418  * Miscellaneous configurable options
 419  */
 420 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 421 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 422 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 423 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 424 #if defined(CONFIG_CMD_KGDB)
 425 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 426 #else
 427 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 428 #endif
 429 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 430 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 431 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 432
 433 /*
 434  * For booting Linux, the board info and command line data
 435  * have to be in the first 64 MB of memory, since this is
 436  * the maximum mapped by the Linux kernel during initialization.
 437  */
 438 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 439 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 440
 441 #if defined(CONFIG_CMD_KGDB)
 442 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 443 #endif
 444
 445 /*
 446  * Environment Configuration
 447  */
 448
 449 /* The mac addresses for all ethernet interface */
 450 #if defined(CONFIG_TSEC_ENET)
 451 #define CONFIG_HAS_ETH0
 452 #define CONFIG_HAS_ETH1
 453 #endif
 454
 455 #define CONFIG_IPADDR   192.168.1.251
 456
 457 #define CONFIG_HOSTNAME 8544ds_unknown
 458 #define CONFIG_ROOTPATH "/nfs/mpc85xx"
 459 #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
 460 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 461
 462 #define CONFIG_SERVERIP 192.168.1.1
 463 #define CONFIG_GATEWAYIP 192.168.1.1
 464 #define CONFIG_NETMASK  255.255.0.0
 465
 466 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 467
 468 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 469 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 470
 471 #define CONFIG_BAUDRATE 115200
 472
 473 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 474 "netdev=eth0\0"                                         \
 475 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 476 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 477         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 478                 " +$filesize; " \
 479         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 480                 " +$filesize; " \
 481         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 482                 " $filesize; "  \
 483         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 484                 " +$filesize; " \
 485         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 486                 " $filesize\0"  \
 487 "consoledev=ttyS0\0"                            \
 488 "ramdiskaddr=2000000\0"                 \
 489 "ramdiskfile=8544ds/ramdisk.uboot\0"            \
 490 "fdtaddr=c00000\0"                              \
 491 "fdtfile=8544ds/mpc8544ds.dtb\0"                \
 492 "bdev=sda3\0"
 493
 494 #define CONFIG_NFSBOOTCOMMAND           \
 495  "setenv bootargs root=/dev/nfs rw "    \
 496  "nfsroot=$serverip:$rootpath "         \
 497  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 498  "console=$consoledev,$baudrate $othbootargs;"  \
 499  "tftp $loadaddr $bootfile;"            \
 500  "tftp $fdtaddr $fdtfile;"              \
 501  "bootm $loadaddr - $fdtaddr"
 502
 503 #define CONFIG_RAMBOOTCOMMAND           \
 504  "setenv bootargs root=/dev/ram rw "    \
 505  "console=$consoledev,$baudrate $othbootargs;"  \
 506  "tftp $ramdiskaddr $ramdiskfile;"      \
 507  "tftp $loadaddr $bootfile;"            \
 508  "tftp $fdtaddr $fdtfile;"              \
 509  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 510
 511 #define CONFIG_BOOTCOMMAND              \
 512  "setenv bootargs root=/dev/$bdev rw "  \
 513  "console=$consoledev,$baudrate $othbootargs;"  \
 514  "tftp $loadaddr $bootfile;"            \
 515  "tftp $fdtaddr $fdtfile;"              \
 516  "bootm $loadaddr - $fdtaddr"
 517
 518 #endif  /* __CONFIG_H */