include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8544ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8544          1
  35 #define CONFIG_MPC8544DS        1
  36
  37 #ifndef CONFIG_SYS_TEXT_BASE
  38 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  39 #endif
  40
  41 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  42 #define CONFIG_PCI1             1       /* PCI controller 1 */
  43 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  44 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  45 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  46 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  47 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  48 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  49 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  50
  51 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  52 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  53
  54 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  55 #define CONFIG_ENV_OVERWRITE
  56 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  57
  58 #ifndef __ASSEMBLY__
  59 extern unsigned long get_board_sys_clk(unsigned long dummy);
  60 #endif
  61 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  67 #define CONFIG_BTB                      /* toggle branch predition */
  68
  69 /*
  70  * Only possible on E500 Version 2 or newer cores.
  71  */
  72 #define CONFIG_ENABLE_36BIT_PHYS        1
  73
  74 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  75 #define CONFIG_SYS_MEMTEST_END          0x00400000
  76 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  77
  78 #define CONFIG_SYS_CCSRBAR              0xe0000000
  79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  80
  81 /* DDR Setup */
  82 #define CONFIG_FSL_DDR2
  83 #undef CONFIG_FSL_DDR_INTERACTIVE
  84 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  85 #define CONFIG_DDR_SPD
  86
  87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  88 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  89
  90 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  92 #define CONFIG_VERY_BIG_RAM
  93
  94 #define CONFIG_NUM_DDR_CONTROLLERS      1
  95 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  96 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  97
  98 /* I2C addresses of SPD EEPROMs */
  99 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 100
 101 /* Make sure required options are set */
 102 #ifndef CONFIG_SPD_EEPROM
 103 #error ("CONFIG_SPD_EEPROM is required")
 104 #endif
 105
 106 #undef CONFIG_CLOCKS_IN_MHZ
 107
 108 /*
 109  * Memory map
 110  *
 111  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 112  *
 113  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 114  *
 115  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 116  *
 117  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
 118  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 119  *
 120  * Localbus cacheable
 121  *
 122  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
 123  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
 124  *
 125  * Localbus non-cacheable
 126  *
 127  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
 128  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
 129  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
 130  *
 131  */
 132
 133 /*
 134  * Local Bus Definitions
 135  */
 136 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* boot TLB */
 137
 138 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of FLASH 8M */
 139
 140 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 141 #define CONFIG_SYS_BR1_PRELIM           0xfe801001
 142
 143 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 144 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 145
 146 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 147
 148 #define CONFIG_SYS_FLASH_QUIET_TEST
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 151 #undef  CONFIG_SYS_FLASH_CHECKSUM
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 154 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 155
 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 157
 158 #define CONFIG_FLASH_CFI_DRIVER
 159 #define CONFIG_SYS_FLASH_CFI
 160 #define CONFIG_SYS_FLASH_EMPTY_INFO
 161
 162 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000
 163
 164 #define CONFIG_SYS_BR2_PRELIM           0xf8201001      /* port size 16bit */
 165 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 166
 167 #define CONFIG_SYS_BR3_PRELIM           0xf8100801      /* port size 8bit */
 168 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 169
 170 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 171 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 172 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 173 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 174 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 175 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 176 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 177                                          * register */
 178 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 179 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 180 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 181 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 182 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 183 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 184 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 185 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 186 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 187 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 188 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 189 #define PIXIS_VSPEED2           0x1d    /* VELA VSpeed 2 */
 190 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 191 #define PIXIS_VSPEED2_TSEC1SER  0x2
 192 #define PIXIS_VSPEED2_TSEC3SER  0x1
 193 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 194 #define PIXIS_VCFGEN1_TSEC3SER  0x40
 195 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
 196 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 197
 198
 199 #define CONFIG_SYS_INIT_RAM_LOCK      1
 200 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 201 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
 202
 203
 204 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 208 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 209
 210 /* Serial Port - controlled on board with jumper J8
 211  * open - index 2
 212  * shorted - index 1
 213  */
 214 #define CONFIG_CONS_INDEX       1
 215 #define CONFIG_SYS_NS16550
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     1
 218 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 219
 220 #define CONFIG_SYS_BAUDRATE_TABLE       \
 221         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 222
 223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 225
 226 /* Use the HUSH parser */
 227 #define CONFIG_SYS_HUSH_PARSER
 228
 229 /* pass open firmware flat tree */
 230 #define CONFIG_OF_LIBFDT                1
 231 #define CONFIG_OF_BOARD_SETUP           1
 232 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 233
 234 /* I2C */
 235 #define CONFIG_SYS_I2C
 236 #define CONFIG_SYS_I2C_FSL
 237 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 238 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 239 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 240 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 242
 243 /*
 244  * General PCI
 245  * Memory space is mapped 1-1, but I/O space must start from 0.
 246  */
 247 #define CONFIG_SYS_PCIE_VIRT            0x80000000      /* 1G PCIE TLB */
 248 #define CONFIG_SYS_PCIE_PHYS            0x80000000      /* 1G PCIE TLB */
 249 #define CONFIG_SYS_PCI_VIRT             0xc0000000      /* 512M PCI TLB */
 250 #define CONFIG_SYS_PCI_PHYS             0xc0000000      /* 512M PCI TLB */
 251
 252 #define CONFIG_SYS_PCI1_MEM_VIRT        0xc0000000
 253 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
 254 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc0000000
 255 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 256 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 257 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 258 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 259 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64k */
 260
 261 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 262 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 263 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x80000000
 264 #define CONFIG_SYS_PCIE2_MEM_BUS        0x80000000
 265 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x80000000
 266 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 267 #define CONFIG_SYS_PCIE2_IO_VIRT        0xe1010000
 268 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 269 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe1010000
 270 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 271
 272 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 273 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 274 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 275 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 276 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 277 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 278 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe1020000
 279 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 280 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe1020000
 281 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 282
 283 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 284 #define CONFIG_SYS_PCIE3_NAME           "ULI"
 285 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 286 #define CONFIG_SYS_PCIE3_MEM_BUS        0xb0000000
 287 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xb0000000
 288 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x00100000      /* 1M */
 289 #define CONFIG_SYS_PCIE3_IO_VIRT        0xb0100000      /* reuse mem LAW */
 290 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 291 #define CONFIG_SYS_PCIE3_IO_PHYS        0xb0100000      /* reuse mem LAW */
 292 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00100000      /* 1M */
 293 #define CONFIG_SYS_PCIE3_MEM_VIRT2      0xb0200000
 294 #define CONFIG_SYS_PCIE3_MEM_BUS2       0xb0200000
 295 #define CONFIG_SYS_PCIE3_MEM_PHYS2      0xb0200000
 296 #define CONFIG_SYS_PCIE3_MEM_SIZE2      0x00200000      /* 1M */
 297
 298 #if defined(CONFIG_PCI)
 299
 300 /*PCIE video card used*/
 301 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 302
 303 /*PCI video card used*/
 304 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 305
 306 /* video */
 307 #define CONFIG_VIDEO
 308
 309 #if defined(CONFIG_VIDEO)
 310 #define CONFIG_BIOSEMU
 311 #define CONFIG_CFB_CONSOLE
 312 #define CONFIG_VIDEO_SW_CURSOR
 313 #define CONFIG_VGA_AS_SINGLE_DEVICE
 314 #define CONFIG_ATI_RADEON_FB
 315 #define CONFIG_VIDEO_LOGO
 316 /*#define CONFIG_CONSOLE_CURSOR*/
 317 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 318 #endif
 319
 320 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 321
 322 #undef CONFIG_EEPRO100
 323 #undef CONFIG_TULIP
 324 #define CONFIG_RTL8139
 325
 326 #ifndef CONFIG_PCI_PNP
 327         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 328         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 329         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 330 #endif
 331
 332 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 333 #define CONFIG_DOS_PARTITION
 334 #define CONFIG_SCSI_AHCI
 335
 336 #ifdef CONFIG_SCSI_AHCI
 337 #define CONFIG_SATA_ULI5288
 338 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 339 #define CONFIG_SYS_SCSI_MAX_LUN 1
 340 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 341 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 342 #endif /* SCSCI */
 343
 344 #endif  /* CONFIG_PCI */
 345
 346
 347 #if defined(CONFIG_TSEC_ENET)
 348
 349 #define CONFIG_MII              1       /* MII PHY management */
 350 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 351 #define CONFIG_TSEC1    1
 352 #define CONFIG_TSEC1_NAME       "eTSEC1"
 353 #define CONFIG_TSEC3    1
 354 #define CONFIG_TSEC3_NAME       "eTSEC3"
 355
 356 #define CONFIG_PIXIS_SGMII_CMD
 357 #define CONFIG_FSL_SGMII_RISER  1
 358 #define SGMII_RISER_PHY_OFFSET  0x1c
 359
 360 #define TSEC1_PHY_ADDR          0
 361 #define TSEC3_PHY_ADDR          1
 362
 363 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 364 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 365
 366 #define TSEC1_PHYIDX            0
 367 #define TSEC3_PHYIDX            0
 368
 369 #define CONFIG_ETHPRIME         "eTSEC1"
 370
 371 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 372 #endif  /* CONFIG_TSEC_ENET */
 373
 374 /*
 375  * Environment
 376  */
 377 #define CONFIG_ENV_IS_IN_FLASH  1
 378 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 379 #define CONFIG_ENV_ADDR         0xfff80000
 380 #else
 381 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x70000)
 382 #endif
 383 #define CONFIG_ENV_SIZE         0x2000
 384 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) */
 385
 386 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 387 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 388
 389 /*
 390  * BOOTP options
 391  */
 392 #define CONFIG_BOOTP_BOOTFILESIZE
 393 #define CONFIG_BOOTP_BOOTPATH
 394 #define CONFIG_BOOTP_GATEWAY
 395 #define CONFIG_BOOTP_HOSTNAME
 396
 397
 398 /*
 399  * Command line configuration.
 400  */
 401 #include <config_cmd_default.h>
 402
 403 #define CONFIG_CMD_PING
 404 #define CONFIG_CMD_I2C
 405 #define CONFIG_CMD_MII
 406 #define CONFIG_CMD_ELF
 407 #define CONFIG_CMD_IRQ
 408 #define CONFIG_CMD_SETEXPR
 409 #define CONFIG_CMD_REGINFO
 410
 411 #if defined(CONFIG_PCI)
 412     #define CONFIG_CMD_PCI
 413     #define CONFIG_CMD_NET
 414     #define CONFIG_CMD_SCSI
 415     #define CONFIG_CMD_EXT2
 416 #endif
 417
 418 /*
 419  * USB
 420  */
 421 #define CONFIG_USB_EHCI
 422
 423 #ifdef CONFIG_USB_EHCI
 424 #define CONFIG_CMD_USB
 425 #define CONFIG_USB_EHCI_PCI
 426 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 427 #define CONFIG_USB_STORAGE
 428 #define CONFIG_PCI_EHCI_DEVICE                  0
 429 #endif
 430
 431 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 432
 433 /*
 434  * Miscellaneous configurable options
 435  */
 436 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 437 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 438 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 439 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 440 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 441 #if defined(CONFIG_CMD_KGDB)
 442 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 443 #else
 444 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 445 #endif
 446 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 447 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 448 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 449 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 450
 451 /*
 452  * For booting Linux, the board info and command line data
 453  * have to be in the first 64 MB of memory, since this is
 454  * the maximum mapped by the Linux kernel during initialization.
 455  */
 456 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 457 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 458
 459 #if defined(CONFIG_CMD_KGDB)
 460 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 461 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 462 #endif
 463
 464 /*
 465  * Environment Configuration
 466  */
 467
 468 /* The mac addresses for all ethernet interface */
 469 #if defined(CONFIG_TSEC_ENET)
 470 #define CONFIG_HAS_ETH0
 471 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 472 #define CONFIG_HAS_ETH1
 473 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 474 #endif
 475
 476 #define CONFIG_IPADDR   192.168.1.251
 477
 478 #define CONFIG_HOSTNAME 8544ds_unknown
 479 #define CONFIG_ROOTPATH "/nfs/mpc85xx"
 480 #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
 481 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 482
 483 #define CONFIG_SERVERIP 192.168.1.1
 484 #define CONFIG_GATEWAYIP 192.168.1.1
 485 #define CONFIG_NETMASK  255.255.0.0
 486
 487 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 488
 489 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 490 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 491
 492 #define CONFIG_BAUDRATE 115200
 493
 494 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 495 "netdev=eth0\0"                                         \
 496 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 497 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 498         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 499                 " +$filesize; " \
 500         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 501                 " +$filesize; " \
 502         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 503                 " $filesize; "  \
 504         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 505                 " +$filesize; " \
 506         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 507                 " $filesize\0"  \
 508 "consoledev=ttyS0\0"                            \
 509 "ramdiskaddr=2000000\0"                 \
 510 "ramdiskfile=8544ds/ramdisk.uboot\0"            \
 511 "fdtaddr=c00000\0"                              \
 512 "fdtfile=8544ds/mpc8544ds.dtb\0"                \
 513 "bdev=sda3\0"
 514
 515 #define CONFIG_NFSBOOTCOMMAND           \
 516  "setenv bootargs root=/dev/nfs rw "    \
 517  "nfsroot=$serverip:$rootpath "         \
 518  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 519  "console=$consoledev,$baudrate $othbootargs;"  \
 520  "tftp $loadaddr $bootfile;"            \
 521  "tftp $fdtaddr $fdtfile;"              \
 522  "bootm $loadaddr - $fdtaddr"
 523
 524 #define CONFIG_RAMBOOTCOMMAND           \
 525  "setenv bootargs root=/dev/ram rw "    \
 526  "console=$consoledev,$baudrate $othbootargs;"  \
 527  "tftp $ramdiskaddr $ramdiskfile;"      \
 528  "tftp $loadaddr $bootfile;"            \
 529  "tftp $fdtaddr $fdtfile;"              \
 530  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 531
 532 #define CONFIG_BOOTCOMMAND              \
 533  "setenv bootargs root=/dev/$bdev rw "  \
 534  "console=$consoledev,$baudrate $othbootargs;"  \
 535  "tftp $loadaddr $bootfile;"            \
 536  "tftp $fdtaddr $fdtfile;"              \
 537  "bootm $loadaddr - $fdtaddr"
 538
 539 #endif  /* __CONFIG_H */