include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8544ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_PCI1             1       /* PCI controller 1 */
  15 #define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
  16 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
  17 #define CONFIG_PCIE3            1       /* PCIE controller 3 (ULI bridge) */
  18 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  19 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  20 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  21 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  22
  23 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  24 #define CONFIG_ENV_OVERWRITE
  25 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  26
  27 #ifndef __ASSEMBLY__
  28 extern unsigned long get_board_sys_clk(unsigned long dummy);
  29 #endif
  30 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  31
  32 /*
  33  * These can be toggled for performance analysis, otherwise use default.
  34  */
  35 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  36 #define CONFIG_BTB                      /* toggle branch predition */
  37
  38 /*
  39  * Only possible on E500 Version 2 or newer cores.
  40  */
  41 #define CONFIG_ENABLE_36BIT_PHYS        1
  42
  43 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  44 #define CONFIG_SYS_MEMTEST_END          0x00400000
  45
  46 #define CONFIG_SYS_CCSRBAR              0xe0000000
  47 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  48
  49 /* DDR Setup */
  50 #undef CONFIG_FSL_DDR_INTERACTIVE
  51 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  52 #define CONFIG_DDR_SPD
  53
  54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  55 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  56
  57 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  58 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  59 #define CONFIG_VERY_BIG_RAM
  60
  61 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  62 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  63
  64 /* I2C addresses of SPD EEPROMs */
  65 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  66
  67 /* Make sure required options are set */
  68 #ifndef CONFIG_SPD_EEPROM
  69 #error ("CONFIG_SPD_EEPROM is required")
  70 #endif
  71
  72 #undef CONFIG_CLOCKS_IN_MHZ
  73
  74 /*
  75  * Memory map
  76  *
  77  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  78  *
  79  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  80  *
  81  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  82  *
  83  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
  84  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  85  *
  86  * Localbus cacheable
  87  *
  88  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
  89  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
  90  *
  91  * Localbus non-cacheable
  92  *
  93  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
  94  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
  95  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
  96  *
  97  */
  98
  99 /*
 100  * Local Bus Definitions
 101  */
 102 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* boot TLB */
 103
 104 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of FLASH 8M */
 105
 106 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 107 #define CONFIG_SYS_BR1_PRELIM           0xfe801001
 108
 109 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 110 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 111
 112 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 113
 114 #define CONFIG_SYS_FLASH_QUIET_TEST
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 117 #undef  CONFIG_SYS_FLASH_CHECKSUM
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 120 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 121
 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 123
 124 #define CONFIG_FLASH_CFI_DRIVER
 125 #define CONFIG_SYS_FLASH_CFI
 126 #define CONFIG_SYS_FLASH_EMPTY_INFO
 127
 128 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000
 129
 130 #define CONFIG_SYS_BR2_PRELIM           0xf8201001      /* port size 16bit */
 131 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 132
 133 #define CONFIG_SYS_BR3_PRELIM           0xf8100801      /* port size 8bit */
 134 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 135
 136 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 137 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 138 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 139 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 140 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 141 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 142 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 143                                          * register */
 144 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 145 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 146 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 147 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 148 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 149 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 150 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 151 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 152 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 153 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 154 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 155 #define PIXIS_VSPEED2           0x1d    /* VELA VSpeed 2 */
 156 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 157 #define PIXIS_VSPEED2_TSEC1SER  0x2
 158 #define PIXIS_VSPEED2_TSEC3SER  0x1
 159 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 160 #define PIXIS_VCFGEN1_TSEC3SER  0x40
 161 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
 162 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 163
 164 #define CONFIG_SYS_INIT_RAM_LOCK      1
 165 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 166 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
 167
 168 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 169 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 170
 171 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 172 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 173
 174 /* Serial Port - controlled on board with jumper J8
 175  * open - index 2
 176  * shorted - index 1
 177  */
 178 #define CONFIG_CONS_INDEX       1
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE     1
 181 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 182
 183 #define CONFIG_SYS_BAUDRATE_TABLE       \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 185
 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 188
 189 /* I2C */
 190 #define CONFIG_SYS_I2C
 191 #define CONFIG_SYS_I2C_FSL
 192 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 193 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 194 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 195 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 197
 198 /*
 199  * General PCI
 200  * Memory space is mapped 1-1, but I/O space must start from 0.
 201  */
 202 #define CONFIG_SYS_PCIE_VIRT            0x80000000      /* 1G PCIE TLB */
 203 #define CONFIG_SYS_PCIE_PHYS            0x80000000      /* 1G PCIE TLB */
 204 #define CONFIG_SYS_PCI_VIRT             0xc0000000      /* 512M PCI TLB */
 205 #define CONFIG_SYS_PCI_PHYS             0xc0000000      /* 512M PCI TLB */
 206
 207 #define CONFIG_SYS_PCI1_MEM_VIRT        0xc0000000
 208 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
 209 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc0000000
 210 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 211 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 212 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 213 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 214 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64k */
 215
 216 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 217 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 218 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x80000000
 219 #define CONFIG_SYS_PCIE2_MEM_BUS        0x80000000
 220 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x80000000
 221 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 222 #define CONFIG_SYS_PCIE2_IO_VIRT        0xe1010000
 223 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 224 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe1010000
 225 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 226
 227 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 228 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 229 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 230 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 231 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 232 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 233 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe1020000
 234 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 235 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe1020000
 236 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 237
 238 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 239 #define CONFIG_SYS_PCIE3_NAME           "ULI"
 240 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 241 #define CONFIG_SYS_PCIE3_MEM_BUS        0xb0000000
 242 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xb0000000
 243 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x00100000      /* 1M */
 244 #define CONFIG_SYS_PCIE3_IO_VIRT        0xb0100000      /* reuse mem LAW */
 245 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 246 #define CONFIG_SYS_PCIE3_IO_PHYS        0xb0100000      /* reuse mem LAW */
 247 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00100000      /* 1M */
 248 #define CONFIG_SYS_PCIE3_MEM_VIRT2      0xb0200000
 249 #define CONFIG_SYS_PCIE3_MEM_BUS2       0xb0200000
 250 #define CONFIG_SYS_PCIE3_MEM_PHYS2      0xb0200000
 251 #define CONFIG_SYS_PCIE3_MEM_SIZE2      0x00200000      /* 1M */
 252
 253 #if defined(CONFIG_PCI)
 254
 255 /*PCIE video card used*/
 256 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 257
 258 /*PCI video card used*/
 259 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 260
 261 /* video */
 262
 263 #if defined(CONFIG_VIDEO)
 264 #define CONFIG_BIOSEMU
 265 #define CONFIG_ATI_RADEON_FB
 266 #define CONFIG_VIDEO_LOGO
 267 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 268 #endif
 269
 270 #undef CONFIG_EEPRO100
 271 #undef CONFIG_TULIP
 272
 273 #ifndef CONFIG_PCI_PNP
 274         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 275         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 276         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 277 #endif
 278
 279 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 280
 281 #ifdef CONFIG_SCSI_AHCI
 282 #define CONFIG_SATA_ULI5288
 283 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 284 #define CONFIG_SYS_SCSI_MAX_LUN 1
 285 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 286 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 287 #endif /* SCSCI */
 288
 289 #endif  /* CONFIG_PCI */
 290
 291 #if defined(CONFIG_TSEC_ENET)
 292
 293 #define CONFIG_MII              1       /* MII PHY management */
 294 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 295 #define CONFIG_TSEC1    1
 296 #define CONFIG_TSEC1_NAME       "eTSEC1"
 297 #define CONFIG_TSEC3    1
 298 #define CONFIG_TSEC3_NAME       "eTSEC3"
 299
 300 #define CONFIG_PIXIS_SGMII_CMD
 301 #define CONFIG_FSL_SGMII_RISER  1
 302 #define SGMII_RISER_PHY_OFFSET  0x1c
 303
 304 #define TSEC1_PHY_ADDR          0
 305 #define TSEC3_PHY_ADDR          1
 306
 307 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 308 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 309
 310 #define TSEC1_PHYIDX            0
 311 #define TSEC3_PHYIDX            0
 312
 313 #define CONFIG_ETHPRIME         "eTSEC1"
 314 #endif  /* CONFIG_TSEC_ENET */
 315
 316 /*
 317  * Environment
 318  */
 319 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) */
 320 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 321 #define CONFIG_ENV_ADDR         0xfff80000
 322 #else
 323 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 324 #endif
 325 #define CONFIG_ENV_SIZE         0x2000
 326
 327 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 328 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 329
 330 /*
 331  * BOOTP options
 332  */
 333 #define CONFIG_BOOTP_BOOTFILESIZE
 334
 335 /*
 336  * USB
 337  */
 338
 339 #ifdef CONFIG_USB_EHCI_HCD
 340 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 341 #define CONFIG_PCI_EHCI_DEVICE                  0
 342 #endif
 343
 344 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 345
 346 /*
 347  * Miscellaneous configurable options
 348  */
 349 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 350
 351 /*
 352  * For booting Linux, the board info and command line data
 353  * have to be in the first 64 MB of memory, since this is
 354  * the maximum mapped by the Linux kernel during initialization.
 355  */
 356 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 357 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 358
 359 #if defined(CONFIG_CMD_KGDB)
 360 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 361 #endif
 362
 363 /*
 364  * Environment Configuration
 365  */
 366
 367 /* The mac addresses for all ethernet interface */
 368 #if defined(CONFIG_TSEC_ENET)
 369 #define CONFIG_HAS_ETH0
 370 #define CONFIG_HAS_ETH1
 371 #endif
 372
 373 #define CONFIG_IPADDR   192.168.1.251
 374
 375 #define CONFIG_HOSTNAME 8544ds_unknown
 376 #define CONFIG_ROOTPATH "/nfs/mpc85xx"
 377 #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
 378 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 379
 380 #define CONFIG_SERVERIP 192.168.1.1
 381 #define CONFIG_GATEWAYIP 192.168.1.1
 382 #define CONFIG_NETMASK  255.255.0.0
 383
 384 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 385
 386 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 387 "netdev=eth0\0"                                         \
 388 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 389 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 390         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 391                 " +$filesize; " \
 392         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 393                 " +$filesize; " \
 394         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 395                 " $filesize; "  \
 396         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 397                 " +$filesize; " \
 398         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 399                 " $filesize\0"  \
 400 "consoledev=ttyS0\0"                            \
 401 "ramdiskaddr=2000000\0"                 \
 402 "ramdiskfile=8544ds/ramdisk.uboot\0"            \
 403 "fdtaddr=1e00000\0"                             \
 404 "fdtfile=8544ds/mpc8544ds.dtb\0"                \
 405 "bdev=sda3\0"
 406
 407 #define CONFIG_NFSBOOTCOMMAND           \
 408  "setenv bootargs root=/dev/nfs rw "    \
 409  "nfsroot=$serverip:$rootpath "         \
 410  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 411  "console=$consoledev,$baudrate $othbootargs;"  \
 412  "tftp $loadaddr $bootfile;"            \
 413  "tftp $fdtaddr $fdtfile;"              \
 414  "bootm $loadaddr - $fdtaddr"
 415
 416 #define CONFIG_RAMBOOTCOMMAND           \
 417  "setenv bootargs root=/dev/ram rw "    \
 418  "console=$consoledev,$baudrate $othbootargs;"  \
 419  "tftp $ramdiskaddr $ramdiskfile;"      \
 420  "tftp $loadaddr $bootfile;"            \
 421  "tftp $fdtaddr $fdtfile;"              \
 422  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 423
 424 #define CONFIG_BOOTCOMMAND              \
 425  "setenv bootargs root=/dev/$bdev rw "  \
 426  "console=$consoledev,$baudrate $othbootargs;"  \
 427  "tftp $loadaddr $bootfile;"            \
 428  "tftp $fdtaddr $fdtfile;"              \
 429  "bootm $loadaddr - $fdtaddr"
 430
 431 #endif  /* __CONFIG_H */