include/configs/MPC8548CDS.h

   1 /*
   2  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8548cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_BOOKE            1       /* BOOKE */
  18 #define CONFIG_E500             1       /* BOOKE e500 family */
  19 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  20 #define CONFIG_MPC8548CDS       1       /* MPC8548CDS board specific */
  21
  22 #ifndef CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  24 #endif
  25
  26 #define CONFIG_SYS_SRIO
  27 #define CONFIG_SRIO1                    /* SRIO port 1 */
  28
  29 #define CONFIG_PCI1             /* PCI controller 1 */
  30 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  31 #undef CONFIG_PCI2
  32 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  33 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  34 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  35 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  36
  37 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  38 #define CONFIG_ENV_OVERWRITE
  39 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  40 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  41
  42 #define CONFIG_FSL_VIA
  43
  44 #ifndef __ASSEMBLY__
  45 extern unsigned long get_clock_freq(void);
  46 #endif
  47 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  48
  49 /*
  50  * These can be toggled for performance analysis, otherwise use default.
  51  */
  52 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  53 #define CONFIG_BTB                      /* toggle branch predition */
  54
  55 /*
  56  * Only possible on E500 Version 2 or newer cores.
  57  */
  58 #define CONFIG_ENABLE_36BIT_PHYS        1
  59
  60 #ifdef CONFIG_PHYS_64BIT
  61 #define CONFIG_ADDR_MAP
  62 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  63 #endif
  64
  65 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  66 #define CONFIG_SYS_MEMTEST_END          0x00400000
  67
  68 #define CONFIG_SYS_CCSRBAR              0xe0000000
  69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  70
  71 /* DDR Setup */
  72 #define CONFIG_SYS_FSL_DDR2
  73 #undef CONFIG_FSL_DDR_INTERACTIVE
  74 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  75 #define CONFIG_DDR_SPD
  76
  77 #define CONFIG_DDR_ECC
  78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  79 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  80
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  83
  84 #define CONFIG_NUM_DDR_CONTROLLERS      1
  85 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  86 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  87
  88 /* I2C addresses of SPD EEPROMs */
  89 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  90
  91 /* Make sure required options are set */
  92 #ifndef CONFIG_SPD_EEPROM
  93 #error ("CONFIG_SPD_EEPROM is required")
  94 #endif
  95
  96 #undef CONFIG_CLOCKS_IN_MHZ
  97 /*
  98  * Physical Address Map
  99  *
 100  * 32bit:
 101  * 0x0000_0000  0x7fff_ffff     DDR                     2G      cacheable
 102  * 0x8000_0000  0x9fff_ffff     PCI1 MEM                512M    cacheable
 103  * 0xa000_0000  0xbfff_ffff     PCIe MEM                512M    cacheable
 104  * 0xc000_0000  0xdfff_ffff     RapidIO                 512M    cacheable
 105  * 0xe000_0000  0xe00f_ffff     CCSR                    1M      non-cacheable
 106  * 0xe200_0000  0xe20f_ffff     PCI1 IO                 1M      non-cacheable
 107  * 0xe300_0000  0xe30f_ffff     PCIe IO                 1M      non-cacheable
 108  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M     cacheable
 109  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS            1M      non-cacheable
 110  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M      non-cacheable
 111  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M      non-cacheable
 112  *
 113  * 36bit:
 114  * 0x00000_0000 0x07fff_ffff    DDR                     2G      cacheable
 115  * 0xc0000_0000 0xc1fff_ffff    PCI1 MEM                512M    cacheable
 116  * 0xc2000_0000 0xc3fff_ffff    PCIe MEM                512M    cacheable
 117  * 0xc4000_0000 0xc5fff_ffff    RapidIO                 512M    cacheable
 118  * 0xfe000_0000 0xfe00f_ffff    CCSR                    1M      non-cacheable
 119  * 0xfe200_0000 0xfe20f_ffff    PCI1 IO                 1M      non-cacheable
 120  * 0xfe300_0000 0xfe30f_ffff    PCIe IO                 1M      non-cacheable
 121  * 0xff000_0000 0xff3ff_ffff    SDRAM                   64M     cacheable
 122  * 0xff800_0000 0xff80f_ffff    NVRAM/CADMUS            1M      non-cacheable
 123  * 0xfff00_0000 0xfff7f_ffff    FLASH (2nd bank)        8M      non-cacheable
 124  * 0xfff80_0000 0xfffff_ffff    FLASH (boot bank)       8M      non-cacheable
 125  *
 126  */
 127
 128 /*
 129  * Local Bus Definitions
 130  */
 131
 132 /*
 133  * FLASH on the Local Bus
 134  * Two banks, 8M each, using the CFI driver.
 135  * Boot from BR0/OR0 bank at 0xff00_0000
 136  * Alternate BR1/OR1 bank at 0xff80_0000
 137  *
 138  * BR0, BR1:
 139  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 140  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 141  *    Port Size = 16 bits = BRx[19:20] = 10
 142  *    Use GPCM = BRx[24:26] = 000
 143  *    Valid = BRx[31] = 1
 144  *
 145  * 0    4    8    12   16   20   24   28
 146  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 147  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 148  *
 149  * OR0, OR1:
 150  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 151  *    Reserved ORx[17:18] = 11, confusion here?
 152  *    CSNT = ORx[20] = 1
 153  *    ACS = half cycle delay = ORx[21:22] = 11
 154  *    SCY = 6 = ORx[24:27] = 0110
 155  *    TRLX = use relaxed timing = ORx[29] = 1
 156  *    EAD = use external address latch delay = OR[31] = 1
 157  *
 158  * 0    4    8    12   16   20   24   28
 159  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 160  */
 161
 162 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 163 #ifdef CONFIG_PHYS_64BIT
 164 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfff000000ull
 165 #else
 166 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 167 #endif
 168
 169 #define CONFIG_SYS_BR0_PRELIM \
 170         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
 171 #define CONFIG_SYS_BR1_PRELIM \
 172         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 173
 174 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 175 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 176
 177 #define CONFIG_SYS_FLASH_BANKS_LIST \
 178         {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 181 #undef  CONFIG_SYS_FLASH_CHECKSUM
 182 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 183 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 184
 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 186
 187 #define CONFIG_FLASH_CFI_DRIVER
 188 #define CONFIG_SYS_FLASH_CFI
 189 #define CONFIG_SYS_FLASH_EMPTY_INFO
 190
 191 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 192
 193 /*
 194  * SDRAM on the Local Bus
 195  */
 196 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 197 #ifdef CONFIG_PHYS_64BIT
 198 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  0xff0000000ull
 199 #else
 200 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  CONFIG_SYS_LBC_SDRAM_BASE
 201 #endif
 202 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 203
 204 /*
 205  * Base Register 2 and Option Register 2 configure SDRAM.
 206  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 207  *
 208  * For BR2, need:
 209  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 210  *    port-size = 32-bits = BR2[19:20] = 11
 211  *    no parity checking = BR2[21:22] = 00
 212  *    SDRAM for MSEL = BR2[24:26] = 011
 213  *    Valid = BR[31] = 1
 214  *
 215  * 0    4    8    12   16   20   24   28
 216  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 217  *
 218  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 219  * FIXME: the top 17 bits of BR2.
 220  */
 221
 222 #define CONFIG_SYS_BR2_PRELIM \
 223         (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
 224         | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
 225
 226 /*
 227  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 228  *
 229  * For OR2, need:
 230  *    64MB mask for AM, OR2[0:7] = 1111 1100
 231  *                 XAM, OR2[17:18] = 11
 232  *    9 columns OR2[19-21] = 010
 233  *    13 rows   OR2[23-25] = 100
 234  *    EAD set for extra time OR[31] = 1
 235  *
 236  * 0    4    8    12   16   20   24   28
 237  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 238  */
 239
 240 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 241
 242 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 243 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 244 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 245 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 246
 247 /*
 248  * Common settings for all Local Bus SDRAM commands.
 249  * At run time, either BSMA1516 (for CPU 1.1)
 250  *                  or BSMA1617 (for CPU 1.0) (old)
 251  * is OR'ed in too.
 252  */
 253 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 254                                 | LSDMR_PRETOACT7       \
 255                                 | LSDMR_ACTTORW7        \
 256                                 | LSDMR_BL8             \
 257                                 | LSDMR_WRC4            \
 258                                 | LSDMR_CL3             \
 259                                 | LSDMR_RFEN            \
 260                                 )
 261
 262 /*
 263  * The CADMUS registers are connected to CS3 on CDS.
 264  * The new memory map places CADMUS at 0xf8000000.
 265  *
 266  * For BR3, need:
 267  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 268  *    port-size = 8-bits  = BR[19:20] = 01
 269  *    no parity checking  = BR[21:22] = 00
 270  *    GPMC for MSEL       = BR[24:26] = 000
 271  *    Valid               = BR[31]    = 1
 272  *
 273  * 0    4    8    12   16   20   24   28
 274  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 275  *
 276  * For OR3, need:
 277  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 278  *    disable buffer ctrl OR[19]    = 0
 279  *    CSNT                OR[20]    = 1
 280  *    ACS                 OR[21:22] = 11
 281  *    XACS                OR[23]    = 1
 282  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 283  *    SETA                OR[28]    = 0
 284  *    TRLX                OR[29]    = 1
 285  *    EHTR                OR[30]    = 1
 286  *    EAD extra time      OR[31]    = 1
 287  *
 288  * 0    4    8    12   16   20   24   28
 289  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 290  */
 291
 292 #define CONFIG_FSL_CADMUS
 293
 294 #define CADMUS_BASE_ADDR 0xf8000000
 295 #ifdef CONFIG_PHYS_64BIT
 296 #define CADMUS_BASE_ADDR_PHYS   0xff8000000ull
 297 #else
 298 #define CADMUS_BASE_ADDR_PHYS   CADMUS_BASE_ADDR
 299 #endif
 300 #define CONFIG_SYS_BR3_PRELIM \
 301         (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
 302 #define CONFIG_SYS_OR3_PRELIM    0xfff00ff7
 303
 304 #define CONFIG_SYS_INIT_RAM_LOCK        1
 305 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 306 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 307
 308 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 309 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 310
 311 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 312 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 313
 314 /* Serial Port */
 315 #define CONFIG_CONS_INDEX       2
 316 #define CONFIG_SYS_NS16550_SERIAL
 317 #define CONFIG_SYS_NS16550_REG_SIZE     1
 318 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 319
 320 #define CONFIG_SYS_BAUDRATE_TABLE \
 321         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 322
 323 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 324 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 325
 326 /*
 327  * I2C
 328  */
 329 #define CONFIG_SYS_I2C
 330 #define CONFIG_SYS_I2C_FSL
 331 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 332 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 333 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 334 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 335
 336 /* EEPROM */
 337 #define CONFIG_ID_EEPROM
 338 #define CONFIG_SYS_I2C_EEPROM_CCID
 339 #define CONFIG_SYS_ID_EEPROM
 340 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 341 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 342
 343 /*
 344  * General PCI
 345  * Memory space is mapped 1-1, but I/O space must start from 0.
 346  */
 347 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 348 #ifdef CONFIG_PHYS_64BIT
 349 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 350 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 351 #else
 352 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 353 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 354 #endif
 355 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 356 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 357 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 358 #ifdef CONFIG_PHYS_64BIT
 359 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 360 #else
 361 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 362 #endif
 363 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 364
 365 #ifdef CONFIG_PCIE1
 366 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 367 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 368 #ifdef CONFIG_PHYS_64BIT
 369 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 370 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc20000000ull
 371 #else
 372 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 373 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 374 #endif
 375 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 376 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe3000000
 377 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 378 #ifdef CONFIG_PHYS_64BIT
 379 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 380 #else
 381 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 382 #endif
 383 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 384 #endif
 385
 386 /*
 387  * RapidIO MMU
 388  */
 389 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xc0000000
 390 #ifdef CONFIG_PHYS_64BIT
 391 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc40000000ull
 392 #else
 393 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc0000000
 394 #endif
 395 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 396
 397 #ifdef CONFIG_LEGACY
 398 #define BRIDGE_ID 17
 399 #define VIA_ID 2
 400 #else
 401 #define BRIDGE_ID 28
 402 #define VIA_ID 4
 403 #endif
 404
 405 #if defined(CONFIG_PCI)
 406 #undef CONFIG_EEPRO100
 407 #undef CONFIG_TULIP
 408
 409 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 410
 411 #endif  /* CONFIG_PCI */
 412
 413 #if defined(CONFIG_TSEC_ENET)
 414
 415 #define CONFIG_MII              1       /* MII PHY management */
 416 #define CONFIG_TSEC1    1
 417 #define CONFIG_TSEC1_NAME       "eTSEC0"
 418 #define CONFIG_TSEC2    1
 419 #define CONFIG_TSEC2_NAME       "eTSEC1"
 420 #define CONFIG_TSEC3    1
 421 #define CONFIG_TSEC3_NAME       "eTSEC2"
 422 #define CONFIG_TSEC4
 423 #define CONFIG_TSEC4_NAME       "eTSEC3"
 424 #undef CONFIG_MPC85XX_FEC
 425
 426 #define CONFIG_PHY_MARVELL
 427
 428 #define TSEC1_PHY_ADDR          0
 429 #define TSEC2_PHY_ADDR          1
 430 #define TSEC3_PHY_ADDR          2
 431 #define TSEC4_PHY_ADDR          3
 432
 433 #define TSEC1_PHYIDX            0
 434 #define TSEC2_PHYIDX            0
 435 #define TSEC3_PHYIDX            0
 436 #define TSEC4_PHYIDX            0
 437 #define TSEC1_FLAGS             TSEC_GIGABIT
 438 #define TSEC2_FLAGS             TSEC_GIGABIT
 439 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 440 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 441
 442 /* Options are: eTSEC[0-3] */
 443 #define CONFIG_ETHPRIME         "eTSEC0"
 444 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 445 #endif  /* CONFIG_TSEC_ENET */
 446
 447 /*
 448  * Environment
 449  */
 450 #define CONFIG_ENV_IS_IN_FLASH  1
 451 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 452 #define CONFIG_ENV_ADDR 0xfff80000
 453 #else
 454 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 455 #endif
 456 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K for env */
 457 #define CONFIG_ENV_SIZE         0x2000
 458
 459 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 460 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 461
 462 /*
 463  * BOOTP options
 464  */
 465 #define CONFIG_BOOTP_BOOTFILESIZE
 466 #define CONFIG_BOOTP_BOOTPATH
 467 #define CONFIG_BOOTP_GATEWAY
 468 #define CONFIG_BOOTP_HOSTNAME
 469
 470 /*
 471  * Command line configuration.
 472  */
 473 #define CONFIG_CMD_IRQ
 474 #define CONFIG_CMD_REGINFO
 475
 476 #if defined(CONFIG_PCI)
 477     #define CONFIG_CMD_PCI
 478 #endif
 479
 480 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 481
 482 /*
 483  * Miscellaneous configurable options
 484  */
 485 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 486 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 487 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 488 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 489 #if defined(CONFIG_CMD_KGDB)
 490 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 491 #else
 492 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 493 #endif
 494 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 495 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 496 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 497
 498 /*
 499  * For booting Linux, the board info and command line data
 500  * have to be in the first 64 MB of memory, since this is
 501  * the maximum mapped by the Linux kernel during initialization.
 502  */
 503 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 504 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 505
 506 #if defined(CONFIG_CMD_KGDB)
 507 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 508 #endif
 509
 510 /*
 511  * Environment Configuration
 512  */
 513 #if defined(CONFIG_TSEC_ENET)
 514 #define CONFIG_HAS_ETH0
 515 #define CONFIG_HAS_ETH1
 516 #define CONFIG_HAS_ETH2
 517 #define CONFIG_HAS_ETH3
 518 #endif
 519
 520 #define CONFIG_IPADDR    192.168.1.253
 521
 522 #define CONFIG_HOSTNAME  unknown
 523 #define CONFIG_ROOTPATH  "/nfsroot"
 524 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
 525 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 526
 527 #define CONFIG_SERVERIP  192.168.1.1
 528 #define CONFIG_GATEWAYIP 192.168.1.1
 529 #define CONFIG_NETMASK   255.255.255.0
 530
 531 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 532
 533 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 534
 535 #define CONFIG_BAUDRATE 115200
 536
 537 #define CONFIG_EXTRA_ENV_SETTINGS               \
 538         "hwconfig=fsl_ddr:ecc=off\0"            \
 539         "netdev=eth0\0"                         \
 540         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 541         "tftpflash=tftpboot $loadaddr $uboot; " \
 542                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 543                         " +$filesize; " \
 544                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 545                         " +$filesize; " \
 546                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 547                         " $filesize; "  \
 548                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 549                         " +$filesize; " \
 550                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 551                         " $filesize\0"  \
 552         "consoledev=ttyS1\0"                    \
 553         "ramdiskaddr=2000000\0"                 \
 554         "ramdiskfile=ramdisk.uboot\0"           \
 555         "fdtaddr=1e00000\0"                     \
 556         "fdtfile=mpc8548cds.dtb\0"
 557
 558 #define CONFIG_NFSBOOTCOMMAND                                           \
 559    "setenv bootargs root=/dev/nfs rw "                                  \
 560       "nfsroot=$serverip:$rootpath "                                    \
 561       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 562       "console=$consoledev,$baudrate $othbootargs;"                     \
 563    "tftp $loadaddr $bootfile;"                                          \
 564    "tftp $fdtaddr $fdtfile;"                                            \
 565    "bootm $loadaddr - $fdtaddr"
 566
 567 #define CONFIG_RAMBOOTCOMMAND \
 568    "setenv bootargs root=/dev/ram rw "                                  \
 569       "console=$consoledev,$baudrate $othbootargs;"                     \
 570    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 571    "tftp $loadaddr $bootfile;"                                          \
 572    "tftp $fdtaddr $fdtfile;"                                            \
 573    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 574
 575 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 576
 577 #endif  /* __CONFIG_H */