include/configs/MPC8548CDS.h

   1 /*
   2  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8548cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_SYS_GENERIC_BOARD
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #ifdef CONFIG_36BIT
  20 #define CONFIG_PHYS_64BIT
  21 #endif
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_BOOKE            1       /* BOOKE */
  25 #define CONFIG_E500             1       /* BOOKE e500 family */
  26 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  27 #define CONFIG_MPC8548CDS       1       /* MPC8548CDS board specific */
  28
  29 #ifndef CONFIG_SYS_TEXT_BASE
  30 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  31 #endif
  32
  33 #define CONFIG_SYS_SRIO
  34 #define CONFIG_SRIO1                    /* SRIO port 1 */
  35
  36 #define CONFIG_PCI              /* enable any pci type devices */
  37 #define CONFIG_PCI1             /* PCI controller 1 */
  38 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  39 #undef CONFIG_PCI2
  40 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  41 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  42 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  43 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  44
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  46 #define CONFIG_ENV_OVERWRITE
  47 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  48 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  49
  50 #define CONFIG_FSL_VIA
  51
  52 #ifndef __ASSEMBLY__
  53 extern unsigned long get_clock_freq(void);
  54 #endif
  55 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  61 #define CONFIG_BTB                      /* toggle branch predition */
  62
  63 /*
  64  * Only possible on E500 Version 2 or newer cores.
  65  */
  66 #define CONFIG_ENABLE_36BIT_PHYS        1
  67
  68 #ifdef CONFIG_PHYS_64BIT
  69 #define CONFIG_ADDR_MAP
  70 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  71 #endif
  72
  73 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  74 #define CONFIG_SYS_MEMTEST_END          0x00400000
  75
  76 #define CONFIG_SYS_CCSRBAR              0xe0000000
  77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  78
  79 /* DDR Setup */
  80 #define CONFIG_SYS_FSL_DDR2
  81 #undef CONFIG_FSL_DDR_INTERACTIVE
  82 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  83 #define CONFIG_DDR_SPD
  84
  85 #define CONFIG_DDR_ECC
  86 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  87 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  88
  89 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  90 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  91
  92 #define CONFIG_NUM_DDR_CONTROLLERS      1
  93 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  94 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  95
  96 /* I2C addresses of SPD EEPROMs */
  97 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  98
  99 /* Make sure required options are set */
 100 #ifndef CONFIG_SPD_EEPROM
 101 #error ("CONFIG_SPD_EEPROM is required")
 102 #endif
 103
 104 #undef CONFIG_CLOCKS_IN_MHZ
 105 /*
 106  * Physical Address Map
 107  *
 108  * 32bit:
 109  * 0x0000_0000  0x7fff_ffff     DDR                     2G      cacheable
 110  * 0x8000_0000  0x9fff_ffff     PCI1 MEM                512M    cacheable
 111  * 0xa000_0000  0xbfff_ffff     PCIe MEM                512M    cacheable
 112  * 0xc000_0000  0xdfff_ffff     RapidIO                 512M    cacheable
 113  * 0xe000_0000  0xe00f_ffff     CCSR                    1M      non-cacheable
 114  * 0xe200_0000  0xe20f_ffff     PCI1 IO                 1M      non-cacheable
 115  * 0xe300_0000  0xe30f_ffff     PCIe IO                 1M      non-cacheable
 116  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M     cacheable
 117  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS            1M      non-cacheable
 118  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M      non-cacheable
 119  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M      non-cacheable
 120  *
 121  * 36bit:
 122  * 0x00000_0000 0x07fff_ffff    DDR                     2G      cacheable
 123  * 0xc0000_0000 0xc1fff_ffff    PCI1 MEM                512M    cacheable
 124  * 0xc2000_0000 0xc3fff_ffff    PCIe MEM                512M    cacheable
 125  * 0xc4000_0000 0xc5fff_ffff    RapidIO                 512M    cacheable
 126  * 0xfe000_0000 0xfe00f_ffff    CCSR                    1M      non-cacheable
 127  * 0xfe200_0000 0xfe20f_ffff    PCI1 IO                 1M      non-cacheable
 128  * 0xfe300_0000 0xfe30f_ffff    PCIe IO                 1M      non-cacheable
 129  * 0xff000_0000 0xff3ff_ffff    SDRAM                   64M     cacheable
 130  * 0xff800_0000 0xff80f_ffff    NVRAM/CADMUS            1M      non-cacheable
 131  * 0xfff00_0000 0xfff7f_ffff    FLASH (2nd bank)        8M      non-cacheable
 132  * 0xfff80_0000 0xfffff_ffff    FLASH (boot bank)       8M      non-cacheable
 133  *
 134  */
 135
 136
 137 /*
 138  * Local Bus Definitions
 139  */
 140
 141 /*
 142  * FLASH on the Local Bus
 143  * Two banks, 8M each, using the CFI driver.
 144  * Boot from BR0/OR0 bank at 0xff00_0000
 145  * Alternate BR1/OR1 bank at 0xff80_0000
 146  *
 147  * BR0, BR1:
 148  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 149  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 150  *    Port Size = 16 bits = BRx[19:20] = 10
 151  *    Use GPCM = BRx[24:26] = 000
 152  *    Valid = BRx[31] = 1
 153  *
 154  * 0    4    8    12   16   20   24   28
 155  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 156  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 157  *
 158  * OR0, OR1:
 159  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 160  *    Reserved ORx[17:18] = 11, confusion here?
 161  *    CSNT = ORx[20] = 1
 162  *    ACS = half cycle delay = ORx[21:22] = 11
 163  *    SCY = 6 = ORx[24:27] = 0110
 164  *    TRLX = use relaxed timing = ORx[29] = 1
 165  *    EAD = use external address latch delay = OR[31] = 1
 166  *
 167  * 0    4    8    12   16   20   24   28
 168  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 169  */
 170
 171 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 172 #ifdef CONFIG_PHYS_64BIT
 173 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfff000000ull
 174 #else
 175 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 176 #endif
 177
 178 #define CONFIG_SYS_BR0_PRELIM \
 179         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
 180 #define CONFIG_SYS_BR1_PRELIM \
 181         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 182
 183 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 184 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 185
 186 #define CONFIG_SYS_FLASH_BANKS_LIST \
 187         {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
 188 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 189 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 190 #undef  CONFIG_SYS_FLASH_CHECKSUM
 191 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 192 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 193
 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 195
 196 #define CONFIG_FLASH_CFI_DRIVER
 197 #define CONFIG_SYS_FLASH_CFI
 198 #define CONFIG_SYS_FLASH_EMPTY_INFO
 199
 200 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 201
 202 /*
 203  * SDRAM on the Local Bus
 204  */
 205 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 206 #ifdef CONFIG_PHYS_64BIT
 207 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  0xff0000000ull
 208 #else
 209 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  CONFIG_SYS_LBC_SDRAM_BASE
 210 #endif
 211 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 212
 213 /*
 214  * Base Register 2 and Option Register 2 configure SDRAM.
 215  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 216  *
 217  * For BR2, need:
 218  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 219  *    port-size = 32-bits = BR2[19:20] = 11
 220  *    no parity checking = BR2[21:22] = 00
 221  *    SDRAM for MSEL = BR2[24:26] = 011
 222  *    Valid = BR[31] = 1
 223  *
 224  * 0    4    8    12   16   20   24   28
 225  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 226  *
 227  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 228  * FIXME: the top 17 bits of BR2.
 229  */
 230
 231 #define CONFIG_SYS_BR2_PRELIM \
 232         (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
 233         | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
 234
 235 /*
 236  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 237  *
 238  * For OR2, need:
 239  *    64MB mask for AM, OR2[0:7] = 1111 1100
 240  *                 XAM, OR2[17:18] = 11
 241  *    9 columns OR2[19-21] = 010
 242  *    13 rows   OR2[23-25] = 100
 243  *    EAD set for extra time OR[31] = 1
 244  *
 245  * 0    4    8    12   16   20   24   28
 246  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 247  */
 248
 249 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 250
 251 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 252 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 253 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 254 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 255
 256 /*
 257  * Common settings for all Local Bus SDRAM commands.
 258  * At run time, either BSMA1516 (for CPU 1.1)
 259  *                  or BSMA1617 (for CPU 1.0) (old)
 260  * is OR'ed in too.
 261  */
 262 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 263                                 | LSDMR_PRETOACT7       \
 264                                 | LSDMR_ACTTORW7        \
 265                                 | LSDMR_BL8             \
 266                                 | LSDMR_WRC4            \
 267                                 | LSDMR_CL3             \
 268                                 | LSDMR_RFEN            \
 269                                 )
 270
 271 /*
 272  * The CADMUS registers are connected to CS3 on CDS.
 273  * The new memory map places CADMUS at 0xf8000000.
 274  *
 275  * For BR3, need:
 276  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 277  *    port-size = 8-bits  = BR[19:20] = 01
 278  *    no parity checking  = BR[21:22] = 00
 279  *    GPMC for MSEL       = BR[24:26] = 000
 280  *    Valid               = BR[31]    = 1
 281  *
 282  * 0    4    8    12   16   20   24   28
 283  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 284  *
 285  * For OR3, need:
 286  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 287  *    disable buffer ctrl OR[19]    = 0
 288  *    CSNT                OR[20]    = 1
 289  *    ACS                 OR[21:22] = 11
 290  *    XACS                OR[23]    = 1
 291  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 292  *    SETA                OR[28]    = 0
 293  *    TRLX                OR[29]    = 1
 294  *    EHTR                OR[30]    = 1
 295  *    EAD extra time      OR[31]    = 1
 296  *
 297  * 0    4    8    12   16   20   24   28
 298  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 299  */
 300
 301 #define CONFIG_FSL_CADMUS
 302
 303 #define CADMUS_BASE_ADDR 0xf8000000
 304 #ifdef CONFIG_PHYS_64BIT
 305 #define CADMUS_BASE_ADDR_PHYS   0xff8000000ull
 306 #else
 307 #define CADMUS_BASE_ADDR_PHYS   CADMUS_BASE_ADDR
 308 #endif
 309 #define CONFIG_SYS_BR3_PRELIM \
 310         (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
 311 #define CONFIG_SYS_OR3_PRELIM    0xfff00ff7
 312
 313 #define CONFIG_SYS_INIT_RAM_LOCK        1
 314 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 315 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 316
 317 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 318 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 319
 320 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 321 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 322
 323 /* Serial Port */
 324 #define CONFIG_CONS_INDEX       2
 325 #define CONFIG_SYS_NS16550
 326 #define CONFIG_SYS_NS16550_SERIAL
 327 #define CONFIG_SYS_NS16550_REG_SIZE     1
 328 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 329
 330 #define CONFIG_SYS_BAUDRATE_TABLE \
 331         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 332
 333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 335
 336 /* Use the HUSH parser */
 337 #define CONFIG_SYS_HUSH_PARSER
 338
 339 /* pass open firmware flat tree */
 340 #define CONFIG_OF_LIBFDT                1
 341 #define CONFIG_OF_BOARD_SETUP           1
 342 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 343
 344 /*
 345  * I2C
 346  */
 347 #define CONFIG_SYS_I2C
 348 #define CONFIG_SYS_I2C_FSL
 349 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 350 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 351 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 352 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 353
 354 /* EEPROM */
 355 #define CONFIG_ID_EEPROM
 356 #define CONFIG_SYS_I2C_EEPROM_CCID
 357 #define CONFIG_SYS_ID_EEPROM
 358 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 359 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 360
 361 /*
 362  * General PCI
 363  * Memory space is mapped 1-1, but I/O space must start from 0.
 364  */
 365 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 366 #ifdef CONFIG_PHYS_64BIT
 367 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 368 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 369 #else
 370 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 371 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 372 #endif
 373 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 374 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 375 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 376 #ifdef CONFIG_PHYS_64BIT
 377 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 378 #else
 379 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 380 #endif
 381 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 382
 383 #ifdef CONFIG_PCIE1
 384 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 385 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 386 #ifdef CONFIG_PHYS_64BIT
 387 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 388 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc20000000ull
 389 #else
 390 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 391 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 392 #endif
 393 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 394 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe3000000
 395 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 396 #ifdef CONFIG_PHYS_64BIT
 397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 398 #else
 399 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 400 #endif
 401 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 402 #endif
 403
 404 /*
 405  * RapidIO MMU
 406  */
 407 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xc0000000
 408 #ifdef CONFIG_PHYS_64BIT
 409 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc40000000ull
 410 #else
 411 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc0000000
 412 #endif
 413 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 414
 415 #ifdef CONFIG_LEGACY
 416 #define BRIDGE_ID 17
 417 #define VIA_ID 2
 418 #else
 419 #define BRIDGE_ID 28
 420 #define VIA_ID 4
 421 #endif
 422
 423 #if defined(CONFIG_PCI)
 424
 425 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 426
 427 #undef CONFIG_EEPRO100
 428 #undef CONFIG_TULIP
 429
 430 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 431
 432 #endif  /* CONFIG_PCI */
 433
 434
 435 #if defined(CONFIG_TSEC_ENET)
 436
 437 #define CONFIG_MII              1       /* MII PHY management */
 438 #define CONFIG_TSEC1    1
 439 #define CONFIG_TSEC1_NAME       "eTSEC0"
 440 #define CONFIG_TSEC2    1
 441 #define CONFIG_TSEC2_NAME       "eTSEC1"
 442 #define CONFIG_TSEC3    1
 443 #define CONFIG_TSEC3_NAME       "eTSEC2"
 444 #define CONFIG_TSEC4
 445 #define CONFIG_TSEC4_NAME       "eTSEC3"
 446 #undef CONFIG_MPC85XX_FEC
 447
 448 #define CONFIG_PHY_MARVELL
 449
 450 #define TSEC1_PHY_ADDR          0
 451 #define TSEC2_PHY_ADDR          1
 452 #define TSEC3_PHY_ADDR          2
 453 #define TSEC4_PHY_ADDR          3
 454
 455 #define TSEC1_PHYIDX            0
 456 #define TSEC2_PHYIDX            0
 457 #define TSEC3_PHYIDX            0
 458 #define TSEC4_PHYIDX            0
 459 #define TSEC1_FLAGS             TSEC_GIGABIT
 460 #define TSEC2_FLAGS             TSEC_GIGABIT
 461 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 462 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 463
 464 /* Options are: eTSEC[0-3] */
 465 #define CONFIG_ETHPRIME         "eTSEC0"
 466 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 467 #endif  /* CONFIG_TSEC_ENET */
 468
 469 /*
 470  * Environment
 471  */
 472 #define CONFIG_ENV_IS_IN_FLASH  1
 473 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 474 #define CONFIG_ENV_ADDR 0xfff80000
 475 #else
 476 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 477 #endif
 478 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K for env */
 479 #define CONFIG_ENV_SIZE         0x2000
 480
 481 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 482 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 483
 484 /*
 485  * BOOTP options
 486  */
 487 #define CONFIG_BOOTP_BOOTFILESIZE
 488 #define CONFIG_BOOTP_BOOTPATH
 489 #define CONFIG_BOOTP_GATEWAY
 490 #define CONFIG_BOOTP_HOSTNAME
 491
 492
 493 /*
 494  * Command line configuration.
 495  */
 496 #define CONFIG_CMD_PING
 497 #define CONFIG_CMD_I2C
 498 #define CONFIG_CMD_MII
 499 #define CONFIG_CMD_ELF
 500 #define CONFIG_CMD_IRQ
 501 #define CONFIG_CMD_REGINFO
 502
 503 #if defined(CONFIG_PCI)
 504     #define CONFIG_CMD_PCI
 505 #endif
 506
 507
 508 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 509
 510 /*
 511  * Miscellaneous configurable options
 512  */
 513 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 514 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 515 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 516 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 517 #if defined(CONFIG_CMD_KGDB)
 518 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 519 #else
 520 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 521 #endif
 522 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 523 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 524 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 525
 526 /*
 527  * For booting Linux, the board info and command line data
 528  * have to be in the first 64 MB of memory, since this is
 529  * the maximum mapped by the Linux kernel during initialization.
 530  */
 531 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 532 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 533
 534 #if defined(CONFIG_CMD_KGDB)
 535 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 536 #endif
 537
 538 /*
 539  * Environment Configuration
 540  */
 541 #if defined(CONFIG_TSEC_ENET)
 542 #define CONFIG_HAS_ETH0
 543 #define CONFIG_HAS_ETH1
 544 #define CONFIG_HAS_ETH2
 545 #define CONFIG_HAS_ETH3
 546 #endif
 547
 548 #define CONFIG_IPADDR    192.168.1.253
 549
 550 #define CONFIG_HOSTNAME  unknown
 551 #define CONFIG_ROOTPATH  "/nfsroot"
 552 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
 553 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 554
 555 #define CONFIG_SERVERIP  192.168.1.1
 556 #define CONFIG_GATEWAYIP 192.168.1.1
 557 #define CONFIG_NETMASK   255.255.255.0
 558
 559 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 560
 561 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 562 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 563
 564 #define CONFIG_BAUDRATE 115200
 565
 566 #define CONFIG_EXTRA_ENV_SETTINGS               \
 567         "hwconfig=fsl_ddr:ecc=off\0"            \
 568         "netdev=eth0\0"                         \
 569         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 570         "tftpflash=tftpboot $loadaddr $uboot; " \
 571                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 572                         " +$filesize; " \
 573                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 574                         " +$filesize; " \
 575                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 576                         " $filesize; "  \
 577                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 578                         " +$filesize; " \
 579                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 580                         " $filesize\0"  \
 581         "consoledev=ttyS1\0"                    \
 582         "ramdiskaddr=2000000\0"                 \
 583         "ramdiskfile=ramdisk.uboot\0"           \
 584         "fdtaddr=c00000\0"                      \
 585         "fdtfile=mpc8548cds.dtb\0"
 586
 587 #define CONFIG_NFSBOOTCOMMAND                                           \
 588    "setenv bootargs root=/dev/nfs rw "                                  \
 589       "nfsroot=$serverip:$rootpath "                                    \
 590       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 591       "console=$consoledev,$baudrate $othbootargs;"                     \
 592    "tftp $loadaddr $bootfile;"                                          \
 593    "tftp $fdtaddr $fdtfile;"                                            \
 594    "bootm $loadaddr - $fdtaddr"
 595
 596
 597 #define CONFIG_RAMBOOTCOMMAND \
 598    "setenv bootargs root=/dev/ram rw "                                  \
 599       "console=$consoledev,$baudrate $othbootargs;"                     \
 600    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 601    "tftp $loadaddr $bootfile;"                                          \
 602    "tftp $fdtaddr $fdtfile;"                                            \
 603    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 604
 605 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 606
 607 #endif  /* __CONFIG_H */