include/configs/MPC8548CDS.h

   1 /*
   2  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8548cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #ifndef CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  18 #endif
  19
  20 #define CONFIG_SYS_SRIO
  21 #define CONFIG_SRIO1                    /* SRIO port 1 */
  22
  23 #define CONFIG_PCI1             /* PCI controller 1 */
  24 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  25 #undef CONFIG_PCI2
  26 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  27 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  28 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  29 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  30
  31 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  32 #define CONFIG_ENV_OVERWRITE
  33 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  34
  35 #define CONFIG_FSL_VIA
  36
  37 #ifndef __ASSEMBLY__
  38 extern unsigned long get_clock_freq(void);
  39 #endif
  40 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  41
  42 /*
  43  * These can be toggled for performance analysis, otherwise use default.
  44  */
  45 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  46 #define CONFIG_BTB                      /* toggle branch predition */
  47
  48 /*
  49  * Only possible on E500 Version 2 or newer cores.
  50  */
  51 #define CONFIG_ENABLE_36BIT_PHYS        1
  52
  53 #ifdef CONFIG_PHYS_64BIT
  54 #define CONFIG_ADDR_MAP
  55 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  56 #endif
  57
  58 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  59 #define CONFIG_SYS_MEMTEST_END          0x00400000
  60
  61 #define CONFIG_SYS_CCSRBAR              0xe0000000
  62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  63
  64 /* DDR Setup */
  65 #define CONFIG_SYS_FSL_DDR2
  66 #undef CONFIG_FSL_DDR_INTERACTIVE
  67 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  68 #define CONFIG_DDR_SPD
  69
  70 #define CONFIG_DDR_ECC
  71 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  72 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  73
  74 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  75 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  76
  77 #define CONFIG_NUM_DDR_CONTROLLERS      1
  78 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  79 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  80
  81 /* I2C addresses of SPD EEPROMs */
  82 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  83
  84 /* Make sure required options are set */
  85 #ifndef CONFIG_SPD_EEPROM
  86 #error ("CONFIG_SPD_EEPROM is required")
  87 #endif
  88
  89 #undef CONFIG_CLOCKS_IN_MHZ
  90 /*
  91  * Physical Address Map
  92  *
  93  * 32bit:
  94  * 0x0000_0000  0x7fff_ffff     DDR                     2G      cacheable
  95  * 0x8000_0000  0x9fff_ffff     PCI1 MEM                512M    cacheable
  96  * 0xa000_0000  0xbfff_ffff     PCIe MEM                512M    cacheable
  97  * 0xc000_0000  0xdfff_ffff     RapidIO                 512M    cacheable
  98  * 0xe000_0000  0xe00f_ffff     CCSR                    1M      non-cacheable
  99  * 0xe200_0000  0xe20f_ffff     PCI1 IO                 1M      non-cacheable
 100  * 0xe300_0000  0xe30f_ffff     PCIe IO                 1M      non-cacheable
 101  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M     cacheable
 102  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS            1M      non-cacheable
 103  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M      non-cacheable
 104  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M      non-cacheable
 105  *
 106  * 36bit:
 107  * 0x00000_0000 0x07fff_ffff    DDR                     2G      cacheable
 108  * 0xc0000_0000 0xc1fff_ffff    PCI1 MEM                512M    cacheable
 109  * 0xc2000_0000 0xc3fff_ffff    PCIe MEM                512M    cacheable
 110  * 0xc4000_0000 0xc5fff_ffff    RapidIO                 512M    cacheable
 111  * 0xfe000_0000 0xfe00f_ffff    CCSR                    1M      non-cacheable
 112  * 0xfe200_0000 0xfe20f_ffff    PCI1 IO                 1M      non-cacheable
 113  * 0xfe300_0000 0xfe30f_ffff    PCIe IO                 1M      non-cacheable
 114  * 0xff000_0000 0xff3ff_ffff    SDRAM                   64M     cacheable
 115  * 0xff800_0000 0xff80f_ffff    NVRAM/CADMUS            1M      non-cacheable
 116  * 0xfff00_0000 0xfff7f_ffff    FLASH (2nd bank)        8M      non-cacheable
 117  * 0xfff80_0000 0xfffff_ffff    FLASH (boot bank)       8M      non-cacheable
 118  *
 119  */
 120
 121 /*
 122  * Local Bus Definitions
 123  */
 124
 125 /*
 126  * FLASH on the Local Bus
 127  * Two banks, 8M each, using the CFI driver.
 128  * Boot from BR0/OR0 bank at 0xff00_0000
 129  * Alternate BR1/OR1 bank at 0xff80_0000
 130  *
 131  * BR0, BR1:
 132  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 133  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 134  *    Port Size = 16 bits = BRx[19:20] = 10
 135  *    Use GPCM = BRx[24:26] = 000
 136  *    Valid = BRx[31] = 1
 137  *
 138  * 0    4    8    12   16   20   24   28
 139  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 140  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 141  *
 142  * OR0, OR1:
 143  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 144  *    Reserved ORx[17:18] = 11, confusion here?
 145  *    CSNT = ORx[20] = 1
 146  *    ACS = half cycle delay = ORx[21:22] = 11
 147  *    SCY = 6 = ORx[24:27] = 0110
 148  *    TRLX = use relaxed timing = ORx[29] = 1
 149  *    EAD = use external address latch delay = OR[31] = 1
 150  *
 151  * 0    4    8    12   16   20   24   28
 152  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 153  */
 154
 155 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfff000000ull
 158 #else
 159 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 160 #endif
 161
 162 #define CONFIG_SYS_BR0_PRELIM \
 163         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
 164 #define CONFIG_SYS_BR1_PRELIM \
 165         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 166
 167 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 168 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 169
 170 #define CONFIG_SYS_FLASH_BANKS_LIST \
 171         {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
 172 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 173 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 174 #undef  CONFIG_SYS_FLASH_CHECKSUM
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177
 178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 179
 180 #define CONFIG_FLASH_CFI_DRIVER
 181 #define CONFIG_SYS_FLASH_CFI
 182 #define CONFIG_SYS_FLASH_EMPTY_INFO
 183
 184 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 185
 186 /*
 187  * SDRAM on the Local Bus
 188  */
 189 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 190 #ifdef CONFIG_PHYS_64BIT
 191 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  0xff0000000ull
 192 #else
 193 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  CONFIG_SYS_LBC_SDRAM_BASE
 194 #endif
 195 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 196
 197 /*
 198  * Base Register 2 and Option Register 2 configure SDRAM.
 199  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 200  *
 201  * For BR2, need:
 202  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 203  *    port-size = 32-bits = BR2[19:20] = 11
 204  *    no parity checking = BR2[21:22] = 00
 205  *    SDRAM for MSEL = BR2[24:26] = 011
 206  *    Valid = BR[31] = 1
 207  *
 208  * 0    4    8    12   16   20   24   28
 209  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 210  *
 211  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 212  * FIXME: the top 17 bits of BR2.
 213  */
 214
 215 #define CONFIG_SYS_BR2_PRELIM \
 216         (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
 217         | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
 218
 219 /*
 220  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 221  *
 222  * For OR2, need:
 223  *    64MB mask for AM, OR2[0:7] = 1111 1100
 224  *                 XAM, OR2[17:18] = 11
 225  *    9 columns OR2[19-21] = 010
 226  *    13 rows   OR2[23-25] = 100
 227  *    EAD set for extra time OR[31] = 1
 228  *
 229  * 0    4    8    12   16   20   24   28
 230  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 231  */
 232
 233 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 234
 235 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 236 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 237 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 238 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 239
 240 /*
 241  * Common settings for all Local Bus SDRAM commands.
 242  * At run time, either BSMA1516 (for CPU 1.1)
 243  *                  or BSMA1617 (for CPU 1.0) (old)
 244  * is OR'ed in too.
 245  */
 246 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 247                                 | LSDMR_PRETOACT7       \
 248                                 | LSDMR_ACTTORW7        \
 249                                 | LSDMR_BL8             \
 250                                 | LSDMR_WRC4            \
 251                                 | LSDMR_CL3             \
 252                                 | LSDMR_RFEN            \
 253                                 )
 254
 255 /*
 256  * The CADMUS registers are connected to CS3 on CDS.
 257  * The new memory map places CADMUS at 0xf8000000.
 258  *
 259  * For BR3, need:
 260  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 261  *    port-size = 8-bits  = BR[19:20] = 01
 262  *    no parity checking  = BR[21:22] = 00
 263  *    GPMC for MSEL       = BR[24:26] = 000
 264  *    Valid               = BR[31]    = 1
 265  *
 266  * 0    4    8    12   16   20   24   28
 267  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 268  *
 269  * For OR3, need:
 270  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 271  *    disable buffer ctrl OR[19]    = 0
 272  *    CSNT                OR[20]    = 1
 273  *    ACS                 OR[21:22] = 11
 274  *    XACS                OR[23]    = 1
 275  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 276  *    SETA                OR[28]    = 0
 277  *    TRLX                OR[29]    = 1
 278  *    EHTR                OR[30]    = 1
 279  *    EAD extra time      OR[31]    = 1
 280  *
 281  * 0    4    8    12   16   20   24   28
 282  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 283  */
 284
 285 #define CONFIG_FSL_CADMUS
 286
 287 #define CADMUS_BASE_ADDR 0xf8000000
 288 #ifdef CONFIG_PHYS_64BIT
 289 #define CADMUS_BASE_ADDR_PHYS   0xff8000000ull
 290 #else
 291 #define CADMUS_BASE_ADDR_PHYS   CADMUS_BASE_ADDR
 292 #endif
 293 #define CONFIG_SYS_BR3_PRELIM \
 294         (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
 295 #define CONFIG_SYS_OR3_PRELIM    0xfff00ff7
 296
 297 #define CONFIG_SYS_INIT_RAM_LOCK        1
 298 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 299 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 300
 301 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 302 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 303
 304 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 305 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 306
 307 /* Serial Port */
 308 #define CONFIG_CONS_INDEX       2
 309 #define CONFIG_SYS_NS16550_SERIAL
 310 #define CONFIG_SYS_NS16550_REG_SIZE     1
 311 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 312
 313 #define CONFIG_SYS_BAUDRATE_TABLE \
 314         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 315
 316 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 317 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 318
 319 /*
 320  * I2C
 321  */
 322 #define CONFIG_SYS_I2C
 323 #define CONFIG_SYS_I2C_FSL
 324 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 325 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 326 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 327 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 328
 329 /* EEPROM */
 330 #define CONFIG_ID_EEPROM
 331 #define CONFIG_SYS_I2C_EEPROM_CCID
 332 #define CONFIG_SYS_ID_EEPROM
 333 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 335
 336 /*
 337  * General PCI
 338  * Memory space is mapped 1-1, but I/O space must start from 0.
 339  */
 340 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 341 #ifdef CONFIG_PHYS_64BIT
 342 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 343 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 344 #else
 345 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 346 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 347 #endif
 348 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 349 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 350 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 351 #ifdef CONFIG_PHYS_64BIT
 352 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 353 #else
 354 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 355 #endif
 356 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 357
 358 #ifdef CONFIG_PCIE1
 359 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 360 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 361 #ifdef CONFIG_PHYS_64BIT
 362 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 363 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc20000000ull
 364 #else
 365 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 366 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 367 #endif
 368 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 369 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe3000000
 370 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 371 #ifdef CONFIG_PHYS_64BIT
 372 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 373 #else
 374 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 375 #endif
 376 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 377 #endif
 378
 379 /*
 380  * RapidIO MMU
 381  */
 382 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xc0000000
 383 #ifdef CONFIG_PHYS_64BIT
 384 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc40000000ull
 385 #else
 386 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc0000000
 387 #endif
 388 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 389
 390 #ifdef CONFIG_LEGACY
 391 #define BRIDGE_ID 17
 392 #define VIA_ID 2
 393 #else
 394 #define BRIDGE_ID 28
 395 #define VIA_ID 4
 396 #endif
 397
 398 #if defined(CONFIG_PCI)
 399 #undef CONFIG_EEPRO100
 400 #undef CONFIG_TULIP
 401
 402 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 403
 404 #endif  /* CONFIG_PCI */
 405
 406 #if defined(CONFIG_TSEC_ENET)
 407
 408 #define CONFIG_MII              1       /* MII PHY management */
 409 #define CONFIG_TSEC1    1
 410 #define CONFIG_TSEC1_NAME       "eTSEC0"
 411 #define CONFIG_TSEC2    1
 412 #define CONFIG_TSEC2_NAME       "eTSEC1"
 413 #define CONFIG_TSEC3    1
 414 #define CONFIG_TSEC3_NAME       "eTSEC2"
 415 #define CONFIG_TSEC4
 416 #define CONFIG_TSEC4_NAME       "eTSEC3"
 417 #undef CONFIG_MPC85XX_FEC
 418
 419 #define CONFIG_PHY_MARVELL
 420
 421 #define TSEC1_PHY_ADDR          0
 422 #define TSEC2_PHY_ADDR          1
 423 #define TSEC3_PHY_ADDR          2
 424 #define TSEC4_PHY_ADDR          3
 425
 426 #define TSEC1_PHYIDX            0
 427 #define TSEC2_PHYIDX            0
 428 #define TSEC3_PHYIDX            0
 429 #define TSEC4_PHYIDX            0
 430 #define TSEC1_FLAGS             TSEC_GIGABIT
 431 #define TSEC2_FLAGS             TSEC_GIGABIT
 432 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 433 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 434
 435 /* Options are: eTSEC[0-3] */
 436 #define CONFIG_ETHPRIME         "eTSEC0"
 437 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 438 #endif  /* CONFIG_TSEC_ENET */
 439
 440 /*
 441  * Environment
 442  */
 443 #define CONFIG_ENV_IS_IN_FLASH  1
 444 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 445 #define CONFIG_ENV_ADDR 0xfff80000
 446 #else
 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 448 #endif
 449 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K for env */
 450 #define CONFIG_ENV_SIZE         0x2000
 451
 452 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 454
 455 /*
 456  * BOOTP options
 457  */
 458 #define CONFIG_BOOTP_BOOTFILESIZE
 459 #define CONFIG_BOOTP_BOOTPATH
 460 #define CONFIG_BOOTP_GATEWAY
 461 #define CONFIG_BOOTP_HOSTNAME
 462
 463 /*
 464  * Command line configuration.
 465  */
 466 #define CONFIG_CMD_IRQ
 467 #define CONFIG_CMD_REGINFO
 468
 469 #if defined(CONFIG_PCI)
 470     #define CONFIG_CMD_PCI
 471 #endif
 472
 473 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 474
 475 /*
 476  * Miscellaneous configurable options
 477  */
 478 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 479 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 480 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 481 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 482 #if defined(CONFIG_CMD_KGDB)
 483 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 484 #else
 485 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 486 #endif
 487 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 488 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 489 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 490
 491 /*
 492  * For booting Linux, the board info and command line data
 493  * have to be in the first 64 MB of memory, since this is
 494  * the maximum mapped by the Linux kernel during initialization.
 495  */
 496 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 497 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 498
 499 #if defined(CONFIG_CMD_KGDB)
 500 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 501 #endif
 502
 503 /*
 504  * Environment Configuration
 505  */
 506 #if defined(CONFIG_TSEC_ENET)
 507 #define CONFIG_HAS_ETH0
 508 #define CONFIG_HAS_ETH1
 509 #define CONFIG_HAS_ETH2
 510 #define CONFIG_HAS_ETH3
 511 #endif
 512
 513 #define CONFIG_IPADDR    192.168.1.253
 514
 515 #define CONFIG_HOSTNAME  unknown
 516 #define CONFIG_ROOTPATH  "/nfsroot"
 517 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
 518 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 519
 520 #define CONFIG_SERVERIP  192.168.1.1
 521 #define CONFIG_GATEWAYIP 192.168.1.1
 522 #define CONFIG_NETMASK   255.255.255.0
 523
 524 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 525
 526 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 527
 528 #define CONFIG_BAUDRATE 115200
 529
 530 #define CONFIG_EXTRA_ENV_SETTINGS               \
 531         "hwconfig=fsl_ddr:ecc=off\0"            \
 532         "netdev=eth0\0"                         \
 533         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 534         "tftpflash=tftpboot $loadaddr $uboot; " \
 535                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 536                         " +$filesize; " \
 537                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 538                         " +$filesize; " \
 539                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 540                         " $filesize; "  \
 541                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 542                         " +$filesize; " \
 543                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 544                         " $filesize\0"  \
 545         "consoledev=ttyS1\0"                    \
 546         "ramdiskaddr=2000000\0"                 \
 547         "ramdiskfile=ramdisk.uboot\0"           \
 548         "fdtaddr=1e00000\0"                     \
 549         "fdtfile=mpc8548cds.dtb\0"
 550
 551 #define CONFIG_NFSBOOTCOMMAND                                           \
 552    "setenv bootargs root=/dev/nfs rw "                                  \
 553       "nfsroot=$serverip:$rootpath "                                    \
 554       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 555       "console=$consoledev,$baudrate $othbootargs;"                     \
 556    "tftp $loadaddr $bootfile;"                                          \
 557    "tftp $fdtaddr $fdtfile;"                                            \
 558    "bootm $loadaddr - $fdtaddr"
 559
 560 #define CONFIG_RAMBOOTCOMMAND \
 561    "setenv bootargs root=/dev/ram rw "                                  \
 562       "console=$consoledev,$baudrate $othbootargs;"                     \
 563    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 564    "tftp $loadaddr $bootfile;"                                          \
 565    "tftp $fdtaddr $fdtfile;"                                            \
 566    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 567
 568 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 569
 570 #endif  /* __CONFIG_H */