include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8555cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41 */
  36 #define CONFIG_CPM2             1       /* has CPM2 */
  37 #define CONFIG_MPC8555          1       /* MPC8555 specific */
  38 #define CONFIG_MPC8555CDS       1       /* MPC8555CDS board specific */
  39
  40 #define CONFIG_PCI
  41 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  42 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  43 #define CONFIG_ENV_OVERWRITE
  44 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  45
  46 #define CONFIG_FSL_VIA
  47
  48
  49 /*
  50  * When initializing flash, if we cannot find the manufacturer ID,
  51  * assume this is the AMD flash associated with the CDS board.
  52  * This allows booting from a promjet.
  53  */
  54 #define CONFIG_ASSUME_AMD_FLASH
  55
  56 #ifndef __ASSEMBLY__
  57 extern unsigned long get_clock_freq(void);
  58 #endif
  59 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  60
  61 /*
  62  * These can be toggled for performance analysis, otherwise use default.
  63  */
  64 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  65 #define CONFIG_BTB                          /* toggle branch predition */
  66
  67 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  68 #define CONFIG_SYS_MEMTEST_END          0x00400000
  69
  70 /*
  71  * Base addresses -- Note these are effective addresses where the
  72  * actual resources get mapped (not physical addresses)
  73  */
  74 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  75 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  76 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  77 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  78
  79 /* DDR Setup */
  80 #define CONFIG_FSL_DDR1
  81 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  82 #define CONFIG_DDR_SPD
  83 #undef CONFIG_FSL_DDR_INTERACTIVE
  84
  85 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  86
  87 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  88 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  89
  90 #define CONFIG_NUM_DDR_CONTROLLERS      1
  91 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  92 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  93
  94 /* I2C addresses of SPD EEPROMs */
  95 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  96
  97 /* Make sure required options are set */
  98 #ifndef CONFIG_SPD_EEPROM
  99 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 100 #endif
 101
 102 #undef CONFIG_CLOCKS_IN_MHZ
 103
 104 /*
 105  * Local Bus Definitions
 106  */
 107
 108 /*
 109  * FLASH on the Local Bus
 110  * Two banks, 8M each, using the CFI driver.
 111  * Boot from BR0/OR0 bank at 0xff00_0000
 112  * Alternate BR1/OR1 bank at 0xff80_0000
 113  *
 114  * BR0, BR1:
 115  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 116  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 117  *    Port Size = 16 bits = BRx[19:20] = 10
 118  *    Use GPCM = BRx[24:26] = 000
 119  *    Valid = BRx[31] = 1
 120  *
 121  * 0    4    8    12   16   20   24   28
 122  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 123  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 124  *
 125  * OR0, OR1:
 126  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 127  *    Reserved ORx[17:18] = 11, confusion here?
 128  *    CSNT = ORx[20] = 1
 129  *    ACS = half cycle delay = ORx[21:22] = 11
 130  *    SCY = 6 = ORx[24:27] = 0110
 131  *    TRLX = use relaxed timing = ORx[29] = 1
 132  *    EAD = use external address latch delay = OR[31] = 1
 133  *
 134  * 0    4    8    12   16   20   24   28
 135  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 136  */
 137
 138 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 139
 140 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 141 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 142
 143 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 144 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 145
 146 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 147 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 148 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 149 #undef  CONFIG_SYS_FLASH_CHECKSUM
 150 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 151 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 152
 153 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 154
 155 #define CONFIG_FLASH_CFI_DRIVER
 156 #define CONFIG_SYS_FLASH_CFI
 157 #define CONFIG_SYS_FLASH_EMPTY_INFO
 158
 159
 160 /*
 161  * SDRAM on the Local Bus
 162  */
 163 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 164 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 165
 166 /*
 167  * Base Register 2 and Option Register 2 configure SDRAM.
 168  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 169  *
 170  * For BR2, need:
 171  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 172  *    port-size = 32-bits = BR2[19:20] = 11
 173  *    no parity checking = BR2[21:22] = 00
 174  *    SDRAM for MSEL = BR2[24:26] = 011
 175  *    Valid = BR[31] = 1
 176  *
 177  * 0    4    8    12   16   20   24   28
 178  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 179  *
 180  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 181  * FIXME: the top 17 bits of BR2.
 182  */
 183
 184 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 185
 186 /*
 187  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 188  *
 189  * For OR2, need:
 190  *    64MB mask for AM, OR2[0:7] = 1111 1100
 191  *                 XAM, OR2[17:18] = 11
 192  *    9 columns OR2[19-21] = 010
 193  *    13 rows   OR2[23-25] = 100
 194  *    EAD set for extra time OR[31] = 1
 195  *
 196  * 0    4    8    12   16   20   24   28
 197  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 198  */
 199
 200 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 201
 202 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 203 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 204 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 205 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 206
 207 /*
 208  * Common settings for all Local Bus SDRAM commands.
 209  * At run time, either BSMA1516 (for CPU 1.1)
 210  *                  or BSMA1617 (for CPU 1.0) (old)
 211  * is OR'ed in too.
 212  */
 213 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 214                                 | LSDMR_PRETOACT7       \
 215                                 | LSDMR_ACTTORW7        \
 216                                 | LSDMR_BL8             \
 217                                 | LSDMR_WRC4            \
 218                                 | LSDMR_CL3             \
 219                                 | LSDMR_RFEN            \
 220                                 )
 221
 222 /*
 223  * The CADMUS registers are connected to CS3 on CDS.
 224  * The new memory map places CADMUS at 0xf8000000.
 225  *
 226  * For BR3, need:
 227  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 228  *    port-size = 8-bits  = BR[19:20] = 01
 229  *    no parity checking  = BR[21:22] = 00
 230  *    GPMC for MSEL       = BR[24:26] = 000
 231  *    Valid               = BR[31]    = 1
 232  *
 233  * 0    4    8    12   16   20   24   28
 234  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 235  *
 236  * For OR3, need:
 237  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 238  *    disable buffer ctrl OR[19]    = 0
 239  *    CSNT                OR[20]    = 1
 240  *    ACS                 OR[21:22] = 11
 241  *    XACS                OR[23]    = 1
 242  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 243  *    SETA                OR[28]    = 0
 244  *    TRLX                OR[29]    = 1
 245  *    EHTR                OR[30]    = 1
 246  *    EAD extra time      OR[31]    = 1
 247  *
 248  * 0    4    8    12   16   20   24   28
 249  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 250  */
 251
 252 #define CONFIG_FSL_CADMUS
 253
 254 #define CADMUS_BASE_ADDR 0xf8000000
 255 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 256 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 257
 258 #define CONFIG_SYS_INIT_RAM_LOCK        1
 259 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 260 #define CONFIG_SYS_INIT_RAM_END 0x4000      /* End of used area in RAM */
 261
 262 #define CONFIG_SYS_GBL_DATA_SIZE        128         /* num bytes initial data */
 263 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 264 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 265
 266 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 267 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 268
 269 /* Serial Port */
 270 #define CONFIG_CONS_INDEX     2
 271 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 272 #define CONFIG_SYS_NS16550
 273 #define CONFIG_SYS_NS16550_SERIAL
 274 #define CONFIG_SYS_NS16550_REG_SIZE    1
 275 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 276
 277 #define CONFIG_SYS_BAUDRATE_TABLE  \
 278         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 279
 280 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 281 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 282
 283 /* Use the HUSH parser */
 284 #define CONFIG_SYS_HUSH_PARSER
 285 #ifdef  CONFIG_SYS_HUSH_PARSER
 286 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 287 #endif
 288
 289 /* pass open firmware flat tree */
 290 #define CONFIG_OF_LIBFDT                1
 291 #define CONFIG_OF_BOARD_SETUP           1
 292 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 293
 294 #define CONFIG_SYS_64BIT_VSPRINTF       1
 295 #define CONFIG_SYS_64BIT_STRTOUL        1
 296
 297 /*
 298  * I2C
 299  */
 300 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 301 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 302 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 303 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 304 #define CONFIG_SYS_I2C_SLAVE            0x7F
 305 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 306 #define CONFIG_SYS_I2C_OFFSET           0x3000
 307
 308 /* EEPROM */
 309 #define CONFIG_ID_EEPROM
 310 #define CONFIG_SYS_I2C_EEPROM_CCID
 311 #define CONFIG_SYS_ID_EEPROM
 312 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 313 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 314
 315 /*
 316  * General PCI
 317  * Addresses are mapped 1-1.
 318  */
 319 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 320 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 321 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 322 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 323 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 324 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 325 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 326 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 327
 328 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 329 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 330 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 331 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 332 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 333 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 334 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 335 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 336
 337 #ifdef CONFIG_LEGACY
 338 #define BRIDGE_ID 17
 339 #define VIA_ID 2
 340 #else
 341 #define BRIDGE_ID 28
 342 #define VIA_ID 4
 343 #endif
 344
 345 #if defined(CONFIG_PCI)
 346
 347 #define CONFIG_NET_MULTI
 348 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 349 #define CONFIG_MPC85XX_PCI2
 350
 351 #undef CONFIG_EEPRO100
 352 #undef CONFIG_TULIP
 353
 354 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 355 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 356
 357 #endif  /* CONFIG_PCI */
 358
 359
 360 #if defined(CONFIG_TSEC_ENET)
 361
 362 #ifndef CONFIG_NET_MULTI
 363 #define CONFIG_NET_MULTI        1
 364 #endif
 365
 366 #define CONFIG_MII              1       /* MII PHY management */
 367 #define CONFIG_TSEC1    1
 368 #define CONFIG_TSEC1_NAME       "TSEC0"
 369 #define CONFIG_TSEC2    1
 370 #define CONFIG_TSEC2_NAME       "TSEC1"
 371 #define TSEC1_PHY_ADDR          0
 372 #define TSEC2_PHY_ADDR          1
 373 #define TSEC1_PHYIDX            0
 374 #define TSEC2_PHYIDX            0
 375 #define TSEC1_FLAGS             TSEC_GIGABIT
 376 #define TSEC2_FLAGS             TSEC_GIGABIT
 377
 378 /* Options are: TSEC[0-1] */
 379 #define CONFIG_ETHPRIME         "TSEC0"
 380
 381 #endif  /* CONFIG_TSEC_ENET */
 382
 383 /*
 384  * Environment
 385  */
 386 #define CONFIG_ENV_IS_IN_FLASH  1
 387 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 388 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 389 #define CONFIG_ENV_SIZE         0x2000
 390
 391 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 392 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 393
 394 /*
 395  * BOOTP options
 396  */
 397 #define CONFIG_BOOTP_BOOTFILESIZE
 398 #define CONFIG_BOOTP_BOOTPATH
 399 #define CONFIG_BOOTP_GATEWAY
 400 #define CONFIG_BOOTP_HOSTNAME
 401
 402
 403 /*
 404  * Command line configuration.
 405  */
 406 #include <config_cmd_default.h>
 407
 408 #define CONFIG_CMD_PING
 409 #define CONFIG_CMD_I2C
 410 #define CONFIG_CMD_MII
 411 #define CONFIG_CMD_ELF
 412 #define CONFIG_CMD_IRQ
 413 #define CONFIG_CMD_SETEXPR
 414
 415 #if defined(CONFIG_PCI)
 416     #define CONFIG_CMD_PCI
 417 #endif
 418
 419
 420 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 421
 422 /*
 423  * Miscellaneous configurable options
 424  */
 425 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 426 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 427 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 428 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 429 #if defined(CONFIG_CMD_KGDB)
 430 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 431 #else
 432 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 433 #endif
 434 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 435 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 436 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 437 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 438
 439 /*
 440  * For booting Linux, the board info and command line data
 441  * have to be in the first 16 MB of memory, since this is
 442  * the maximum mapped by the Linux kernel during initialization.
 443  */
 444 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 445
 446 /*
 447  * Internal Definitions
 448  *
 449  * Boot Flags
 450  */
 451 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 452 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 453
 454 #if defined(CONFIG_CMD_KGDB)
 455 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 456 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 457 #endif
 458
 459 /*
 460  * Environment Configuration
 461  */
 462
 463 /* The mac addresses for all ethernet interface */
 464 #if defined(CONFIG_TSEC_ENET)
 465 #define CONFIG_HAS_ETH0
 466 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 467 #define CONFIG_HAS_ETH1
 468 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 469 #define CONFIG_HAS_ETH2
 470 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 471 #endif
 472
 473 #define CONFIG_IPADDR    192.168.1.253
 474
 475 #define CONFIG_HOSTNAME  unknown
 476 #define CONFIG_ROOTPATH  /nfsroot
 477 #define CONFIG_BOOTFILE  your.uImage
 478
 479 #define CONFIG_SERVERIP  192.168.1.1
 480 #define CONFIG_GATEWAYIP 192.168.1.1
 481 #define CONFIG_NETMASK   255.255.255.0
 482
 483 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 484
 485 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 486 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 487
 488 #define CONFIG_BAUDRATE 115200
 489
 490 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 491    "netdev=eth0\0"                                                      \
 492    "consoledev=ttyS1\0"                                                 \
 493    "ramdiskaddr=600000\0"                                               \
 494    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 495    "fdtaddr=400000\0"                                                   \
 496    "fdtfile=your.fdt.dtb\0"
 497
 498 #define CONFIG_NFSBOOTCOMMAND                                           \
 499    "setenv bootargs root=/dev/nfs rw "                                  \
 500       "nfsroot=$serverip:$rootpath "                                    \
 501       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 502       "console=$consoledev,$baudrate $othbootargs;"                     \
 503    "tftp $loadaddr $bootfile;"                                          \
 504    "tftp $fdtaddr $fdtfile;"                                            \
 505    "bootm $loadaddr - $fdtaddr"
 506
 507 #define CONFIG_RAMBOOTCOMMAND \
 508    "setenv bootargs root=/dev/ram rw "                                  \
 509       "console=$consoledev,$baudrate $othbootargs;"                     \
 510    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 511    "tftp $loadaddr $bootfile;"                                          \
 512    "bootm $loadaddr $ramdiskaddr"
 513
 514 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 515
 516 #endif  /* __CONFIG_H */