include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8555cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_CPM2             1       /* has CPM2 */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  20
  21 #define CONFIG_PCI_INDIRECT_BRIDGE
  22 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  23 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  24 #define CONFIG_ENV_OVERWRITE
  25
  26 #define CONFIG_FSL_VIA
  27
  28 #ifndef __ASSEMBLY__
  29 extern unsigned long get_clock_freq(void);
  30 #endif
  31 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  32
  33 /*
  34  * These can be toggled for performance analysis, otherwise use default.
  35  */
  36 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  37 #define CONFIG_BTB                          /* toggle branch predition */
  38
  39 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  40 #define CONFIG_SYS_MEMTEST_END          0x00400000
  41
  42 #define CONFIG_SYS_CCSRBAR              0xe0000000
  43 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  44
  45 /* DDR Setup */
  46 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  47 #define CONFIG_DDR_SPD
  48 #undef CONFIG_FSL_DDR_INTERACTIVE
  49
  50 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  51
  52 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  53 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  54
  55 #define CONFIG_NUM_DDR_CONTROLLERS      1
  56 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  57 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  58
  59 /* I2C addresses of SPD EEPROMs */
  60 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  61
  62 /* Make sure required options are set */
  63 #ifndef CONFIG_SPD_EEPROM
  64 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  65 #endif
  66
  67 #undef CONFIG_CLOCKS_IN_MHZ
  68
  69 /*
  70  * Local Bus Definitions
  71  */
  72
  73 /*
  74  * FLASH on the Local Bus
  75  * Two banks, 8M each, using the CFI driver.
  76  * Boot from BR0/OR0 bank at 0xff00_0000
  77  * Alternate BR1/OR1 bank at 0xff80_0000
  78  *
  79  * BR0, BR1:
  80  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  81  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  82  *    Port Size = 16 bits = BRx[19:20] = 10
  83  *    Use GPCM = BRx[24:26] = 000
  84  *    Valid = BRx[31] = 1
  85  *
  86  * 0    4    8    12   16   20   24   28
  87  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
  88  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
  89  *
  90  * OR0, OR1:
  91  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  92  *    Reserved ORx[17:18] = 11, confusion here?
  93  *    CSNT = ORx[20] = 1
  94  *    ACS = half cycle delay = ORx[21:22] = 11
  95  *    SCY = 6 = ORx[24:27] = 0110
  96  *    TRLX = use relaxed timing = ORx[29] = 1
  97  *    EAD = use external address latch delay = OR[31] = 1
  98  *
  99  * 0    4    8    12   16   20   24   28
 100  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 101  */
 102
 103 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 104
 105 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 106 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 107
 108 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 109 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 110
 111 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 113 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 114 #undef  CONFIG_SYS_FLASH_CHECKSUM
 115 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 116 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 117
 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 119
 120 #define CONFIG_FLASH_CFI_DRIVER
 121 #define CONFIG_SYS_FLASH_CFI
 122 #define CONFIG_SYS_FLASH_EMPTY_INFO
 123
 124 /*
 125  * SDRAM on the Local Bus
 126  */
 127 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 128 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 129
 130 /*
 131  * Base Register 2 and Option Register 2 configure SDRAM.
 132  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 133  *
 134  * For BR2, need:
 135  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 136  *    port-size = 32-bits = BR2[19:20] = 11
 137  *    no parity checking = BR2[21:22] = 00
 138  *    SDRAM for MSEL = BR2[24:26] = 011
 139  *    Valid = BR[31] = 1
 140  *
 141  * 0    4    8    12   16   20   24   28
 142  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 143  *
 144  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 145  * FIXME: the top 17 bits of BR2.
 146  */
 147
 148 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 149
 150 /*
 151  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 152  *
 153  * For OR2, need:
 154  *    64MB mask for AM, OR2[0:7] = 1111 1100
 155  *                 XAM, OR2[17:18] = 11
 156  *    9 columns OR2[19-21] = 010
 157  *    13 rows   OR2[23-25] = 100
 158  *    EAD set for extra time OR[31] = 1
 159  *
 160  * 0    4    8    12   16   20   24   28
 161  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 162  */
 163
 164 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 165
 166 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 167 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 168 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 169 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 170
 171 /*
 172  * Common settings for all Local Bus SDRAM commands.
 173  * At run time, either BSMA1516 (for CPU 1.1)
 174  *                  or BSMA1617 (for CPU 1.0) (old)
 175  * is OR'ed in too.
 176  */
 177 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 178                                 | LSDMR_PRETOACT7       \
 179                                 | LSDMR_ACTTORW7        \
 180                                 | LSDMR_BL8             \
 181                                 | LSDMR_WRC4            \
 182                                 | LSDMR_CL3             \
 183                                 | LSDMR_RFEN            \
 184                                 )
 185
 186 /*
 187  * The CADMUS registers are connected to CS3 on CDS.
 188  * The new memory map places CADMUS at 0xf8000000.
 189  *
 190  * For BR3, need:
 191  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 192  *    port-size = 8-bits  = BR[19:20] = 01
 193  *    no parity checking  = BR[21:22] = 00
 194  *    GPMC for MSEL       = BR[24:26] = 000
 195  *    Valid               = BR[31]    = 1
 196  *
 197  * 0    4    8    12   16   20   24   28
 198  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 199  *
 200  * For OR3, need:
 201  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 202  *    disable buffer ctrl OR[19]    = 0
 203  *    CSNT                OR[20]    = 1
 204  *    ACS                 OR[21:22] = 11
 205  *    XACS                OR[23]    = 1
 206  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 207  *    SETA                OR[28]    = 0
 208  *    TRLX                OR[29]    = 1
 209  *    EHTR                OR[30]    = 1
 210  *    EAD extra time      OR[31]    = 1
 211  *
 212  * 0    4    8    12   16   20   24   28
 213  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 214  */
 215
 216 #define CONFIG_FSL_CADMUS
 217
 218 #define CADMUS_BASE_ADDR 0xf8000000
 219 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 220 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 221
 222 #define CONFIG_SYS_INIT_RAM_LOCK        1
 223 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 224 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 225
 226 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 227 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 228
 229 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 230 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 231
 232 /* Serial Port */
 233 #define CONFIG_CONS_INDEX     2
 234 #define CONFIG_SYS_NS16550_SERIAL
 235 #define CONFIG_SYS_NS16550_REG_SIZE    1
 236 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 237
 238 #define CONFIG_SYS_BAUDRATE_TABLE  \
 239         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 240
 241 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 242 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 243
 244 /*
 245  * I2C
 246  */
 247 #define CONFIG_SYS_I2C
 248 #define CONFIG_SYS_I2C_FSL
 249 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 250 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 251 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 252 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 253
 254 /* EEPROM */
 255 #define CONFIG_ID_EEPROM
 256 #define CONFIG_SYS_I2C_EEPROM_CCID
 257 #define CONFIG_SYS_ID_EEPROM
 258 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 260
 261 /*
 262  * General PCI
 263  * Addresses are mapped 1-1.
 264  */
 265 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 266 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 267 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 268 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 269 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 270 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 271 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 272 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 273
 274 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 275 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 276 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 277 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 278 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 279 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 280 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 281 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 282
 283 #ifdef CONFIG_LEGACY
 284 #define BRIDGE_ID 17
 285 #define VIA_ID 2
 286 #else
 287 #define BRIDGE_ID 28
 288 #define VIA_ID 4
 289 #endif
 290
 291 #if defined(CONFIG_PCI)
 292
 293 #define CONFIG_MPC85XX_PCI2
 294
 295 #undef CONFIG_EEPRO100
 296 #undef CONFIG_TULIP
 297
 298 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 299 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 300
 301 #endif  /* CONFIG_PCI */
 302
 303 #if defined(CONFIG_TSEC_ENET)
 304
 305 #define CONFIG_MII              1       /* MII PHY management */
 306 #define CONFIG_TSEC1    1
 307 #define CONFIG_TSEC1_NAME       "TSEC0"
 308 #define CONFIG_TSEC2    1
 309 #define CONFIG_TSEC2_NAME       "TSEC1"
 310 #define TSEC1_PHY_ADDR          0
 311 #define TSEC2_PHY_ADDR          1
 312 #define TSEC1_PHYIDX            0
 313 #define TSEC2_PHYIDX            0
 314 #define TSEC1_FLAGS             TSEC_GIGABIT
 315 #define TSEC2_FLAGS             TSEC_GIGABIT
 316
 317 /* Options are: TSEC[0-1] */
 318 #define CONFIG_ETHPRIME         "TSEC0"
 319
 320 #endif  /* CONFIG_TSEC_ENET */
 321
 322 /*
 323  * Environment
 324  */
 325 #define CONFIG_ENV_IS_IN_FLASH  1
 326 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 327 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 328 #define CONFIG_ENV_SIZE         0x2000
 329
 330 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 331 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 332
 333 /*
 334  * BOOTP options
 335  */
 336 #define CONFIG_BOOTP_BOOTFILESIZE
 337 #define CONFIG_BOOTP_BOOTPATH
 338 #define CONFIG_BOOTP_GATEWAY
 339 #define CONFIG_BOOTP_HOSTNAME
 340
 341 /*
 342  * Command line configuration.
 343  */
 344 #define CONFIG_CMD_IRQ
 345 #define CONFIG_CMD_REGINFO
 346
 347 #if defined(CONFIG_PCI)
 348     #define CONFIG_CMD_PCI
 349 #endif
 350
 351 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 352
 353 /*
 354  * Miscellaneous configurable options
 355  */
 356 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 357 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 358 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 359 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 360 #if defined(CONFIG_CMD_KGDB)
 361 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 362 #else
 363 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 364 #endif
 365 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 366 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 367 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 368
 369 /*
 370  * For booting Linux, the board info and command line data
 371  * have to be in the first 64 MB of memory, since this is
 372  * the maximum mapped by the Linux kernel during initialization.
 373  */
 374 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 375 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 376
 377 #if defined(CONFIG_CMD_KGDB)
 378 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 379 #endif
 380
 381 /*
 382  * Environment Configuration
 383  */
 384 #if defined(CONFIG_TSEC_ENET)
 385 #define CONFIG_HAS_ETH0
 386 #define CONFIG_HAS_ETH1
 387 #define CONFIG_HAS_ETH2
 388 #endif
 389
 390 #define CONFIG_IPADDR    192.168.1.253
 391
 392 #define CONFIG_HOSTNAME  unknown
 393 #define CONFIG_ROOTPATH  "/nfsroot"
 394 #define CONFIG_BOOTFILE  "your.uImage"
 395
 396 #define CONFIG_SERVERIP  192.168.1.1
 397 #define CONFIG_GATEWAYIP 192.168.1.1
 398 #define CONFIG_NETMASK   255.255.255.0
 399
 400 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 401
 402 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 403
 404 #define CONFIG_BAUDRATE 115200
 405
 406 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 407    "netdev=eth0\0"                                                      \
 408    "consoledev=ttyS1\0"                                                 \
 409    "ramdiskaddr=600000\0"                                               \
 410    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 411    "fdtaddr=400000\0"                                                   \
 412    "fdtfile=your.fdt.dtb\0"
 413
 414 #define CONFIG_NFSBOOTCOMMAND                                           \
 415    "setenv bootargs root=/dev/nfs rw "                                  \
 416       "nfsroot=$serverip:$rootpath "                                    \
 417       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 418       "console=$consoledev,$baudrate $othbootargs;"                     \
 419    "tftp $loadaddr $bootfile;"                                          \
 420    "tftp $fdtaddr $fdtfile;"                                            \
 421    "bootm $loadaddr - $fdtaddr"
 422
 423 #define CONFIG_RAMBOOTCOMMAND \
 424    "setenv bootargs root=/dev/ram rw "                                  \
 425       "console=$consoledev,$baudrate $othbootargs;"                     \
 426    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 427    "tftp $loadaddr $bootfile;"                                          \
 428    "bootm $loadaddr $ramdiskaddr"
 429
 430 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 431
 432 #endif  /* __CONFIG_H */