include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8560ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_SERVERIP, etc. in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /* High Level Configuration Options */
  22 #define CONFIG_CPM2             1       /* has CPM2 */
  23
  24 /*
  25  * default CCARBAR is at 0xff700000
  26  * assume U-Boot is less than 0.5MB
  27  */
  28
  29 #define CONFIG_PCI_INDIRECT_BRIDGE
  30 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  31 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  32 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  33 #define CONFIG_ENV_OVERWRITE
  34 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  35
  36 /*
  37  * sysclk for MPC85xx
  38  *
  39  * Two valid values are:
  40  *    33000000
  41  *    66000000
  42  *
  43  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  44  * is likely the desired value here, so that is now the default.
  45  * The board, however, can run at 66MHz.  In any event, this value
  46  * must match the settings of some switches.  Details can be found
  47  * in the README.mpc85xxads.
  48  */
  49
  50 #ifndef CONFIG_SYS_CLK_FREQ
  51 #define CONFIG_SYS_CLK_FREQ     33000000
  52 #endif
  53
  54 /*
  55  * These can be toggled for performance analysis, otherwise use default.
  56  */
  57 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  58 #define CONFIG_BTB                      /* toggle branch predition */
  59
  60 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  61
  62 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  63 #define CONFIG_SYS_MEMTEST_END          0x00400000
  64
  65 #define CONFIG_SYS_CCSRBAR              0xe0000000
  66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  67
  68 /* DDR Setup */
  69 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  70 #define CONFIG_DDR_SPD
  71 #undef CONFIG_FSL_DDR_INTERACTIVE
  72
  73 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  74
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  76 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  77
  78 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  79 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  80
  81 /* I2C addresses of SPD EEPROMs */
  82 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  83
  84 /* These are used when DDR doesn't use SPD.  */
  85 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
  86 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
  87 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
  88 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  89 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  90 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
  91 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
  92 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
  93
  94 /*
  95  * SDRAM on the Local Bus
  96  */
  97 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
  98 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
  99
 100 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 101 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 102
 103 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 104 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 105 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 106 #undef  CONFIG_SYS_FLASH_CHECKSUM
 107 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 108 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 109
 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 111
 112 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 113 #define CONFIG_SYS_RAMBOOT
 114 #else
 115 #undef  CONFIG_SYS_RAMBOOT
 116 #endif
 117
 118 #define CONFIG_FLASH_CFI_DRIVER
 119 #define CONFIG_SYS_FLASH_CFI
 120 #define CONFIG_SYS_FLASH_EMPTY_INFO
 121
 122 #undef CONFIG_CLOCKS_IN_MHZ
 123
 124 /*
 125  * Local Bus Definitions
 126  */
 127
 128 /*
 129  * Base Register 2 and Option Register 2 configure SDRAM.
 130  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 131  *
 132  * For BR2, need:
 133  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 134  *    port-size = 32-bits = BR2[19:20] = 11
 135  *    no parity checking = BR2[21:22] = 00
 136  *    SDRAM for MSEL = BR2[24:26] = 011
 137  *    Valid = BR[31] = 1
 138  *
 139  * 0    4    8    12   16   20   24   28
 140  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 141  *
 142  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 143  * FIXME: the top 17 bits of BR2.
 144  */
 145
 146 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 147
 148 /*
 149  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 150  *
 151  * For OR2, need:
 152  *    64MB mask for AM, OR2[0:7] = 1111 1100
 153  *                 XAM, OR2[17:18] = 11
 154  *    9 columns OR2[19-21] = 010
 155  *    13 rows   OR2[23-25] = 100
 156  *    EAD set for extra time OR[31] = 1
 157  *
 158  * 0    4    8    12   16   20   24   28
 159  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 160  */
 161
 162 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 163
 164 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 165 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 166 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 167 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 168
 169 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 170                                 | LSDMR_RFCR5           \
 171                                 | LSDMR_PRETOACT3       \
 172                                 | LSDMR_ACTTORW3        \
 173                                 | LSDMR_BL8             \
 174                                 | LSDMR_WRC2            \
 175                                 | LSDMR_CL3             \
 176                                 | LSDMR_RFEN            \
 177                                 )
 178
 179 /*
 180  * SDRAM Controller configuration sequence.
 181  */
 182 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 183 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 184 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 185 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 186 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 187
 188 /*
 189  * 32KB, 8-bit wide for ADS config reg
 190  */
 191 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 192 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 193 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 194
 195 #define CONFIG_SYS_INIT_RAM_LOCK        1
 196 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 197 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 198
 199 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 200 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 201
 202 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 203 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 204
 205 /* Serial Port */
 206 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 207 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 208 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 209
 210 #define CONFIG_SYS_BAUDRATE_TABLE  \
 211         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 212
 213 /*
 214  * I2C
 215  */
 216 #define CONFIG_SYS_I2C
 217 #define CONFIG_SYS_I2C_FSL
 218 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 219 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 220 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 221 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 222
 223 /* RapidIO MMU */
 224 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 225 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 226 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 227 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 228
 229 /*
 230  * General PCI
 231  * Memory space is mapped 1-1, but I/O space must start from 0.
 232  */
 233 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 234 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 235 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 236 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 237 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 238 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 239 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 240 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 241
 242 #if defined(CONFIG_PCI)
 243 #undef CONFIG_EEPRO100
 244 #undef CONFIG_TULIP
 245
 246 #if !defined(CONFIG_PCI_PNP)
 247     #define PCI_ENET0_IOADDR    0xe0000000
 248     #define PCI_ENET0_MEMADDR   0xe0000000
 249     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 250 #endif
 251
 252 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 253 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 254
 255 #endif  /* CONFIG_PCI */
 256
 257 #ifdef CONFIG_TSEC_ENET
 258
 259 #ifndef CONFIG_MII
 260 #define CONFIG_MII              1       /* MII PHY management */
 261 #endif
 262 #define CONFIG_TSEC1    1
 263 #define CONFIG_TSEC1_NAME       "TSEC0"
 264 #define CONFIG_TSEC2    1
 265 #define CONFIG_TSEC2_NAME       "TSEC1"
 266 #define TSEC1_PHY_ADDR          0
 267 #define TSEC2_PHY_ADDR          1
 268 #define TSEC1_PHYIDX            0
 269 #define TSEC2_PHYIDX            0
 270 #define TSEC1_FLAGS             TSEC_GIGABIT
 271 #define TSEC2_FLAGS             TSEC_GIGABIT
 272
 273 /* Options are: TSEC[0-1] */
 274 #define CONFIG_ETHPRIME         "TSEC0"
 275
 276 #endif /* CONFIG_TSEC_ENET */
 277
 278 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 279
 280 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 281 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 282
 283 #if (CONFIG_ETHER_INDEX == 2)
 284   /*
 285    * - Rx-CLK is CLK13
 286    * - Tx-CLK is CLK14
 287    * - Select bus for bd/buffers
 288    * - Full duplex
 289    */
 290   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 291   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 292   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 293   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 294   #define FETH2_RST             0x01
 295 #elif (CONFIG_ETHER_INDEX == 3)
 296   /* need more definitions here for FE3 */
 297   #define FETH3_RST             0x80
 298 #endif                                  /* CONFIG_ETHER_INDEX */
 299
 300 #ifndef CONFIG_MII
 301 #define CONFIG_MII              1       /* MII PHY management */
 302 #endif
 303
 304 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 305
 306 /*
 307  * GPIO pins used for bit-banged MII communications
 308  */
 309 #define MDIO_PORT       2               /* Port C */
 310 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 311                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 312 #define MDC_DECLARE     MDIO_DECLARE
 313
 314 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 315 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 316 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 317
 318 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 319                         else    iop->pdat &= ~0x00400000
 320
 321 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 322                         else    iop->pdat &= ~0x00200000
 323
 324 #define MIIDELAY        udelay(1)
 325
 326 #endif
 327
 328 /*
 329  * Environment
 330  */
 331 #ifndef CONFIG_SYS_RAMBOOT
 332   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 333   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 334   #define CONFIG_ENV_SIZE               0x2000
 335 #else
 336   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 337   #define CONFIG_ENV_SIZE               0x2000
 338 #endif
 339
 340 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 341 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 342
 343 /*
 344  * BOOTP options
 345  */
 346 #define CONFIG_BOOTP_BOOTFILESIZE
 347
 348 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 349
 350 /*
 351  * Miscellaneous configurable options
 352  */
 353 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 354
 355 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 356
 357 /*
 358  * For booting Linux, the board info and command line data
 359  * have to be in the first 64 MB of memory, since this is
 360  * the maximum mapped by the Linux kernel during initialization.
 361  */
 362 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 363 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 364
 365 #if defined(CONFIG_CMD_KGDB)
 366 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 367 #endif
 368
 369 /*
 370  * Environment Configuration
 371  */
 372 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 373 #define CONFIG_HAS_ETH0
 374 #define CONFIG_HAS_ETH1
 375 #define CONFIG_HAS_ETH2
 376 #define CONFIG_HAS_ETH3
 377 #endif
 378
 379 #define CONFIG_IPADDR    192.168.1.253
 380
 381 #define CONFIG_HOSTNAME         unknown
 382 #define CONFIG_ROOTPATH         "/nfsroot"
 383 #define CONFIG_BOOTFILE         "your.uImage"
 384
 385 #define CONFIG_SERVERIP  192.168.1.1
 386 #define CONFIG_GATEWAYIP 192.168.1.1
 387 #define CONFIG_NETMASK   255.255.255.0
 388
 389 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 390
 391 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 392         "netdev=eth0\0"                                                 \
 393         "consoledev=ttyCPM\0"                                           \
 394         "ramdiskaddr=1000000\0"                                         \
 395         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 396         "fdtaddr=400000\0"                                              \
 397         "fdtfile=mpc8560ads.dtb\0"
 398
 399 #define CONFIG_NFSBOOTCOMMAND                                           \
 400         "setenv bootargs root=/dev/nfs rw "                             \
 401                 "nfsroot=$serverip:$rootpath "                          \
 402                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 403                 "console=$consoledev,$baudrate $othbootargs;"           \
 404         "tftp $loadaddr $bootfile;"                                     \
 405         "tftp $fdtaddr $fdtfile;"                                       \
 406         "bootm $loadaddr - $fdtaddr"
 407
 408 #define CONFIG_RAMBOOTCOMMAND \
 409         "setenv bootargs root=/dev/ram rw "                             \
 410                 "console=$consoledev,$baudrate $othbootargs;"           \
 411         "tftp $ramdiskaddr $ramdiskfile;"                               \
 412         "tftp $loadaddr $bootfile;"                                     \
 413         "tftp $fdtaddr $fdtfile;"                                       \
 414         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 415
 416 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 417
 418 #endif  /* __CONFIG_H */