include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8560ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_SERVERIP, etc. in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /* High Level Configuration Options */
  22 #define CONFIG_BOOKE            1       /* BOOKE */
  23 #define CONFIG_E500             1       /* BOOKE e500 family */
  24 #define CONFIG_CPM2             1       /* has CPM2 */
  25 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  26 #define CONFIG_MPC8560          1
  27
  28 /*
  29  * default CCARBAR is at 0xff700000
  30  * assume U-Boot is less than 0.5MB
  31  */
  32 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  33
  34 #define CONFIG_PCI_INDIRECT_BRIDGE
  35 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  36 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  37 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  38 #define CONFIG_ENV_OVERWRITE
  39 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  40 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  41
  42 /*
  43  * sysclk for MPC85xx
  44  *
  45  * Two valid values are:
  46  *    33000000
  47  *    66000000
  48  *
  49  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  50  * is likely the desired value here, so that is now the default.
  51  * The board, however, can run at 66MHz.  In any event, this value
  52  * must match the settings of some switches.  Details can be found
  53  * in the README.mpc85xxads.
  54  */
  55
  56 #ifndef CONFIG_SYS_CLK_FREQ
  57 #define CONFIG_SYS_CLK_FREQ     33000000
  58 #endif
  59
  60 /*
  61  * These can be toggled for performance analysis, otherwise use default.
  62  */
  63 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  64 #define CONFIG_BTB                      /* toggle branch predition */
  65
  66 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  67
  68 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  69 #define CONFIG_SYS_MEMTEST_END          0x00400000
  70
  71 #define CONFIG_SYS_CCSRBAR              0xe0000000
  72 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  73
  74 /* DDR Setup */
  75 #define CONFIG_SYS_FSL_DDR1
  76 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  77 #define CONFIG_DDR_SPD
  78 #undef CONFIG_FSL_DDR_INTERACTIVE
  79
  80 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  81
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  83 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  84
  85 #define CONFIG_NUM_DDR_CONTROLLERS      1
  86 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  87 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  88
  89 /* I2C addresses of SPD EEPROMs */
  90 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  91
  92 /* These are used when DDR doesn't use SPD.  */
  93 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
  94 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
  95 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
  96 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  97 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  98 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
  99 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 100 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 101
 102 /*
 103  * SDRAM on the Local Bus
 104  */
 105 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 106 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 107
 108 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 109 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 110
 111 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 112 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 113 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 114 #undef  CONFIG_SYS_FLASH_CHECKSUM
 115 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 116 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 117
 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 119
 120 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 121 #define CONFIG_SYS_RAMBOOT
 122 #else
 123 #undef  CONFIG_SYS_RAMBOOT
 124 #endif
 125
 126 #define CONFIG_FLASH_CFI_DRIVER
 127 #define CONFIG_SYS_FLASH_CFI
 128 #define CONFIG_SYS_FLASH_EMPTY_INFO
 129
 130 #undef CONFIG_CLOCKS_IN_MHZ
 131
 132 /*
 133  * Local Bus Definitions
 134  */
 135
 136 /*
 137  * Base Register 2 and Option Register 2 configure SDRAM.
 138  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 139  *
 140  * For BR2, need:
 141  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 142  *    port-size = 32-bits = BR2[19:20] = 11
 143  *    no parity checking = BR2[21:22] = 00
 144  *    SDRAM for MSEL = BR2[24:26] = 011
 145  *    Valid = BR[31] = 1
 146  *
 147  * 0    4    8    12   16   20   24   28
 148  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 149  *
 150  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 151  * FIXME: the top 17 bits of BR2.
 152  */
 153
 154 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 155
 156 /*
 157  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 158  *
 159  * For OR2, need:
 160  *    64MB mask for AM, OR2[0:7] = 1111 1100
 161  *                 XAM, OR2[17:18] = 11
 162  *    9 columns OR2[19-21] = 010
 163  *    13 rows   OR2[23-25] = 100
 164  *    EAD set for extra time OR[31] = 1
 165  *
 166  * 0    4    8    12   16   20   24   28
 167  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 168  */
 169
 170 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 171
 172 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 173 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 174 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 175 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 176
 177 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 178                                 | LSDMR_RFCR5           \
 179                                 | LSDMR_PRETOACT3       \
 180                                 | LSDMR_ACTTORW3        \
 181                                 | LSDMR_BL8             \
 182                                 | LSDMR_WRC2            \
 183                                 | LSDMR_CL3             \
 184                                 | LSDMR_RFEN            \
 185                                 )
 186
 187 /*
 188  * SDRAM Controller configuration sequence.
 189  */
 190 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 191 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 192 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 193 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 194 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 195
 196 /*
 197  * 32KB, 8-bit wide for ADS config reg
 198  */
 199 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 200 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 201 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 202
 203 #define CONFIG_SYS_INIT_RAM_LOCK        1
 204 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 205 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 206
 207 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 208 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 209
 210 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 211 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 212
 213 /* Serial Port */
 214 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 215 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 216 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 217
 218 #define CONFIG_BAUDRATE         115200
 219
 220 #define CONFIG_SYS_BAUDRATE_TABLE  \
 221         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 222
 223 /*
 224  * I2C
 225  */
 226 #define CONFIG_SYS_I2C
 227 #define CONFIG_SYS_I2C_FSL
 228 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 229 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 230 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 231 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 232
 233 /* RapidIO MMU */
 234 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 235 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 236 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 237 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 238
 239 /*
 240  * General PCI
 241  * Memory space is mapped 1-1, but I/O space must start from 0.
 242  */
 243 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 244 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 245 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 246 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 247 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 248 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 249 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 250 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 251
 252 #if defined(CONFIG_PCI)
 253
 254 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 255
 256 #undef CONFIG_EEPRO100
 257 #undef CONFIG_TULIP
 258
 259 #if !defined(CONFIG_PCI_PNP)
 260     #define PCI_ENET0_IOADDR    0xe0000000
 261     #define PCI_ENET0_MEMADDR   0xe0000000
 262     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 263 #endif
 264
 265 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 266 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 267
 268 #endif  /* CONFIG_PCI */
 269
 270 #ifdef CONFIG_TSEC_ENET
 271
 272 #ifndef CONFIG_MII
 273 #define CONFIG_MII              1       /* MII PHY management */
 274 #endif
 275 #define CONFIG_TSEC1    1
 276 #define CONFIG_TSEC1_NAME       "TSEC0"
 277 #define CONFIG_TSEC2    1
 278 #define CONFIG_TSEC2_NAME       "TSEC1"
 279 #define TSEC1_PHY_ADDR          0
 280 #define TSEC2_PHY_ADDR          1
 281 #define TSEC1_PHYIDX            0
 282 #define TSEC2_PHYIDX            0
 283 #define TSEC1_FLAGS             TSEC_GIGABIT
 284 #define TSEC2_FLAGS             TSEC_GIGABIT
 285
 286 /* Options are: TSEC[0-1] */
 287 #define CONFIG_ETHPRIME         "TSEC0"
 288
 289 #endif /* CONFIG_TSEC_ENET */
 290
 291 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 292
 293 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 294 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 295
 296 #if (CONFIG_ETHER_INDEX == 2)
 297   /*
 298    * - Rx-CLK is CLK13
 299    * - Tx-CLK is CLK14
 300    * - Select bus for bd/buffers
 301    * - Full duplex
 302    */
 303   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 304   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 305   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 306   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 307   #define FETH2_RST             0x01
 308 #elif (CONFIG_ETHER_INDEX == 3)
 309   /* need more definitions here for FE3 */
 310   #define FETH3_RST             0x80
 311 #endif                                  /* CONFIG_ETHER_INDEX */
 312
 313 #ifndef CONFIG_MII
 314 #define CONFIG_MII              1       /* MII PHY management */
 315 #endif
 316
 317 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 318
 319 /*
 320  * GPIO pins used for bit-banged MII communications
 321  */
 322 #define MDIO_PORT       2               /* Port C */
 323 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 324                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 325 #define MDC_DECLARE     MDIO_DECLARE
 326
 327 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 328 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 329 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 330
 331 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 332                         else    iop->pdat &= ~0x00400000
 333
 334 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 335                         else    iop->pdat &= ~0x00200000
 336
 337 #define MIIDELAY        udelay(1)
 338
 339 #endif
 340
 341 /*
 342  * Environment
 343  */
 344 #ifndef CONFIG_SYS_RAMBOOT
 345   #define CONFIG_ENV_IS_IN_FLASH        1
 346   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 347   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 348   #define CONFIG_ENV_SIZE               0x2000
 349 #else
 350   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 351   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 352   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 353   #define CONFIG_ENV_SIZE               0x2000
 354 #endif
 355
 356 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 357 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 358
 359 /*
 360  * BOOTP options
 361  */
 362 #define CONFIG_BOOTP_BOOTFILESIZE
 363 #define CONFIG_BOOTP_BOOTPATH
 364 #define CONFIG_BOOTP_GATEWAY
 365 #define CONFIG_BOOTP_HOSTNAME
 366
 367 /*
 368  * Command line configuration.
 369  */
 370 #define CONFIG_CMD_IRQ
 371 #define CONFIG_CMD_REGINFO
 372
 373 #if defined(CONFIG_PCI)
 374     #define CONFIG_CMD_PCI
 375 #endif
 376
 377 #if defined(CONFIG_ETHER_ON_FCC)
 378 #endif
 379
 380 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 381
 382 /*
 383  * Miscellaneous configurable options
 384  */
 385 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 386 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 387 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 388 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 389
 390 #if defined(CONFIG_CMD_KGDB)
 391     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 392 #else
 393     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 394 #endif
 395
 396 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 397 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 398 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 399
 400 /*
 401  * For booting Linux, the board info and command line data
 402  * have to be in the first 64 MB of memory, since this is
 403  * the maximum mapped by the Linux kernel during initialization.
 404  */
 405 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 406 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 407
 408 #if defined(CONFIG_CMD_KGDB)
 409 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 410 #endif
 411
 412 /*
 413  * Environment Configuration
 414  */
 415 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 416 #define CONFIG_HAS_ETH0
 417 #define CONFIG_HAS_ETH1
 418 #define CONFIG_HAS_ETH2
 419 #define CONFIG_HAS_ETH3
 420 #endif
 421
 422 #define CONFIG_IPADDR    192.168.1.253
 423
 424 #define CONFIG_HOSTNAME         unknown
 425 #define CONFIG_ROOTPATH         "/nfsroot"
 426 #define CONFIG_BOOTFILE         "your.uImage"
 427
 428 #define CONFIG_SERVERIP  192.168.1.1
 429 #define CONFIG_GATEWAYIP 192.168.1.1
 430 #define CONFIG_NETMASK   255.255.255.0
 431
 432 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 433
 434 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 435
 436 #define CONFIG_BAUDRATE 115200
 437
 438 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 439         "netdev=eth0\0"                                                 \
 440         "consoledev=ttyCPM\0"                                           \
 441         "ramdiskaddr=1000000\0"                                         \
 442         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 443         "fdtaddr=400000\0"                                              \
 444         "fdtfile=mpc8560ads.dtb\0"
 445
 446 #define CONFIG_NFSBOOTCOMMAND                                           \
 447         "setenv bootargs root=/dev/nfs rw "                             \
 448                 "nfsroot=$serverip:$rootpath "                          \
 449                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 450                 "console=$consoledev,$baudrate $othbootargs;"           \
 451         "tftp $loadaddr $bootfile;"                                     \
 452         "tftp $fdtaddr $fdtfile;"                                       \
 453         "bootm $loadaddr - $fdtaddr"
 454
 455 #define CONFIG_RAMBOOTCOMMAND \
 456         "setenv bootargs root=/dev/ram rw "                             \
 457                 "console=$consoledev,$baudrate $othbootargs;"           \
 458         "tftp $ramdiskaddr $ramdiskfile;"                               \
 459         "tftp $loadaddr $bootfile;"                                     \
 460         "tftp $fdtaddr $fdtfile;"                                       \
 461         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 462
 463 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 464
 465 #endif  /* __CONFIG_H */