include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8560ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_SERVERIP, etc. in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 #define CONFIG_DISPLAY_BOARDINFO
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_BOOKE            1       /* BOOKE */
  25 #define CONFIG_E500             1       /* BOOKE e500 family */
  26 #define CONFIG_CPM2             1       /* has CPM2 */
  27 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  28 #define CONFIG_MPC8560          1
  29
  30 /*
  31  * default CCARBAR is at 0xff700000
  32  * assume U-Boot is less than 0.5MB
  33  */
  34 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  35
  36 #define CONFIG_PCI
  37 #define CONFIG_PCI_INDIRECT_BRIDGE
  38 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  39 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  40 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  41 #define CONFIG_ENV_OVERWRITE
  42 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  43 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  44
  45 /*
  46  * sysclk for MPC85xx
  47  *
  48  * Two valid values are:
  49  *    33000000
  50  *    66000000
  51  *
  52  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  53  * is likely the desired value here, so that is now the default.
  54  * The board, however, can run at 66MHz.  In any event, this value
  55  * must match the settings of some switches.  Details can be found
  56  * in the README.mpc85xxads.
  57  */
  58
  59 #ifndef CONFIG_SYS_CLK_FREQ
  60 #define CONFIG_SYS_CLK_FREQ     33000000
  61 #endif
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  67 #define CONFIG_BTB                      /* toggle branch predition */
  68
  69 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  70
  71 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  72 #define CONFIG_SYS_MEMTEST_END          0x00400000
  73
  74 #define CONFIG_SYS_CCSRBAR              0xe0000000
  75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  76
  77 /* DDR Setup */
  78 #define CONFIG_SYS_FSL_DDR1
  79 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  80 #define CONFIG_DDR_SPD
  81 #undef CONFIG_FSL_DDR_INTERACTIVE
  82
  83 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  84
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  86 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  87
  88 #define CONFIG_NUM_DDR_CONTROLLERS      1
  89 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  90 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  91
  92 /* I2C addresses of SPD EEPROMs */
  93 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  94
  95 /* These are used when DDR doesn't use SPD.  */
  96 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
  97 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
  98 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
  99 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 100 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 101 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 102 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 103 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 104
 105 /*
 106  * SDRAM on the Local Bus
 107  */
 108 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 109 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 110
 111 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 112 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 113
 114 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 117 #undef  CONFIG_SYS_FLASH_CHECKSUM
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 120
 121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 122
 123 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 124 #define CONFIG_SYS_RAMBOOT
 125 #else
 126 #undef  CONFIG_SYS_RAMBOOT
 127 #endif
 128
 129 #define CONFIG_FLASH_CFI_DRIVER
 130 #define CONFIG_SYS_FLASH_CFI
 131 #define CONFIG_SYS_FLASH_EMPTY_INFO
 132
 133 #undef CONFIG_CLOCKS_IN_MHZ
 134
 135 /*
 136  * Local Bus Definitions
 137  */
 138
 139 /*
 140  * Base Register 2 and Option Register 2 configure SDRAM.
 141  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 142  *
 143  * For BR2, need:
 144  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 145  *    port-size = 32-bits = BR2[19:20] = 11
 146  *    no parity checking = BR2[21:22] = 00
 147  *    SDRAM for MSEL = BR2[24:26] = 011
 148  *    Valid = BR[31] = 1
 149  *
 150  * 0    4    8    12   16   20   24   28
 151  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 152  *
 153  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 154  * FIXME: the top 17 bits of BR2.
 155  */
 156
 157 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 158
 159 /*
 160  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 161  *
 162  * For OR2, need:
 163  *    64MB mask for AM, OR2[0:7] = 1111 1100
 164  *                 XAM, OR2[17:18] = 11
 165  *    9 columns OR2[19-21] = 010
 166  *    13 rows   OR2[23-25] = 100
 167  *    EAD set for extra time OR[31] = 1
 168  *
 169  * 0    4    8    12   16   20   24   28
 170  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 171  */
 172
 173 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 174
 175 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 176 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 177 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 178 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 179
 180 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 181                                 | LSDMR_RFCR5           \
 182                                 | LSDMR_PRETOACT3       \
 183                                 | LSDMR_ACTTORW3        \
 184                                 | LSDMR_BL8             \
 185                                 | LSDMR_WRC2            \
 186                                 | LSDMR_CL3             \
 187                                 | LSDMR_RFEN            \
 188                                 )
 189
 190 /*
 191  * SDRAM Controller configuration sequence.
 192  */
 193 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 194 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 195 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 196 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 197 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 198
 199 /*
 200  * 32KB, 8-bit wide for ADS config reg
 201  */
 202 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 203 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 204 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 205
 206 #define CONFIG_SYS_INIT_RAM_LOCK        1
 207 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 208 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 209
 210 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 211 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 212
 213 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 214 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 215
 216 /* Serial Port */
 217 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 218 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 219 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 220
 221 #define CONFIG_BAUDRATE         115200
 222
 223 #define CONFIG_SYS_BAUDRATE_TABLE  \
 224         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 225
 226 /*
 227  * I2C
 228  */
 229 #define CONFIG_SYS_I2C
 230 #define CONFIG_SYS_I2C_FSL
 231 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 232 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 233 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 234 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 235
 236 /* RapidIO MMU */
 237 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 238 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 239 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 240 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 241
 242 /*
 243  * General PCI
 244  * Memory space is mapped 1-1, but I/O space must start from 0.
 245  */
 246 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 247 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 248 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 249 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 250 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 251 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 252 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 253 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 254
 255 #if defined(CONFIG_PCI)
 256
 257 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 258
 259 #undef CONFIG_EEPRO100
 260 #undef CONFIG_TULIP
 261
 262 #if !defined(CONFIG_PCI_PNP)
 263     #define PCI_ENET0_IOADDR    0xe0000000
 264     #define PCI_ENET0_MEMADDR   0xe0000000
 265     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 266 #endif
 267
 268 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 269 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 270
 271 #endif  /* CONFIG_PCI */
 272
 273 #ifdef CONFIG_TSEC_ENET
 274
 275 #ifndef CONFIG_MII
 276 #define CONFIG_MII              1       /* MII PHY management */
 277 #endif
 278 #define CONFIG_TSEC1    1
 279 #define CONFIG_TSEC1_NAME       "TSEC0"
 280 #define CONFIG_TSEC2    1
 281 #define CONFIG_TSEC2_NAME       "TSEC1"
 282 #define TSEC1_PHY_ADDR          0
 283 #define TSEC2_PHY_ADDR          1
 284 #define TSEC1_PHYIDX            0
 285 #define TSEC2_PHYIDX            0
 286 #define TSEC1_FLAGS             TSEC_GIGABIT
 287 #define TSEC2_FLAGS             TSEC_GIGABIT
 288
 289 /* Options are: TSEC[0-1] */
 290 #define CONFIG_ETHPRIME         "TSEC0"
 291
 292 #endif /* CONFIG_TSEC_ENET */
 293
 294 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 295
 296 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 297 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 298
 299 #if (CONFIG_ETHER_INDEX == 2)
 300   /*
 301    * - Rx-CLK is CLK13
 302    * - Tx-CLK is CLK14
 303    * - Select bus for bd/buffers
 304    * - Full duplex
 305    */
 306   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 307   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 308   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 309   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 310   #define FETH2_RST             0x01
 311 #elif (CONFIG_ETHER_INDEX == 3)
 312   /* need more definitions here for FE3 */
 313   #define FETH3_RST             0x80
 314 #endif                                  /* CONFIG_ETHER_INDEX */
 315
 316 #ifndef CONFIG_MII
 317 #define CONFIG_MII              1       /* MII PHY management */
 318 #endif
 319
 320 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 321
 322 /*
 323  * GPIO pins used for bit-banged MII communications
 324  */
 325 #define MDIO_PORT       2               /* Port C */
 326 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 327                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 328 #define MDC_DECLARE     MDIO_DECLARE
 329
 330 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 331 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 332 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 333
 334 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 335                         else    iop->pdat &= ~0x00400000
 336
 337 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 338                         else    iop->pdat &= ~0x00200000
 339
 340 #define MIIDELAY        udelay(1)
 341
 342 #endif
 343
 344 /*
 345  * Environment
 346  */
 347 #ifndef CONFIG_SYS_RAMBOOT
 348   #define CONFIG_ENV_IS_IN_FLASH        1
 349   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 350   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 351   #define CONFIG_ENV_SIZE               0x2000
 352 #else
 353   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 354   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 355   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 356   #define CONFIG_ENV_SIZE               0x2000
 357 #endif
 358
 359 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 360 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 361
 362 /*
 363  * BOOTP options
 364  */
 365 #define CONFIG_BOOTP_BOOTFILESIZE
 366 #define CONFIG_BOOTP_BOOTPATH
 367 #define CONFIG_BOOTP_GATEWAY
 368 #define CONFIG_BOOTP_HOSTNAME
 369
 370 /*
 371  * Command line configuration.
 372  */
 373 #define CONFIG_CMD_IRQ
 374 #define CONFIG_CMD_REGINFO
 375
 376 #if defined(CONFIG_PCI)
 377     #define CONFIG_CMD_PCI
 378 #endif
 379
 380 #if defined(CONFIG_ETHER_ON_FCC)
 381 #endif
 382
 383 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 384
 385 /*
 386  * Miscellaneous configurable options
 387  */
 388 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 389 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 390 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 391 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 392
 393 #if defined(CONFIG_CMD_KGDB)
 394     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 395 #else
 396     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 397 #endif
 398
 399 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 400 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 401 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 402
 403 /*
 404  * For booting Linux, the board info and command line data
 405  * have to be in the first 64 MB of memory, since this is
 406  * the maximum mapped by the Linux kernel during initialization.
 407  */
 408 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 409 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 410
 411 #if defined(CONFIG_CMD_KGDB)
 412 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 413 #endif
 414
 415 /*
 416  * Environment Configuration
 417  */
 418 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 419 #define CONFIG_HAS_ETH0
 420 #define CONFIG_HAS_ETH1
 421 #define CONFIG_HAS_ETH2
 422 #define CONFIG_HAS_ETH3
 423 #endif
 424
 425 #define CONFIG_IPADDR    192.168.1.253
 426
 427 #define CONFIG_HOSTNAME         unknown
 428 #define CONFIG_ROOTPATH         "/nfsroot"
 429 #define CONFIG_BOOTFILE         "your.uImage"
 430
 431 #define CONFIG_SERVERIP  192.168.1.1
 432 #define CONFIG_GATEWAYIP 192.168.1.1
 433 #define CONFIG_NETMASK   255.255.255.0
 434
 435 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 436
 437 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 438 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 439
 440 #define CONFIG_BAUDRATE 115200
 441
 442 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 443         "netdev=eth0\0"                                                 \
 444         "consoledev=ttyCPM\0"                                           \
 445         "ramdiskaddr=1000000\0"                                         \
 446         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 447         "fdtaddr=400000\0"                                              \
 448         "fdtfile=mpc8560ads.dtb\0"
 449
 450 #define CONFIG_NFSBOOTCOMMAND                                           \
 451         "setenv bootargs root=/dev/nfs rw "                             \
 452                 "nfsroot=$serverip:$rootpath "                          \
 453                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 454                 "console=$consoledev,$baudrate $othbootargs;"           \
 455         "tftp $loadaddr $bootfile;"                                     \
 456         "tftp $fdtaddr $fdtfile;"                                       \
 457         "bootm $loadaddr - $fdtaddr"
 458
 459 #define CONFIG_RAMBOOTCOMMAND \
 460         "setenv bootargs root=/dev/ram rw "                             \
 461                 "console=$consoledev,$baudrate $othbootargs;"           \
 462         "tftp $ramdiskaddr $ramdiskfile;"                               \
 463         "tftp $loadaddr $bootfile;"                                     \
 464         "tftp $fdtaddr $fdtfile;"                                       \
 465         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 466
 467 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 468
 469 #endif  /* __CONFIG_H */