include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * mpc8560ads board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_CPM2             1       /* has CPM2 */
  42 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  43 #define CONFIG_MPC8560          1
  44
  45 #define CONFIG_PCI
  46 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  48 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  51
  52 /*
  53  * sysclk for MPC85xx
  54  *
  55  * Two valid values are:
  56  *    33000000
  57  *    66000000
  58  *
  59  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  60  * is likely the desired value here, so that is now the default.
  61  * The board, however, can run at 66MHz.  In any event, this value
  62  * must match the settings of some switches.  Details can be found
  63  * in the README.mpc85xxads.
  64  */
  65
  66 #ifndef CONFIG_SYS_CLK_FREQ
  67 #define CONFIG_SYS_CLK_FREQ     33000000
  68 #endif
  69
  70
  71 /*
  72  * These can be toggled for performance analysis, otherwise use default.
  73  */
  74 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  75 #define CONFIG_BTB                      /* toggle branch predition */
  76
  77 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  78
  79 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  80 #define CONFIG_SYS_MEMTEST_END          0x00400000
  81
  82
  83 /*
  84  * Base addresses -- Note these are effective addresses where the
  85  * actual resources get mapped (not physical addresses)
  86  */
  87 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  88 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  89 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  90 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  91
  92 /* DDR Setup */
  93 #define CONFIG_FSL_DDR1
  94 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  95 #define CONFIG_DDR_SPD
  96 #undef CONFIG_FSL_DDR_INTERACTIVE
  97
  98 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  99
 100 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 101 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 102
 103 #define CONFIG_NUM_DDR_CONTROLLERS      1
 104 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 105 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 106
 107 /* I2C addresses of SPD EEPROMs */
 108 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 109
 110 /* These are used when DDR doesn't use SPD.  */
 111 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
 112 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
 113 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
 114 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 115 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 116 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 117 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 118 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 119
 120 /*
 121  * SDRAM on the Local Bus
 122  */
 123 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 124 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 125
 126 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 127 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 128
 129 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 132 #undef  CONFIG_SYS_FLASH_CHECKSUM
 133 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 134 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 135
 136 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 137
 138 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 139 #define CONFIG_SYS_RAMBOOT
 140 #else
 141 #undef  CONFIG_SYS_RAMBOOT
 142 #endif
 143
 144 #define CONFIG_FLASH_CFI_DRIVER
 145 #define CONFIG_SYS_FLASH_CFI
 146 #define CONFIG_SYS_FLASH_EMPTY_INFO
 147
 148 #undef CONFIG_CLOCKS_IN_MHZ
 149
 150
 151 /*
 152  * Local Bus Definitions
 153  */
 154
 155 /*
 156  * Base Register 2 and Option Register 2 configure SDRAM.
 157  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 158  *
 159  * For BR2, need:
 160  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 161  *    port-size = 32-bits = BR2[19:20] = 11
 162  *    no parity checking = BR2[21:22] = 00
 163  *    SDRAM for MSEL = BR2[24:26] = 011
 164  *    Valid = BR[31] = 1
 165  *
 166  * 0    4    8    12   16   20   24   28
 167  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 168  *
 169  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 170  * FIXME: the top 17 bits of BR2.
 171  */
 172
 173 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 174
 175 /*
 176  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 177  *
 178  * For OR2, need:
 179  *    64MB mask for AM, OR2[0:7] = 1111 1100
 180  *                 XAM, OR2[17:18] = 11
 181  *    9 columns OR2[19-21] = 010
 182  *    13 rows   OR2[23-25] = 100
 183  *    EAD set for extra time OR[31] = 1
 184  *
 185  * 0    4    8    12   16   20   24   28
 186  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 187  */
 188
 189 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 190
 191 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 192 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 193 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 194 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 195
 196 /*
 197  * LSDMR masks
 198  */
 199 #define CONFIG_SYS_LBC_LSDMR_RFEN       (1 << (31 -  1))
 200 #define CONFIG_SYS_LBC_LSDMR_BSMA1516   (3 << (31 - 10))
 201 #define CONFIG_SYS_LBC_LSDMR_BSMA1617   (4 << (31 - 10))
 202 #define CONFIG_SYS_LBC_LSDMR_RFCR5      (3 << (31 - 16))
 203 #define CONFIG_SYS_LBC_LSDMR_RFCR16     (7 << (31 - 16))
 204 #define CONFIG_SYS_LBC_LSDMR_PRETOACT3  (3 << (31 - 19))
 205 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7  (7 << (31 - 19))
 206 #define CONFIG_SYS_LBC_LSDMR_ACTTORW3   (3 << (31 - 22))
 207 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7   (7 << (31 - 22))
 208 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6   (6 << (31 - 22))
 209 #define CONFIG_SYS_LBC_LSDMR_BL8        (1 << (31 - 23))
 210 #define CONFIG_SYS_LBC_LSDMR_WRC2       (2 << (31 - 27))
 211 #define CONFIG_SYS_LBC_LSDMR_WRC4       (0 << (31 - 27))
 212 #define CONFIG_SYS_LBC_LSDMR_BUFCMD     (1 << (31 - 29))
 213 #define CONFIG_SYS_LBC_LSDMR_CL3        (3 << (31 - 31))
 214
 215 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL  (0 << (31 - 4))
 216 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH  (1 << (31 - 4))
 217 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH  (2 << (31 - 4))
 218 #define CONFIG_SYS_LBC_LSDMR_OP_MRW     (3 << (31 - 4))
 219 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH   (4 << (31 - 4))
 220 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL  (5 << (31 - 4))
 221 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK  (6 << (31 - 4))
 222 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV   (7 << (31 - 4))
 223
 224 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( CONFIG_SYS_LBC_LSDMR_BSMA1516 \
 225                                 | CONFIG_SYS_LBC_LSDMR_RFCR5            \
 226                                 | CONFIG_SYS_LBC_LSDMR_PRETOACT3        \
 227                                 | CONFIG_SYS_LBC_LSDMR_ACTTORW3 \
 228                                 | CONFIG_SYS_LBC_LSDMR_BL8              \
 229                                 | CONFIG_SYS_LBC_LSDMR_WRC2             \
 230                                 | CONFIG_SYS_LBC_LSDMR_CL3              \
 231                                 | CONFIG_SYS_LBC_LSDMR_RFEN             \
 232                                 )
 233
 234 /*
 235  * SDRAM Controller configuration sequence.
 236  */
 237 #define CONFIG_SYS_LBC_LSDMR_1          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 238                                 | CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
 239 #define CONFIG_SYS_LBC_LSDMR_2          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 240                                 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
 241 #define CONFIG_SYS_LBC_LSDMR_3          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 242                                 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
 243 #define CONFIG_SYS_LBC_LSDMR_4          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 244                                 | CONFIG_SYS_LBC_LSDMR_OP_MRW)
 245 #define CONFIG_SYS_LBC_LSDMR_5          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 246                                 | CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 247
 248
 249 /*
 250  * 32KB, 8-bit wide for ADS config reg
 251  */
 252 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 253 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 254 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 255
 256 #define CONFIG_SYS_INIT_RAM_LOCK        1
 257 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 258 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 259
 260 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 261 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 262 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 263
 264 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 265 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 266
 267 /* Serial Port */
 268 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 269 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 270 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 271
 272 #define CONFIG_BAUDRATE         115200
 273
 274 #define CONFIG_SYS_BAUDRATE_TABLE  \
 275         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 276
 277 /* Use the HUSH parser */
 278 #define CONFIG_SYS_HUSH_PARSER
 279 #ifdef  CONFIG_SYS_HUSH_PARSER
 280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 281 #endif
 282
 283 /* pass open firmware flat tree */
 284 #define CONFIG_OF_LIBFDT                1
 285 #define CONFIG_OF_BOARD_SETUP           1
 286 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 287
 288 #define CONFIG_SYS_64BIT_VSPRINTF       1
 289 #define CONFIG_SYS_64BIT_STRTOUL        1
 290
 291 /*
 292  * I2C
 293  */
 294 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 295 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 296 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 297 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 298 #define CONFIG_SYS_I2C_SLAVE            0x7F
 299 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 300 #define CONFIG_SYS_I2C_OFFSET           0x3000
 301
 302 /* RapidIO MMU */
 303 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 304 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 305 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 306 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 307
 308 /*
 309  * General PCI
 310  * Memory space is mapped 1-1, but I/O space must start from 0.
 311  */
 312 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 313 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 314 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 315 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 316 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 317 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 318 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 319
 320 #if defined(CONFIG_PCI)
 321
 322 #define CONFIG_NET_MULTI
 323 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 324
 325 #undef CONFIG_EEPRO100
 326 #undef CONFIG_TULIP
 327
 328 #if !defined(CONFIG_PCI_PNP)
 329     #define PCI_ENET0_IOADDR    0xe0000000
 330     #define PCI_ENET0_MEMADDR   0xe0000000
 331     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 332 #endif
 333
 334 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 335 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 336
 337 #endif  /* CONFIG_PCI */
 338
 339
 340 #ifdef CONFIG_TSEC_ENET
 341
 342 #ifndef CONFIG_NET_MULTI
 343 #define CONFIG_NET_MULTI        1
 344 #endif
 345
 346 #ifndef CONFIG_MII
 347 #define CONFIG_MII              1       /* MII PHY management */
 348 #endif
 349 #define CONFIG_TSEC1    1
 350 #define CONFIG_TSEC1_NAME       "TSEC0"
 351 #define CONFIG_TSEC2    1
 352 #define CONFIG_TSEC2_NAME       "TSEC1"
 353 #define TSEC1_PHY_ADDR          0
 354 #define TSEC2_PHY_ADDR          1
 355 #define TSEC1_PHYIDX            0
 356 #define TSEC2_PHYIDX            0
 357 #define TSEC1_FLAGS             TSEC_GIGABIT
 358 #define TSEC2_FLAGS             TSEC_GIGABIT
 359
 360 /* Options are: TSEC[0-1] */
 361 #define CONFIG_ETHPRIME         "TSEC0"
 362
 363 #endif /* CONFIG_TSEC_ENET */
 364
 365 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 366
 367 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 368 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 369
 370 #if (CONFIG_ETHER_INDEX == 2)
 371   /*
 372    * - Rx-CLK is CLK13
 373    * - Tx-CLK is CLK14
 374    * - Select bus for bd/buffers
 375    * - Full duplex
 376    */
 377   #define CONFIG_SYS_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 378   #define CONFIG_SYS_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 379   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 380   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 381   #define FETH2_RST             0x01
 382 #elif (CONFIG_ETHER_INDEX == 3)
 383   /* need more definitions here for FE3 */
 384   #define FETH3_RST             0x80
 385 #endif                                  /* CONFIG_ETHER_INDEX */
 386
 387 #ifndef CONFIG_MII
 388 #define CONFIG_MII              1       /* MII PHY management */
 389 #endif
 390
 391 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 392
 393 /*
 394  * GPIO pins used for bit-banged MII communications
 395  */
 396 #define MDIO_PORT       2               /* Port C */
 397 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 398 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 399 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 400
 401 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 402                         else    iop->pdat &= ~0x00400000
 403
 404 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 405                         else    iop->pdat &= ~0x00200000
 406
 407 #define MIIDELAY        udelay(1)
 408
 409 #endif
 410
 411
 412 /*
 413  * Environment
 414  */
 415 #ifndef CONFIG_SYS_RAMBOOT
 416   #define CONFIG_ENV_IS_IN_FLASH        1
 417   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 418   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 419   #define CONFIG_ENV_SIZE               0x2000
 420 #else
 421   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 422   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 423   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 424   #define CONFIG_ENV_SIZE               0x2000
 425 #endif
 426
 427 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 428 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 429
 430 /*
 431  * BOOTP options
 432  */
 433 #define CONFIG_BOOTP_BOOTFILESIZE
 434 #define CONFIG_BOOTP_BOOTPATH
 435 #define CONFIG_BOOTP_GATEWAY
 436 #define CONFIG_BOOTP_HOSTNAME
 437
 438
 439 /*
 440  * Command line configuration.
 441  */
 442 #include <config_cmd_default.h>
 443
 444 #define CONFIG_CMD_PING
 445 #define CONFIG_CMD_I2C
 446 #define CONFIG_CMD_ELF
 447 #define CONFIG_CMD_IRQ
 448 #define CONFIG_CMD_SETEXPR
 449
 450 #if defined(CONFIG_PCI)
 451     #define CONFIG_CMD_PCI
 452 #endif
 453
 454 #if defined(CONFIG_ETHER_ON_FCC)
 455     #define CONFIG_CMD_MII
 456 #endif
 457
 458 #if defined(CONFIG_SYS_RAMBOOT)
 459     #undef CONFIG_CMD_ENV
 460     #undef CONFIG_CMD_LOADS
 461 #endif
 462
 463
 464 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 465
 466 /*
 467  * Miscellaneous configurable options
 468  */
 469 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 470 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 471 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 472 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 473
 474 #if defined(CONFIG_CMD_KGDB)
 475     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 476 #else
 477     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 478 #endif
 479
 480 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 481 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 482 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 483 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 484
 485 /*
 486  * For booting Linux, the board info and command line data
 487  * have to be in the first 8 MB of memory, since this is
 488  * the maximum mapped by the Linux kernel during initialization.
 489  */
 490 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 491
 492 /*
 493  * Internal Definitions
 494  *
 495  * Boot Flags
 496  */
 497 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 498 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 499
 500 #if defined(CONFIG_CMD_KGDB)
 501 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 502 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 503 #endif
 504
 505
 506 /*
 507  * Environment Configuration
 508  */
 509
 510 /* The mac addresses for all ethernet interface */
 511 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 512 #define CONFIG_HAS_ETH0
 513 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 514 #define CONFIG_HAS_ETH1
 515 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 516 #define CONFIG_HAS_ETH2
 517 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 518 #define CONFIG_HAS_ETH3
 519 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 520 #endif
 521
 522 #define CONFIG_IPADDR    192.168.1.253
 523
 524 #define CONFIG_HOSTNAME         unknown
 525 #define CONFIG_ROOTPATH         /nfsroot
 526 #define CONFIG_BOOTFILE         your.uImage
 527
 528 #define CONFIG_SERVERIP  192.168.1.1
 529 #define CONFIG_GATEWAYIP 192.168.1.1
 530 #define CONFIG_NETMASK   255.255.255.0
 531
 532 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 533
 534 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 535 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 536
 537 #define CONFIG_BAUDRATE 115200
 538
 539 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 540         "netdev=eth0\0"                                                 \
 541         "consoledev=ttyCPM\0"                                           \
 542         "ramdiskaddr=1000000\0"                                         \
 543         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 544         "fdtaddr=400000\0"                                              \
 545         "fdtfile=mpc8560ads.dtb\0"
 546
 547 #define CONFIG_NFSBOOTCOMMAND                                           \
 548         "setenv bootargs root=/dev/nfs rw "                             \
 549                 "nfsroot=$serverip:$rootpath "                          \
 550                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 551                 "console=$consoledev,$baudrate $othbootargs;"           \
 552         "tftp $loadaddr $bootfile;"                                     \
 553         "tftp $fdtaddr $fdtfile;"                                       \
 554         "bootm $loadaddr - $fdtaddr"
 555
 556 #define CONFIG_RAMBOOTCOMMAND \
 557         "setenv bootargs root=/dev/ram rw "                             \
 558                 "console=$consoledev,$baudrate $othbootargs;"           \
 559         "tftp $ramdiskaddr $ramdiskfile;"                               \
 560         "tftp $loadaddr $bootfile;"                                     \
 561         "tftp $fdtaddr $fdtfile;"                                       \
 562         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 563
 564 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 565
 566 #endif  /* __CONFIG_H */