include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * mpc8560ads board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_CPM2             1       /* has CPM2 */
  42 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  43 #define CONFIG_MPC8560          1
  44
  45 /*
  46  * default CCARBAR is at 0xff700000
  47  * assume U-Boot is less than 0.5MB
  48  */
  49 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  50
  51 #define CONFIG_PCI
  52 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  53 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  54 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  55 #define CONFIG_ENV_OVERWRITE
  56 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  57 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  58
  59 /*
  60  * sysclk for MPC85xx
  61  *
  62  * Two valid values are:
  63  *    33000000
  64  *    66000000
  65  *
  66  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  67  * is likely the desired value here, so that is now the default.
  68  * The board, however, can run at 66MHz.  In any event, this value
  69  * must match the settings of some switches.  Details can be found
  70  * in the README.mpc85xxads.
  71  */
  72
  73 #ifndef CONFIG_SYS_CLK_FREQ
  74 #define CONFIG_SYS_CLK_FREQ     33000000
  75 #endif
  76
  77
  78 /*
  79  * These can be toggled for performance analysis, otherwise use default.
  80  */
  81 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  82 #define CONFIG_BTB                      /* toggle branch predition */
  83
  84 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  85
  86 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  87 #define CONFIG_SYS_MEMTEST_END          0x00400000
  88
  89 #define CONFIG_SYS_CCSRBAR              0xe0000000
  90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  91
  92 /* DDR Setup */
  93 #define CONFIG_FSL_DDR1
  94 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  95 #define CONFIG_DDR_SPD
  96 #undef CONFIG_FSL_DDR_INTERACTIVE
  97
  98 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  99
 100 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 101 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 102
 103 #define CONFIG_NUM_DDR_CONTROLLERS      1
 104 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 105 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 106
 107 /* I2C addresses of SPD EEPROMs */
 108 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 109
 110 /* These are used when DDR doesn't use SPD.  */
 111 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
 112 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
 113 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
 114 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 115 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 116 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 117 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 118 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 119
 120 /*
 121  * SDRAM on the Local Bus
 122  */
 123 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 124 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 125
 126 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 127 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 128
 129 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 132 #undef  CONFIG_SYS_FLASH_CHECKSUM
 133 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 134 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 135
 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 137
 138 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 139 #define CONFIG_SYS_RAMBOOT
 140 #else
 141 #undef  CONFIG_SYS_RAMBOOT
 142 #endif
 143
 144 #define CONFIG_FLASH_CFI_DRIVER
 145 #define CONFIG_SYS_FLASH_CFI
 146 #define CONFIG_SYS_FLASH_EMPTY_INFO
 147
 148 #undef CONFIG_CLOCKS_IN_MHZ
 149
 150
 151 /*
 152  * Local Bus Definitions
 153  */
 154
 155 /*
 156  * Base Register 2 and Option Register 2 configure SDRAM.
 157  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 158  *
 159  * For BR2, need:
 160  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 161  *    port-size = 32-bits = BR2[19:20] = 11
 162  *    no parity checking = BR2[21:22] = 00
 163  *    SDRAM for MSEL = BR2[24:26] = 011
 164  *    Valid = BR[31] = 1
 165  *
 166  * 0    4    8    12   16   20   24   28
 167  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 168  *
 169  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 170  * FIXME: the top 17 bits of BR2.
 171  */
 172
 173 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 174
 175 /*
 176  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 177  *
 178  * For OR2, need:
 179  *    64MB mask for AM, OR2[0:7] = 1111 1100
 180  *                 XAM, OR2[17:18] = 11
 181  *    9 columns OR2[19-21] = 010
 182  *    13 rows   OR2[23-25] = 100
 183  *    EAD set for extra time OR[31] = 1
 184  *
 185  * 0    4    8    12   16   20   24   28
 186  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 187  */
 188
 189 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 190
 191 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 192 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 193 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 194 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 195
 196 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 197                                 | LSDMR_RFCR5           \
 198                                 | LSDMR_PRETOACT3       \
 199                                 | LSDMR_ACTTORW3        \
 200                                 | LSDMR_BL8             \
 201                                 | LSDMR_WRC2            \
 202                                 | LSDMR_CL3             \
 203                                 | LSDMR_RFEN            \
 204                                 )
 205
 206 /*
 207  * SDRAM Controller configuration sequence.
 208  */
 209 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 210 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 211 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 212 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 213 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 214
 215
 216 /*
 217  * 32KB, 8-bit wide for ADS config reg
 218  */
 219 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 220 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 221 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 222
 223 #define CONFIG_SYS_INIT_RAM_LOCK        1
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 225 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 226
 227 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 228 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 229
 230 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 231 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 232
 233 /* Serial Port */
 234 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 235 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 236 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 237
 238 #define CONFIG_BAUDRATE         115200
 239
 240 #define CONFIG_SYS_BAUDRATE_TABLE  \
 241         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 242
 243 /* Use the HUSH parser */
 244 #define CONFIG_SYS_HUSH_PARSER
 245 #ifdef  CONFIG_SYS_HUSH_PARSER
 246 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 247 #endif
 248
 249 /* pass open firmware flat tree */
 250 #define CONFIG_OF_LIBFDT                1
 251 #define CONFIG_OF_BOARD_SETUP           1
 252 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 253
 254 /*
 255  * I2C
 256  */
 257 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 258 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 259 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 260 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 261 #define CONFIG_SYS_I2C_SLAVE            0x7F
 262 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 263 #define CONFIG_SYS_I2C_OFFSET           0x3000
 264
 265 /* RapidIO MMU */
 266 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 267 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 268 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 269 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 270
 271 /*
 272  * General PCI
 273  * Memory space is mapped 1-1, but I/O space must start from 0.
 274  */
 275 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 276 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 277 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 278 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 279 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 280 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 281 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 282 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 283
 284 #if defined(CONFIG_PCI)
 285
 286 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 287
 288 #undef CONFIG_EEPRO100
 289 #undef CONFIG_TULIP
 290
 291 #if !defined(CONFIG_PCI_PNP)
 292     #define PCI_ENET0_IOADDR    0xe0000000
 293     #define PCI_ENET0_MEMADDR   0xe0000000
 294     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 295 #endif
 296
 297 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 298 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 299
 300 #endif  /* CONFIG_PCI */
 301
 302
 303 #ifdef CONFIG_TSEC_ENET
 304
 305 #ifndef CONFIG_MII
 306 #define CONFIG_MII              1       /* MII PHY management */
 307 #endif
 308 #define CONFIG_TSEC1    1
 309 #define CONFIG_TSEC1_NAME       "TSEC0"
 310 #define CONFIG_TSEC2    1
 311 #define CONFIG_TSEC2_NAME       "TSEC1"
 312 #define TSEC1_PHY_ADDR          0
 313 #define TSEC2_PHY_ADDR          1
 314 #define TSEC1_PHYIDX            0
 315 #define TSEC2_PHYIDX            0
 316 #define TSEC1_FLAGS             TSEC_GIGABIT
 317 #define TSEC2_FLAGS             TSEC_GIGABIT
 318
 319 /* Options are: TSEC[0-1] */
 320 #define CONFIG_ETHPRIME         "TSEC0"
 321
 322 #endif /* CONFIG_TSEC_ENET */
 323
 324 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 325
 326 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 327 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 328
 329 #if (CONFIG_ETHER_INDEX == 2)
 330   /*
 331    * - Rx-CLK is CLK13
 332    * - Tx-CLK is CLK14
 333    * - Select bus for bd/buffers
 334    * - Full duplex
 335    */
 336   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 337   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 338   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 339   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 340   #define FETH2_RST             0x01
 341 #elif (CONFIG_ETHER_INDEX == 3)
 342   /* need more definitions here for FE3 */
 343   #define FETH3_RST             0x80
 344 #endif                                  /* CONFIG_ETHER_INDEX */
 345
 346 #ifndef CONFIG_MII
 347 #define CONFIG_MII              1       /* MII PHY management */
 348 #endif
 349
 350 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 351
 352 /*
 353  * GPIO pins used for bit-banged MII communications
 354  */
 355 #define MDIO_PORT       2               /* Port C */
 356 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 357                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 358 #define MDC_DECLARE     MDIO_DECLARE
 359
 360 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 361 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 362 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 363
 364 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 365                         else    iop->pdat &= ~0x00400000
 366
 367 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 368                         else    iop->pdat &= ~0x00200000
 369
 370 #define MIIDELAY        udelay(1)
 371
 372 #endif
 373
 374
 375 /*
 376  * Environment
 377  */
 378 #ifndef CONFIG_SYS_RAMBOOT
 379   #define CONFIG_ENV_IS_IN_FLASH        1
 380   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 381   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 382   #define CONFIG_ENV_SIZE               0x2000
 383 #else
 384   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 385   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 386   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 387   #define CONFIG_ENV_SIZE               0x2000
 388 #endif
 389
 390 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 391 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 392
 393 /*
 394  * BOOTP options
 395  */
 396 #define CONFIG_BOOTP_BOOTFILESIZE
 397 #define CONFIG_BOOTP_BOOTPATH
 398 #define CONFIG_BOOTP_GATEWAY
 399 #define CONFIG_BOOTP_HOSTNAME
 400
 401
 402 /*
 403  * Command line configuration.
 404  */
 405 #include <config_cmd_default.h>
 406
 407 #define CONFIG_CMD_PING
 408 #define CONFIG_CMD_I2C
 409 #define CONFIG_CMD_ELF
 410 #define CONFIG_CMD_IRQ
 411 #define CONFIG_CMD_SETEXPR
 412 #define CONFIG_CMD_REGINFO
 413
 414 #if defined(CONFIG_PCI)
 415     #define CONFIG_CMD_PCI
 416 #endif
 417
 418 #if defined(CONFIG_ETHER_ON_FCC)
 419     #define CONFIG_CMD_MII
 420 #endif
 421
 422 #if defined(CONFIG_SYS_RAMBOOT)
 423     #undef CONFIG_CMD_SAVEENV
 424     #undef CONFIG_CMD_LOADS
 425 #endif
 426
 427
 428 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 429
 430 /*
 431  * Miscellaneous configurable options
 432  */
 433 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 434 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 435 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 436 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 437 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 438
 439 #if defined(CONFIG_CMD_KGDB)
 440     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 441 #else
 442     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 443 #endif
 444
 445 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 446 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 447 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 448 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 449
 450 /*
 451  * For booting Linux, the board info and command line data
 452  * have to be in the first 64 MB of memory, since this is
 453  * the maximum mapped by the Linux kernel during initialization.
 454  */
 455 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 456 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 457
 458 #if defined(CONFIG_CMD_KGDB)
 459 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 460 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 461 #endif
 462
 463
 464 /*
 465  * Environment Configuration
 466  */
 467
 468 /* The mac addresses for all ethernet interface */
 469 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 470 #define CONFIG_HAS_ETH0
 471 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 472 #define CONFIG_HAS_ETH1
 473 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 474 #define CONFIG_HAS_ETH2
 475 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 476 #define CONFIG_HAS_ETH3
 477 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 478 #endif
 479
 480 #define CONFIG_IPADDR    192.168.1.253
 481
 482 #define CONFIG_HOSTNAME         unknown
 483 #define CONFIG_ROOTPATH         /nfsroot
 484 #define CONFIG_BOOTFILE         your.uImage
 485
 486 #define CONFIG_SERVERIP  192.168.1.1
 487 #define CONFIG_GATEWAYIP 192.168.1.1
 488 #define CONFIG_NETMASK   255.255.255.0
 489
 490 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 491
 492 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 493 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 494
 495 #define CONFIG_BAUDRATE 115200
 496
 497 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 498         "netdev=eth0\0"                                                 \
 499         "consoledev=ttyCPM\0"                                           \
 500         "ramdiskaddr=1000000\0"                                         \
 501         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 502         "fdtaddr=400000\0"                                              \
 503         "fdtfile=mpc8560ads.dtb\0"
 504
 505 #define CONFIG_NFSBOOTCOMMAND                                           \
 506         "setenv bootargs root=/dev/nfs rw "                             \
 507                 "nfsroot=$serverip:$rootpath "                          \
 508                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 509                 "console=$consoledev,$baudrate $othbootargs;"           \
 510         "tftp $loadaddr $bootfile;"                                     \
 511         "tftp $fdtaddr $fdtfile;"                                       \
 512         "bootm $loadaddr - $fdtaddr"
 513
 514 #define CONFIG_RAMBOOTCOMMAND \
 515         "setenv bootargs root=/dev/ram rw "                             \
 516                 "console=$consoledev,$baudrate $othbootargs;"           \
 517         "tftp $ramdiskaddr $ramdiskfile;"                               \
 518         "tftp $loadaddr $bootfile;"                                     \
 519         "tftp $fdtaddr $fdtfile;"                                       \
 520         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 521
 522 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 523
 524 #endif  /* __CONFIG_H */