include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * mpc8560ads board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_CPM2             1       /* has CPM2 */
  42 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  43 #define CONFIG_MPC8560          1
  44
  45 /*
  46  * default CCARBAR is at 0xff700000
  47  * assume U-Boot is less than 0.5MB
  48  */
  49 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  50
  51 #define CONFIG_PCI
  52 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  53 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  54 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  55 #define CONFIG_ENV_OVERWRITE
  56 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  57 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  58
  59 /*
  60  * sysclk for MPC85xx
  61  *
  62  * Two valid values are:
  63  *    33000000
  64  *    66000000
  65  *
  66  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  67  * is likely the desired value here, so that is now the default.
  68  * The board, however, can run at 66MHz.  In any event, this value
  69  * must match the settings of some switches.  Details can be found
  70  * in the README.mpc85xxads.
  71  */
  72
  73 #ifndef CONFIG_SYS_CLK_FREQ
  74 #define CONFIG_SYS_CLK_FREQ     33000000
  75 #endif
  76
  77
  78 /*
  79  * These can be toggled for performance analysis, otherwise use default.
  80  */
  81 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  82 #define CONFIG_BTB                      /* toggle branch predition */
  83
  84 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  85
  86 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  87 #define CONFIG_SYS_MEMTEST_END          0x00400000
  88
  89
  90 /*
  91  * Base addresses -- Note these are effective addresses where the
  92  * actual resources get mapped (not physical addresses)
  93  */
  94 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  95 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  96 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  97 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  98
  99 /* DDR Setup */
 100 #define CONFIG_FSL_DDR1
 101 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 102 #define CONFIG_DDR_SPD
 103 #undef CONFIG_FSL_DDR_INTERACTIVE
 104
 105 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 106
 107 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 109
 110 #define CONFIG_NUM_DDR_CONTROLLERS      1
 111 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 112 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 113
 114 /* I2C addresses of SPD EEPROMs */
 115 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 116
 117 /* These are used when DDR doesn't use SPD.  */
 118 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
 119 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
 120 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
 121 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 122 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 123 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 124 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 125 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 126
 127 /*
 128  * SDRAM on the Local Bus
 129  */
 130 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 131 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 132
 133 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 134 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 135
 136 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 137 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 138 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 139 #undef  CONFIG_SYS_FLASH_CHECKSUM
 140 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 141 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 142
 143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 144
 145 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 146 #define CONFIG_SYS_RAMBOOT
 147 #else
 148 #undef  CONFIG_SYS_RAMBOOT
 149 #endif
 150
 151 #define CONFIG_FLASH_CFI_DRIVER
 152 #define CONFIG_SYS_FLASH_CFI
 153 #define CONFIG_SYS_FLASH_EMPTY_INFO
 154
 155 #undef CONFIG_CLOCKS_IN_MHZ
 156
 157
 158 /*
 159  * Local Bus Definitions
 160  */
 161
 162 /*
 163  * Base Register 2 and Option Register 2 configure SDRAM.
 164  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 165  *
 166  * For BR2, need:
 167  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 168  *    port-size = 32-bits = BR2[19:20] = 11
 169  *    no parity checking = BR2[21:22] = 00
 170  *    SDRAM for MSEL = BR2[24:26] = 011
 171  *    Valid = BR[31] = 1
 172  *
 173  * 0    4    8    12   16   20   24   28
 174  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 175  *
 176  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 177  * FIXME: the top 17 bits of BR2.
 178  */
 179
 180 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 181
 182 /*
 183  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 184  *
 185  * For OR2, need:
 186  *    64MB mask for AM, OR2[0:7] = 1111 1100
 187  *                 XAM, OR2[17:18] = 11
 188  *    9 columns OR2[19-21] = 010
 189  *    13 rows   OR2[23-25] = 100
 190  *    EAD set for extra time OR[31] = 1
 191  *
 192  * 0    4    8    12   16   20   24   28
 193  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 194  */
 195
 196 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 197
 198 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 199 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 200 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 201 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 202
 203 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 204                                 | LSDMR_RFCR5           \
 205                                 | LSDMR_PRETOACT3       \
 206                                 | LSDMR_ACTTORW3        \
 207                                 | LSDMR_BL8             \
 208                                 | LSDMR_WRC2            \
 209                                 | LSDMR_CL3             \
 210                                 | LSDMR_RFEN            \
 211                                 )
 212
 213 /*
 214  * SDRAM Controller configuration sequence.
 215  */
 216 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 217 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 218 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 219 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 220 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 221
 222
 223 /*
 224  * 32KB, 8-bit wide for ADS config reg
 225  */
 226 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 227 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 228 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 229
 230 #define CONFIG_SYS_INIT_RAM_LOCK        1
 231 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 232 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 233
 234 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 235 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 236 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 237
 238 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 239 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 240
 241 /* Serial Port */
 242 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 243 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 244 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 245
 246 #define CONFIG_BAUDRATE         115200
 247
 248 #define CONFIG_SYS_BAUDRATE_TABLE  \
 249         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 250
 251 /* Use the HUSH parser */
 252 #define CONFIG_SYS_HUSH_PARSER
 253 #ifdef  CONFIG_SYS_HUSH_PARSER
 254 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 255 #endif
 256
 257 /* pass open firmware flat tree */
 258 #define CONFIG_OF_LIBFDT                1
 259 #define CONFIG_OF_BOARD_SETUP           1
 260 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 261
 262 /*
 263  * I2C
 264  */
 265 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 266 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 267 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 268 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 269 #define CONFIG_SYS_I2C_SLAVE            0x7F
 270 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 271 #define CONFIG_SYS_I2C_OFFSET           0x3000
 272
 273 /* RapidIO MMU */
 274 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 275 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 276 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 277 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 278
 279 /*
 280  * General PCI
 281  * Memory space is mapped 1-1, but I/O space must start from 0.
 282  */
 283 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 284 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 285 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 286 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 287 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 288 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 289 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 290 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 291
 292 #if defined(CONFIG_PCI)
 293
 294 #define CONFIG_NET_MULTI
 295 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 296
 297 #undef CONFIG_EEPRO100
 298 #undef CONFIG_TULIP
 299
 300 #if !defined(CONFIG_PCI_PNP)
 301     #define PCI_ENET0_IOADDR    0xe0000000
 302     #define PCI_ENET0_MEMADDR   0xe0000000
 303     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 304 #endif
 305
 306 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 307 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 308
 309 #endif  /* CONFIG_PCI */
 310
 311
 312 #ifdef CONFIG_TSEC_ENET
 313
 314 #ifndef CONFIG_NET_MULTI
 315 #define CONFIG_NET_MULTI        1
 316 #endif
 317
 318 #ifndef CONFIG_MII
 319 #define CONFIG_MII              1       /* MII PHY management */
 320 #endif
 321 #define CONFIG_TSEC1    1
 322 #define CONFIG_TSEC1_NAME       "TSEC0"
 323 #define CONFIG_TSEC2    1
 324 #define CONFIG_TSEC2_NAME       "TSEC1"
 325 #define TSEC1_PHY_ADDR          0
 326 #define TSEC2_PHY_ADDR          1
 327 #define TSEC1_PHYIDX            0
 328 #define TSEC2_PHYIDX            0
 329 #define TSEC1_FLAGS             TSEC_GIGABIT
 330 #define TSEC2_FLAGS             TSEC_GIGABIT
 331
 332 /* Options are: TSEC[0-1] */
 333 #define CONFIG_ETHPRIME         "TSEC0"
 334
 335 #endif /* CONFIG_TSEC_ENET */
 336
 337 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 338
 339 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 340 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 341
 342 #if (CONFIG_ETHER_INDEX == 2)
 343   /*
 344    * - Rx-CLK is CLK13
 345    * - Tx-CLK is CLK14
 346    * - Select bus for bd/buffers
 347    * - Full duplex
 348    */
 349   #define CONFIG_SYS_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 350   #define CONFIG_SYS_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 351   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 352   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 353   #define FETH2_RST             0x01
 354 #elif (CONFIG_ETHER_INDEX == 3)
 355   /* need more definitions here for FE3 */
 356   #define FETH3_RST             0x80
 357 #endif                                  /* CONFIG_ETHER_INDEX */
 358
 359 #ifndef CONFIG_MII
 360 #define CONFIG_MII              1       /* MII PHY management */
 361 #endif
 362
 363 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 364
 365 /*
 366  * GPIO pins used for bit-banged MII communications
 367  */
 368 #define MDIO_PORT       2               /* Port C */
 369 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 370                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 371 #define MDC_DECLARE     MDIO_DECLARE
 372
 373 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 374 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 375 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 376
 377 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 378                         else    iop->pdat &= ~0x00400000
 379
 380 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 381                         else    iop->pdat &= ~0x00200000
 382
 383 #define MIIDELAY        udelay(1)
 384
 385 #endif
 386
 387
 388 /*
 389  * Environment
 390  */
 391 #ifndef CONFIG_SYS_RAMBOOT
 392   #define CONFIG_ENV_IS_IN_FLASH        1
 393   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 394   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 395   #define CONFIG_ENV_SIZE               0x2000
 396 #else
 397   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 398   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 399   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 400   #define CONFIG_ENV_SIZE               0x2000
 401 #endif
 402
 403 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 404 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 405
 406 /*
 407  * BOOTP options
 408  */
 409 #define CONFIG_BOOTP_BOOTFILESIZE
 410 #define CONFIG_BOOTP_BOOTPATH
 411 #define CONFIG_BOOTP_GATEWAY
 412 #define CONFIG_BOOTP_HOSTNAME
 413
 414
 415 /*
 416  * Command line configuration.
 417  */
 418 #include <config_cmd_default.h>
 419
 420 #define CONFIG_CMD_PING
 421 #define CONFIG_CMD_I2C
 422 #define CONFIG_CMD_ELF
 423 #define CONFIG_CMD_IRQ
 424 #define CONFIG_CMD_SETEXPR
 425 #define CONFIG_CMD_REGINFO
 426
 427 #if defined(CONFIG_PCI)
 428     #define CONFIG_CMD_PCI
 429 #endif
 430
 431 #if defined(CONFIG_ETHER_ON_FCC)
 432     #define CONFIG_CMD_MII
 433 #endif
 434
 435 #if defined(CONFIG_SYS_RAMBOOT)
 436     #undef CONFIG_CMD_SAVEENV
 437     #undef CONFIG_CMD_LOADS
 438 #endif
 439
 440
 441 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 442
 443 /*
 444  * Miscellaneous configurable options
 445  */
 446 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 447 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 448 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 449 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 450 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 451
 452 #if defined(CONFIG_CMD_KGDB)
 453     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 454 #else
 455     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 456 #endif
 457
 458 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 459 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 460 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 461 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 462
 463 /*
 464  * For booting Linux, the board info and command line data
 465  * have to be in the first 16 MB of memory, since this is
 466  * the maximum mapped by the Linux kernel during initialization.
 467  */
 468 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 469
 470 #if defined(CONFIG_CMD_KGDB)
 471 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 472 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 473 #endif
 474
 475
 476 /*
 477  * Environment Configuration
 478  */
 479
 480 /* The mac addresses for all ethernet interface */
 481 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 482 #define CONFIG_HAS_ETH0
 483 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 484 #define CONFIG_HAS_ETH1
 485 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 486 #define CONFIG_HAS_ETH2
 487 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 488 #define CONFIG_HAS_ETH3
 489 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 490 #endif
 491
 492 #define CONFIG_IPADDR    192.168.1.253
 493
 494 #define CONFIG_HOSTNAME         unknown
 495 #define CONFIG_ROOTPATH         /nfsroot
 496 #define CONFIG_BOOTFILE         your.uImage
 497
 498 #define CONFIG_SERVERIP  192.168.1.1
 499 #define CONFIG_GATEWAYIP 192.168.1.1
 500 #define CONFIG_NETMASK   255.255.255.0
 501
 502 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 503
 504 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 505 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 506
 507 #define CONFIG_BAUDRATE 115200
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 510         "netdev=eth0\0"                                                 \
 511         "consoledev=ttyCPM\0"                                           \
 512         "ramdiskaddr=1000000\0"                                         \
 513         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 514         "fdtaddr=400000\0"                                              \
 515         "fdtfile=mpc8560ads.dtb\0"
 516
 517 #define CONFIG_NFSBOOTCOMMAND                                           \
 518         "setenv bootargs root=/dev/nfs rw "                             \
 519                 "nfsroot=$serverip:$rootpath "                          \
 520                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 521                 "console=$consoledev,$baudrate $othbootargs;"           \
 522         "tftp $loadaddr $bootfile;"                                     \
 523         "tftp $fdtaddr $fdtfile;"                                       \
 524         "bootm $loadaddr - $fdtaddr"
 525
 526 #define CONFIG_RAMBOOTCOMMAND \
 527         "setenv bootargs root=/dev/ram rw "                             \
 528                 "console=$consoledev,$baudrate $othbootargs;"           \
 529         "tftp $ramdiskaddr $ramdiskfile;"                               \
 530         "tftp $loadaddr $bootfile;"                                     \
 531         "tftp $fdtaddr $fdtfile;"                                       \
 532         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 533
 534 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 535
 536 #endif  /* __CONFIG_H */