include/configs/MPC8568MDS.h

   1 /*
   2  * Copyright 2004-2007, 2010 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8568mds board configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_BOOKE            1       /* BOOKE */
  31 #define CONFIG_E500             1       /* BOOKE e500 family */
  32 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/68 */
  33 #define CONFIG_MPC8568          1       /* MPC8568 specific */
  34 #define CONFIG_MPC8568MDS       1       /* MPC8568MDS board specific */
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  37
  38 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  39 #define CONFIG_PCI1             1       /* PCI controller */
  40 #define CONFIG_PCIE1            1       /* PCIE controller */
  41 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  42 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  43 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  44 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  45 #define CONFIG_QE                       /* Enable QE */
  46 #define CONFIG_ENV_OVERWRITE
  47 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  48
  49 #ifndef __ASSEMBLY__
  50 extern unsigned long get_clock_freq(void);
  51 #endif                                            /*Replace a call to get_clock_freq (after it is implemented)*/
  52 #define CONFIG_SYS_CLK_FREQ     66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
  53
  54 /*
  55  * These can be toggled for performance analysis, otherwise use default.
  56  */
  57 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  58 #define CONFIG_BTB                              /* toggle branch predition */
  59
  60 /*
  61  * Only possible on E500 Version 2 or newer cores.
  62  */
  63 #define CONFIG_ENABLE_36BIT_PHYS        1
  64
  65
  66 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  67
  68 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  69 #define CONFIG_SYS_MEMTEST_END          0x00400000
  70
  71 /*
  72  * Base addresses -- Note these are effective addresses where the
  73  * actual resources get mapped (not physical addresses)
  74  */
  75 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  76 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  77 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  78 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  79
  80 /* DDR Setup */
  81 #define CONFIG_FSL_DDR2
  82 #undef CONFIG_FSL_DDR_INTERACTIVE
  83 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  84 #define CONFIG_DDR_SPD
  85 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  86
  87 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  88
  89 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  90 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  91
  92 #define CONFIG_NUM_DDR_CONTROLLERS      1
  93 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  94 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  95
  96 /* I2C addresses of SPD EEPROMs */
  97 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  98
  99 /* Make sure required options are set */
 100 #ifndef CONFIG_SPD_EEPROM
 101 #error ("CONFIG_SPD_EEPROM is required")
 102 #endif
 103
 104 #undef CONFIG_CLOCKS_IN_MHZ
 105
 106 /*
 107  * Local Bus Definitions
 108  */
 109
 110 /*
 111  * FLASH on the Local Bus
 112  * Two banks, 8M each, using the CFI driver.
 113  * Boot from BR0/OR0 bank at 0xff00_0000
 114  * Alternate BR1/OR1 bank at 0xff80_0000
 115  *
 116  * BR0, BR1:
 117  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 118  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 119  *    Port Size = 16 bits = BRx[19:20] = 10
 120  *    Use GPCM = BRx[24:26] = 000
 121  *    Valid = BRx[31] = 1
 122  *
 123  * 0    4    8    12   16   20   24   28
 124  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 125  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 126  *
 127  * OR0, OR1:
 128  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 129  *    Reserved ORx[17:18] = 11, confusion here?
 130  *    CSNT = ORx[20] = 1
 131  *    ACS = half cycle delay = ORx[21:22] = 11
 132  *    SCY = 6 = ORx[24:27] = 0110
 133  *    TRLX = use relaxed timing = ORx[29] = 1
 134  *    EAD = use external address latch delay = OR[31] = 1
 135  *
 136  * 0    4    8    12   16   20   24   28
 137  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 138  */
 139 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 140
 141 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 142
 143 /*Chip select 0 - Flash*/
 144 #define CONFIG_SYS_BR0_PRELIM           0xfe001001
 145 #define CONFIG_SYS_OR0_PRELIM           0xfe006ff7
 146
 147 /*Chip slelect 1 - BCSR*/
 148 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 149 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 150
 151 /*#define CONFIG_SYS_FLASH_BANKS_LIST   {0xff800000, CONFIG_SYS_FLASH_BASE} */
 152 #define CONFIG_SYS_MAX_FLASH_BANKS              1               /* number of banks */
 153 #define CONFIG_SYS_MAX_FLASH_SECT               512             /* sectors per device */
 154 #undef  CONFIG_SYS_FLASH_CHECKSUM
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 157
 158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 159
 160 #define CONFIG_FLASH_CFI_DRIVER
 161 #define CONFIG_SYS_FLASH_CFI
 162 #define CONFIG_SYS_FLASH_EMPTY_INFO
 163
 164
 165 /*
 166  * SDRAM on the LocalBus
 167  */
 168 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM        */
 169 #define CONFIG_SYS_LBC_SDRAM_SIZE       64                      /* LBC SDRAM is 64MB */
 170
 171
 172 /*Chip select 2 - SDRAM*/
 173 #define CONFIG_SYS_BR2_PRELIM      0xf0001861
 174 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 175
 176 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 177 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 178 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 179 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 180
 181 /*
 182  * Common settings for all Local Bus SDRAM commands.
 183  * At run time, either BSMA1516 (for CPU 1.1)
 184  *                  or BSMA1617 (for CPU 1.0) (old)
 185  * is OR'ed in too.
 186  */
 187 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 188                                 | LSDMR_PRETOACT7       \
 189                                 | LSDMR_ACTTORW7        \
 190                                 | LSDMR_BL8             \
 191                                 | LSDMR_WRC4            \
 192                                 | LSDMR_CL3             \
 193                                 | LSDMR_RFEN            \
 194                                 )
 195
 196 /*
 197  * The bcsr registers are connected to CS3 on MDS.
 198  * The new memory map places bcsr at 0xf8000000.
 199  *
 200  * For BR3, need:
 201  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 202  *    port-size = 8-bits  = BR[19:20] = 01
 203  *    no parity checking  = BR[21:22] = 00
 204  *    GPMC for MSEL       = BR[24:26] = 000
 205  *    Valid               = BR[31]    = 1
 206  *
 207  * 0    4    8    12   16   20   24   28
 208  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 209  *
 210  * For OR3, need:
 211  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 212  *    disable buffer ctrl OR[19]    = 0
 213  *    CSNT                OR[20]    = 1
 214  *    ACS                 OR[21:22] = 11
 215  *    XACS                OR[23]    = 1
 216  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 217  *    SETA                OR[28]    = 0
 218  *    TRLX                OR[29]    = 1
 219  *    EHTR                OR[30]    = 1
 220  *    EAD extra time      OR[31]    = 1
 221  *
 222  * 0    4    8    12   16   20   24   28
 223  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 224  */
 225 #define CONFIG_SYS_BCSR (0xf8000000)
 226
 227 /*Chip slelect 4 - PIB*/
 228 #define CONFIG_SYS_BR4_PRELIM   0xf8008801
 229 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
 230
 231 /*Chip select 5 - PIB*/
 232 #define CONFIG_SYS_BR5_PRELIM    0xf8010801
 233 #define CONFIG_SYS_OR5_PRELIM    0xffff69f7
 234
 235 #define CONFIG_SYS_INIT_RAM_LOCK        1
 236 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 237 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 238
 239 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241
 242 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 243 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 244
 245 /* Serial Port */
 246 #define CONFIG_CONS_INDEX               1
 247 #define CONFIG_SYS_NS16550
 248 #define CONFIG_SYS_NS16550_SERIAL
 249 #define CONFIG_SYS_NS16550_REG_SIZE    1
 250 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 251
 252 #define CONFIG_SYS_BAUDRATE_TABLE  \
 253         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 254
 255 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 256 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 257
 258 /* Use the HUSH parser*/
 259 #define CONFIG_SYS_HUSH_PARSER
 260 #ifdef  CONFIG_SYS_HUSH_PARSER
 261 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 262 #endif
 263
 264 /* pass open firmware flat tree */
 265 #define CONFIG_OF_LIBFDT                1
 266 #define CONFIG_OF_BOARD_SETUP           1
 267 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 268
 269 /*
 270  * I2C
 271  */
 272 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 273 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 274 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 275 #define CONFIG_I2C_MULTI_BUS
 276 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 277 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 278 #define CONFIG_SYS_I2C_SLAVE            0x7F
 279 #define CONFIG_SYS_I2C_NOPROBES        {{0,0x69}}       /* Don't probe these addrs */
 280 #define CONFIG_SYS_I2C_OFFSET           0x3000
 281 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 282
 283 /*
 284  * General PCI
 285  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 286  */
 287 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 288 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 289 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 290 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 291 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 292 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 293 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 294 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000      /* 8M */
 295
 296 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 297 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 298 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 299 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 300 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 301 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 302 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 303 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 304 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 305
 306 #define CONFIG_SYS_SRIO_MEM_VIRT        0xc0000000
 307 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
 308 #define CONFIG_SYS_SRIO_MEM_PHYS        0xc0000000
 309
 310 #ifdef CONFIG_QE
 311 /*
 312  * QE UEC ethernet configuration
 313  */
 314 #define CONFIG_UEC_ETH
 315 #ifndef CONFIG_TSEC_ENET
 316 #define CONFIG_ETHPRIME         "UEC0"
 317 #endif
 318 #define CONFIG_PHY_MODE_NEED_CHANGE
 319 #define CONFIG_eTSEC_MDIO_BUS
 320
 321 #ifdef CONFIG_eTSEC_MDIO_BUS
 322 #define CONFIG_MIIM_ADDRESS     0xE0024520
 323 #endif
 324
 325 #define CONFIG_UEC_ETH1         /* GETH1 */
 326
 327 #ifdef CONFIG_UEC_ETH1
 328 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 329 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 330 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
 331 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 332 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 333 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
 334 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 335 #endif
 336
 337 #define CONFIG_UEC_ETH2         /* GETH2 */
 338
 339 #ifdef CONFIG_UEC_ETH2
 340 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 341 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 342 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
 343 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 344 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 345 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
 346 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 347 #endif
 348 #endif /* CONFIG_QE */
 349
 350 #if defined(CONFIG_PCI)
 351
 352 #define CONFIG_NET_MULTI
 353 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 354
 355 #undef CONFIG_EEPRO100
 356 #undef CONFIG_TULIP
 357
 358 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 359 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 360
 361 #endif  /* CONFIG_PCI */
 362
 363 #ifndef CONFIG_NET_MULTI
 364 #define CONFIG_NET_MULTI        1
 365 #endif
 366
 367 #if defined(CONFIG_TSEC_ENET)
 368
 369 #define CONFIG_MII              1       /* MII PHY management */
 370 #define CONFIG_TSEC1    1
 371 #define CONFIG_TSEC1_NAME       "eTSEC0"
 372 #define CONFIG_TSEC2    1
 373 #define CONFIG_TSEC2_NAME       "eTSEC1"
 374
 375 #define TSEC1_PHY_ADDR          2
 376 #define TSEC2_PHY_ADDR          3
 377
 378 #define TSEC1_PHYIDX            0
 379 #define TSEC2_PHYIDX            0
 380
 381 #define TSEC1_FLAGS             TSEC_GIGABIT
 382 #define TSEC2_FLAGS             TSEC_GIGABIT
 383
 384 /* Options are: eTSEC[0-1] */
 385 #define CONFIG_ETHPRIME         "eTSEC0"
 386
 387 #endif  /* CONFIG_TSEC_ENET */
 388
 389 /*
 390  * Environment
 391  */
 392 #define CONFIG_ENV_IS_IN_FLASH  1
 393 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 394 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 395 #define CONFIG_ENV_SIZE         0x2000
 396
 397 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 398 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 399
 400
 401 /*
 402  * BOOTP options
 403  */
 404 #define CONFIG_BOOTP_BOOTFILESIZE
 405 #define CONFIG_BOOTP_BOOTPATH
 406 #define CONFIG_BOOTP_GATEWAY
 407 #define CONFIG_BOOTP_HOSTNAME
 408
 409
 410 /*
 411  * Command line configuration.
 412  */
 413 #include <config_cmd_default.h>
 414
 415 #define CONFIG_CMD_PING
 416 #define CONFIG_CMD_I2C
 417 #define CONFIG_CMD_MII
 418 #define CONFIG_CMD_ELF
 419 #define CONFIG_CMD_IRQ
 420 #define CONFIG_CMD_SETEXPR
 421 #define CONFIG_CMD_REGINFO
 422
 423 #if defined(CONFIG_PCI)
 424     #define CONFIG_CMD_PCI
 425 #endif
 426
 427
 428 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 429
 430 /*
 431  * Miscellaneous configurable options
 432  */
 433 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 434 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 435 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 436 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 437 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 438 #if defined(CONFIG_CMD_KGDB)
 439 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 440 #else
 441 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size */
 442 #endif
 443 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 444 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 445 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 446 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 447
 448 /*
 449  * For booting Linux, the board info and command line data
 450  * have to be in the first 16 MB of memory, since this is
 451  * the maximum mapped by the Linux kernel during initialization.
 452  */
 453 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 454
 455 #if defined(CONFIG_CMD_KGDB)
 456 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 457 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 458 #endif
 459
 460 /*
 461  * Environment Configuration
 462  */
 463
 464 /* The mac addresses for all ethernet interface */
 465 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
 466 #define CONFIG_HAS_ETH0
 467 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 468 #define CONFIG_HAS_ETH1
 469 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 470 #define CONFIG_HAS_ETH2
 471 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 472 #define CONFIG_HAS_ETH3
 473 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 474 #endif
 475
 476 #define CONFIG_IPADDR    192.168.1.253
 477
 478 #define CONFIG_HOSTNAME  unknown
 479 #define CONFIG_ROOTPATH  /nfsroot
 480 #define CONFIG_BOOTFILE  your.uImage
 481
 482 #define CONFIG_SERVERIP  192.168.1.1
 483 #define CONFIG_GATEWAYIP 192.168.1.1
 484 #define CONFIG_NETMASK   255.255.255.0
 485
 486 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 487
 488 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 489 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 490
 491 #define CONFIG_BAUDRATE 115200
 492
 493 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 494    "netdev=eth0\0"                                                      \
 495    "consoledev=ttyS0\0"                                                 \
 496    "ramdiskaddr=600000\0"                                               \
 497    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 498    "fdtaddr=400000\0"                                                   \
 499    "fdtfile=your.fdt.dtb\0"                                             \
 500    "nfsargs=setenv bootargs root=/dev/nfs rw "                          \
 501       "nfsroot=$serverip:$rootpath "                                    \
 502       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 503       "console=$consoledev,$baudrate $othbootargs\0"                    \
 504    "ramargs=setenv bootargs root=/dev/ram rw "                          \
 505       "console=$consoledev,$baudrate $othbootargs\0"                    \
 506
 507
 508 #define CONFIG_NFSBOOTCOMMAND                                           \
 509    "run nfsargs;"                                                       \
 510    "tftp $loadaddr $bootfile;"                                          \
 511    "tftp $fdtaddr $fdtfile;"                                            \
 512    "bootm $loadaddr - $fdtaddr"
 513
 514
 515 #define CONFIG_RAMBOOTCOMMAND \
 516    "run ramargs;"                                                       \
 517    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 518    "tftp $loadaddr $bootfile;"                                          \
 519    "bootm $loadaddr $ramdiskaddr"
 520
 521 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 522
 523 #endif  /* __CONFIG_H */