include/configs/MPC8569MDS.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8569mds board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_ELBC         1       /* Has Enhance localbus controller */
  14
  15 #define CONFIG_SYS_SRIO
  16 #define CONFIG_SRIO1                    /* SRIO port 1 */
  17
  18 #define CONFIG_PCIE1            1       /* PCIE controller */
  19 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  20 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  21 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  22 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  23 #define CONFIG_QE                       /* Enable QE */
  24 #define CONFIG_ENV_OVERWRITE
  25
  26 #ifndef __ASSEMBLY__
  27 extern unsigned long get_clock_freq(void);
  28 #endif
  29 /* Replace a call to get_clock_freq (after it is implemented)*/
  30 #define CONFIG_SYS_CLK_FREQ     66666666
  31 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  32
  33 #ifdef CONFIG_ATM
  34 #define CONFIG_PQ_MDS_PIB
  35 #define CONFIG_PQ_MDS_PIB_ATM
  36 #endif
  37
  38 /*
  39  * These can be toggled for performance analysis, otherwise use default.
  40  */
  41 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  42 #define CONFIG_BTB                              /* toggle branch predition */
  43
  44 #ifndef CONFIG_SYS_TEXT_BASE
  45 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  46 #endif
  47
  48 #ifndef CONFIG_SYS_MONITOR_BASE
  49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  50 #endif
  51
  52 /*
  53  * Only possible on E500 Version 2 or newer cores.
  54  */
  55 #define CONFIG_ENABLE_36BIT_PHYS        1
  56
  57 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  58 #define CONFIG_BOARD_EARLY_INIT_R       1
  59 #define CONFIG_HWCONFIG
  60
  61 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  62 #define CONFIG_SYS_MEMTEST_END          0x00400000
  63
  64 /*
  65  * Config the L2 Cache as L2 SRAM
  66  */
  67 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  69 #define CONFIG_SYS_L2_SIZE              (512 << 10)
  70 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  71
  72 #define CONFIG_SYS_CCSRBAR              0xe0000000
  73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  74
  75 #if defined(CONFIG_NAND_SPL)
  76 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  77 #endif
  78
  79 /* DDR Setup */
  80 #undef CONFIG_FSL_DDR_INTERACTIVE
  81 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  82 #define CONFIG_DDR_SPD
  83 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  84
  85 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  86
  87 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  88                                         /* DDR is system memory*/
  89 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  90
  91 #define CONFIG_NUM_DDR_CONTROLLERS      1
  92 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  93 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  94
  95 /* I2C addresses of SPD EEPROMs */
  96 #define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
  97
  98 /* These are used when DDR doesn't use SPD.  */
  99 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1024MB */
 100 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 101 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 102 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 103 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 104 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
 105 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
 106 #define CONFIG_SYS_DDR_SDRAM_CFG        0x47000000
 107 #define CONFIG_SYS_DDR_SDRAM_CFG_2      0x04401040
 108 #define CONFIG_SYS_DDR_SDRAM_MODE       0x40401521
 109 #define CONFIG_SYS_DDR_SDRAM_MODE_2     0x8000C000
 110 #define CONFIG_SYS_DDR_SDRAM_INTERVAL   0x03E00000
 111 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 112 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x01000000
 113 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 114 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 115 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 116 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x0655A604
 117 #define CONFIG_SYS_DDR_CDR_1            0x80040000
 118 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 119 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 120 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 121 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
 122 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 123
 124 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 125 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 126 #define CONFIG_SYS_DDR_SBE              0x00010000
 127
 128 #undef CONFIG_CLOCKS_IN_MHZ
 129
 130 /*
 131  * Local Bus Definitions
 132  */
 133
 134 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 135 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 136
 137 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 138 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 139
 140 /*Chip select 0 - Flash*/
 141 #define CONFIG_FLASH_BR_PRELIM          0xfe000801
 142 #define CONFIG_FLASH_OR_PRELIM          0xfe000ff7
 143
 144 /*Chip select 1 - BCSR*/
 145 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 146 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 147
 148 /*Chip select 4 - PIB*/
 149 #define CONFIG_SYS_BR4_PRELIM           0xf8008801
 150 #define CONFIG_SYS_OR4_PRELIM           0xffffe9f7
 151
 152 /*Chip select 5 - PIB*/
 153 #define CONFIG_SYS_BR5_PRELIM           0xf8010801
 154 #define CONFIG_SYS_OR5_PRELIM           0xffffe9f7
 155
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 157 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 158 #undef  CONFIG_SYS_FLASH_CHECKSUM
 159 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 160 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 161
 162 #undef CONFIG_SYS_RAMBOOT
 163
 164 #define CONFIG_FLASH_CFI_DRIVER
 165 #define CONFIG_SYS_FLASH_CFI
 166 #define CONFIG_SYS_FLASH_EMPTY_INFO
 167
 168 /* Chip select 3 - NAND */
 169 #ifndef CONFIG_NAND_SPL
 170 #define CONFIG_SYS_NAND_BASE            0xFC000000
 171 #else
 172 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 173 #endif
 174
 175 /* NAND boot: 4K NAND loader config */
 176 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 177 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 178 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 179 #define CONFIG_SYS_NAND_U_BOOT_START \
 180         (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 181 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 182 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 183 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 184
 185 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 186 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, }
 187 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 188 #define CONFIG_CMD_NAND                 1
 189 #define CONFIG_NAND_FSL_ELBC            1
 190 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 191 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE_PHYS \
 192                                 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
 193                                 | BR_PS_8            /* Port Size = 8 bit */ \
 194                                 | BR_MS_FCM          /* MSEL = FCM */ \
 195                                 | BR_V)              /* valid */
 196 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000          /* length 256K */ \
 197                                 | OR_FCM_CSCT \
 198                                 | OR_FCM_CST \
 199                                 | OR_FCM_CHT \
 200                                 | OR_FCM_SCY_1 \
 201                                 | OR_FCM_TRLX \
 202                                 | OR_FCM_EHTR)
 203
 204 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 205 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 206 #define CONFIG_SYS_BR3_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 207 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 208
 209 #define CONFIG_SYS_LBC_LCRR     0x00000004      /* LB clock ratio reg */
 210 #define CONFIG_SYS_LBC_LBCR     0x00040000      /* LB config reg */
 211 #define CONFIG_SYS_LBC_LSRT     0x20000000      /* LB sdram refresh timer */
 212 #define CONFIG_SYS_LBC_MRTPR    0x00000000      /* LB refresh timer prescal*/
 213
 214 #define CONFIG_SYS_INIT_RAM_LOCK        1
 215 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000  /* Initial RAM address */
 216 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 217
 218 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 219                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 220 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 221
 222 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 223 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 224
 225 /* Serial Port */
 226 #define CONFIG_CONS_INDEX               1
 227 #define CONFIG_SYS_NS16550_SERIAL
 228 #define CONFIG_SYS_NS16550_REG_SIZE    1
 229 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 230 #ifdef CONFIG_NAND_SPL
 231 #define CONFIG_NS16550_MIN_FUNCTIONS
 232 #endif
 233
 234 #define CONFIG_SYS_BAUDRATE_TABLE  \
 235         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 236
 237 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 238 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 239
 240 /*
 241  * I2C
 242  */
 243 #define CONFIG_SYS_I2C
 244 #define CONFIG_SYS_I2C_FSL
 245 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 246 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 247 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 248 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 249 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 250 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 251 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 252
 253 /*
 254  * I2C2 EEPROM
 255  */
 256 #define CONFIG_ID_EEPROM
 257 #ifdef CONFIG_ID_EEPROM
 258 #define CONFIG_SYS_I2C_EEPROM_NXID
 259 #endif
 260 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 261 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 262 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 263
 264 #define PLPPAR1_I2C_BIT_MASK            0x0000000F
 265 #define PLPPAR1_I2C2_VAL                0x00000000
 266 #define PLPPAR1_ESDHC_VAL               0x0000000A
 267 #define PLPDIR1_I2C_BIT_MASK            0x0000000F
 268 #define PLPDIR1_I2C2_VAL                0x0000000F
 269 #define PLPDIR1_ESDHC_VAL               0x00000006
 270 #define PLPPAR1_UART0_BIT_MASK          0x00000fc0
 271 #define PLPPAR1_ESDHC_4BITS_VAL         0x00000a80
 272 #define PLPDIR1_UART0_BIT_MASK          0x00000fc0
 273 #define PLPDIR1_ESDHC_4BITS_VAL         0x00000a80
 274
 275 /*
 276  * General PCI
 277  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 278  */
 279 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 280 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 281 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 282 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 283 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 284 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 285 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 286 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 287 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 288
 289 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xC0000000
 290 #define CONFIG_SYS_SRIO1_MEM_BUS        0xC0000000
 291 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BUS
 292 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 293
 294 #ifdef CONFIG_QE
 295 /*
 296  * QE UEC ethernet configuration
 297  */
 298 #define CONFIG_SYS_UCC_RGMII_MODE       /* Set UCC work at RGMII by default */
 299 #undef CONFIG_SYS_UCC_RMII_MODE         /* Set UCC work at RMII mode */
 300
 301 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 302 #define CONFIG_UEC_ETH
 303 #define CONFIG_ETHPRIME         "UEC0"
 304 #define CONFIG_PHY_MODE_NEED_CHANGE
 305
 306 #define CONFIG_UEC_ETH1         /* GETH1 */
 307 #define CONFIG_HAS_ETH0
 308
 309 #ifdef CONFIG_UEC_ETH1
 310 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 311 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 312 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 313 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 314 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 315 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 316 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 317 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 318 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 319 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16 /* CLK16 for RMII */
 320 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 321 #define CONFIG_SYS_UEC1_PHY_ADDR       8        /* 0x8 for RMII */
 322 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 323 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 324 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 325 #endif /* CONFIG_UEC_ETH1 */
 326
 327 #define CONFIG_UEC_ETH2         /* GETH2 */
 328 #define CONFIG_HAS_ETH1
 329
 330 #ifdef CONFIG_UEC_ETH2
 331 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 332 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 333 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 334 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 335 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 336 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 337 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 338 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 339 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 340 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16 /* CLK 16 for RMII */
 341 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 342 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9      /* 0x9 for RMII */
 343 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 344 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 345 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 346 #endif /* CONFIG_UEC_ETH2 */
 347
 348 #define CONFIG_UEC_ETH3         /* GETH3 */
 349 #define CONFIG_HAS_ETH2
 350
 351 #ifdef CONFIG_UEC_ETH3
 352 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
 353 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
 354 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 355 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 356 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 357 #define CONFIG_SYS_UEC3_PHY_ADDR       2
 358 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 359 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 360 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 361 #define CONFIG_SYS_UEC3_TX_CLK          QE_CLK16 /* CLK_16 for RMII */
 362 #define CONFIG_SYS_UEC3_ETH_TYPE        FAST_ETH
 363 #define CONFIG_SYS_UEC3_PHY_ADDR        0xA     /* 0xA for RMII */
 364 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 365 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 366 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 367 #endif /* CONFIG_UEC_ETH3 */
 368
 369 #define CONFIG_UEC_ETH4         /* GETH4 */
 370 #define CONFIG_HAS_ETH3
 371
 372 #ifdef CONFIG_UEC_ETH4
 373 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
 374 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
 375 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 376 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 377 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 378 #define CONFIG_SYS_UEC4_PHY_ADDR       3
 379 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 380 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 381 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 382 #define CONFIG_SYS_UEC4_TX_CLK          QE_CLK16 /* CLK16 for RMII */
 383 #define CONFIG_SYS_UEC4_ETH_TYPE        FAST_ETH
 384 #define CONFIG_SYS_UEC4_PHY_ADDR        0xB     /* 0xB for RMII */
 385 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 386 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 387 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 388 #endif /* CONFIG_UEC_ETH4 */
 389
 390 #undef CONFIG_UEC_ETH6         /* GETH6 */
 391 #define CONFIG_HAS_ETH5
 392
 393 #ifdef CONFIG_UEC_ETH6
 394 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
 395 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
 396 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 397 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 398 #define CONFIG_SYS_UEC6_PHY_ADDR       4
 399 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 400 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 401 #endif /* CONFIG_UEC_ETH6 */
 402
 403 #undef CONFIG_UEC_ETH8         /* GETH8 */
 404 #define CONFIG_HAS_ETH7
 405
 406 #ifdef CONFIG_UEC_ETH8
 407 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
 408 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
 409 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 410 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 411 #define CONFIG_SYS_UEC8_PHY_ADDR       6
 412 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 413 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 414 #endif /* CONFIG_UEC_ETH8 */
 415
 416 #endif /* CONFIG_QE */
 417
 418 #if defined(CONFIG_PCI)
 419 #undef CONFIG_EEPRO100
 420 #undef CONFIG_TULIP
 421
 422 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 423
 424 #endif  /* CONFIG_PCI */
 425
 426 /*
 427  * Environment
 428  */
 429 #if defined(CONFIG_SYS_RAMBOOT)
 430 #else
 431 #define CONFIG_ENV_IS_IN_FLASH  1
 432 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 433 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 434 #define CONFIG_ENV_SIZE         0x2000
 435 #endif
 436
 437 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 438 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 439
 440 /* QE microcode/firmware address */
 441 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 442 #define CONFIG_SYS_QE_FW_ADDR   0xfff00000
 443
 444 /*
 445  * BOOTP options
 446  */
 447 #define CONFIG_BOOTP_BOOTFILESIZE
 448 #define CONFIG_BOOTP_BOOTPATH
 449 #define CONFIG_BOOTP_GATEWAY
 450 #define CONFIG_BOOTP_HOSTNAME
 451
 452 /*
 453  * Command line configuration.
 454  */
 455 #define CONFIG_CMD_IRQ
 456 #define CONFIG_CMD_REGINFO
 457
 458 #if defined(CONFIG_PCI)
 459     #define CONFIG_CMD_PCI
 460 #endif
 461
 462 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 463
 464 #ifdef CONFIG_MMC
 465 #define CONFIG_FSL_ESDHC
 466 #define CONFIG_FSL_ESDHC_PIN_MUX
 467 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 468 #define CONFIG_GENERIC_MMC
 469 #define CONFIG_DOS_PARTITION
 470 #endif
 471
 472 /*
 473  * Miscellaneous configurable options
 474  */
 475 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 476 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 477 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 478 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 479 #if defined(CONFIG_CMD_KGDB)
 480 #define CONFIG_SYS_CBSIZE       2048            /* Console I/O Buffer Size */
 481 #else
 482 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 483 #endif
 484 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 485                                                 /* Print Buffer Size */
 486 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
 487 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 488                                                 /* Boot Argument Buffer Size */
 489
 490 /*
 491  * For booting Linux, the board info and command line data
 492  * have to be in the first 64 MB of memory, since this is
 493  * the maximum mapped by the Linux kernel during initialization.
 494  */
 495 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux*/
 496 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 497
 498 #if defined(CONFIG_CMD_KGDB)
 499 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 500 #endif
 501
 502 /*
 503  * Environment Configuration
 504  */
 505 #define CONFIG_HOSTNAME mpc8569mds
 506 #define CONFIG_ROOTPATH  "/nfsroot"
 507 #define CONFIG_BOOTFILE  "your.uImage"
 508
 509 #define CONFIG_SERVERIP  192.168.1.1
 510 #define CONFIG_GATEWAYIP 192.168.1.1
 511 #define CONFIG_NETMASK   255.255.255.0
 512
 513 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 514
 515 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 516
 517 #define CONFIG_BAUDRATE 115200
 518
 519 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 520         "netdev=eth0\0"                                                 \
 521         "consoledev=ttyS0\0"                                            \
 522         "ramdiskaddr=600000\0"                                          \
 523         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 524         "fdtaddr=400000\0"                                              \
 525         "fdtfile=your.fdt.dtb\0"                                        \
 526         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 527         "nfsroot=$serverip:$rootpath "                                  \
 528         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 529         "console=$consoledev,$baudrate $othbootargs\0"                  \
 530         "ramargs=setenv bootargs root=/dev/ram rw "                     \
 531         "console=$consoledev,$baudrate $othbootargs\0"                  \
 532
 533 #define CONFIG_NFSBOOTCOMMAND                                           \
 534         "run nfsargs;"                                                  \
 535         "tftp $loadaddr $bootfile;"                                     \
 536         "tftp $fdtaddr $fdtfile;"                                       \
 537         "bootm $loadaddr - $fdtaddr"
 538
 539 #define CONFIG_RAMBOOTCOMMAND                                           \
 540         "run ramargs;"                                                  \
 541         "tftp $ramdiskaddr $ramdiskfile;"                               \
 542         "tftp $loadaddr $bootfile;"                                     \
 543         "bootm $loadaddr $ramdiskaddr"
 544
 545 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 546
 547 #endif  /* __CONFIG_H */