include/configs/MPC8569MDS.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8569mds board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_BOOKE            1       /* BOOKE */
  15 #define CONFIG_E500             1       /* BOOKE e500 family */
  16 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/68 */
  17 #define CONFIG_MPC8569          1       /* MPC8569 specific */
  18 #define CONFIG_MPC8569MDS       1       /* MPC8569MDS board specific */
  19
  20 #define CONFIG_FSL_ELBC         1       /* Has Enhance localbus controller */
  21
  22 #define CONFIG_SYS_SRIO
  23 #define CONFIG_SRIO1                    /* SRIO port 1 */
  24
  25 #define CONFIG_PCI              1       /* Disable PCI/PCIE */
  26 #define CONFIG_PCIE1            1       /* PCIE controller */
  27 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  28 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  29 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  30 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  31 #define CONFIG_QE                       /* Enable QE */
  32 #define CONFIG_ENV_OVERWRITE
  33 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  34
  35 #ifndef __ASSEMBLY__
  36 extern unsigned long get_clock_freq(void);
  37 #endif
  38 /* Replace a call to get_clock_freq (after it is implemented)*/
  39 #define CONFIG_SYS_CLK_FREQ     66666666
  40 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  41
  42 #ifdef CONFIG_ATM
  43 #define CONFIG_PQ_MDS_PIB
  44 #define CONFIG_PQ_MDS_PIB_ATM
  45 #endif
  46
  47 /*
  48  * These can be toggled for performance analysis, otherwise use default.
  49  */
  50 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  51 #define CONFIG_BTB                              /* toggle branch predition */
  52
  53 #ifdef CONFIG_NAND
  54 #define CONFIG_NAND_U_BOOT              1
  55 #define CONFIG_RAMBOOT_NAND             1
  56 #ifdef CONFIG_NAND_SPL
  57 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  59 #else
  60 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  61 #define CONFIG_SYS_TEXT_BASE    0xf8f82000
  62 #endif
  63 #endif
  64
  65 #ifndef CONFIG_SYS_TEXT_BASE
  66 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  67 #endif
  68
  69 #ifndef CONFIG_SYS_MONITOR_BASE
  70 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  71 #endif
  72
  73 /*
  74  * Only possible on E500 Version 2 or newer cores.
  75  */
  76 #define CONFIG_ENABLE_36BIT_PHYS        1
  77
  78 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  79 #define CONFIG_BOARD_EARLY_INIT_R       1
  80 #define CONFIG_HWCONFIG
  81
  82 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  83 #define CONFIG_SYS_MEMTEST_END          0x00400000
  84
  85 /*
  86  * Config the L2 Cache as L2 SRAM
  87  */
  88 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  89 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  90 #define CONFIG_SYS_L2_SIZE              (512 << 10)
  91 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  92
  93 #define CONFIG_SYS_CCSRBAR              0xe0000000
  94 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  95
  96 #if defined(CONFIG_NAND_SPL)
  97 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  98 #endif
  99
 100 /* DDR Setup */
 101 #define CONFIG_FSL_DDR3
 102 #undef CONFIG_FSL_DDR_INTERACTIVE
 103 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 104 #define CONFIG_DDR_SPD
 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 106
 107 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 108
 109 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 110                                         /* DDR is system memory*/
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 112
 113 #define CONFIG_NUM_DDR_CONTROLLERS      1
 114 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 115 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 116
 117 /* I2C addresses of SPD EEPROMs */
 118 #define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
 119
 120 /* These are used when DDR doesn't use SPD.  */
 121 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1024MB */
 122 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 123 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 124 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 125 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 126 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
 127 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
 128 #define CONFIG_SYS_DDR_SDRAM_CFG        0x47000000
 129 #define CONFIG_SYS_DDR_SDRAM_CFG_2      0x04401040
 130 #define CONFIG_SYS_DDR_SDRAM_MODE       0x40401521
 131 #define CONFIG_SYS_DDR_SDRAM_MODE_2     0x8000C000
 132 #define CONFIG_SYS_DDR_SDRAM_INTERVAL   0x03E00000
 133 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 134 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x01000000
 135 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 136 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 137 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 138 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x0655A604
 139 #define CONFIG_SYS_DDR_CDR_1            0x80040000
 140 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 141 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
 142 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 143 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
 144 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
 145
 146 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 147 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 148 #define CONFIG_SYS_DDR_SBE              0x00010000
 149
 150 #undef CONFIG_CLOCKS_IN_MHZ
 151
 152 /*
 153  * Local Bus Definitions
 154  */
 155
 156 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 157 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 158
 159 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 160 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 161
 162 /*Chip select 0 - Flash*/
 163 #define CONFIG_FLASH_BR_PRELIM          0xfe000801
 164 #define CONFIG_FLASH_OR_PRELIM          0xfe000ff7
 165
 166 /*Chip select 1 - BCSR*/
 167 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 168 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 169
 170 /*Chip select 4 - PIB*/
 171 #define CONFIG_SYS_BR4_PRELIM           0xf8008801
 172 #define CONFIG_SYS_OR4_PRELIM           0xffffe9f7
 173
 174 /*Chip select 5 - PIB*/
 175 #define CONFIG_SYS_BR5_PRELIM           0xf8010801
 176 #define CONFIG_SYS_OR5_PRELIM           0xffffe9f7
 177
 178 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 179 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 180 #undef  CONFIG_SYS_FLASH_CHECKSUM
 181 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 182 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 183
 184 #if defined(CONFIG_RAMBOOT_NAND)
 185 #define CONFIG_SYS_RAMBOOT
 186 #define CONFIG_SYS_EXTRA_ENV_RELOC
 187 #else
 188 #undef CONFIG_SYS_RAMBOOT
 189 #endif
 190
 191 #define CONFIG_FLASH_CFI_DRIVER
 192 #define CONFIG_SYS_FLASH_CFI
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO
 194
 195 /* Chip select 3 - NAND */
 196 #ifndef CONFIG_NAND_SPL
 197 #define CONFIG_SYS_NAND_BASE            0xFC000000
 198 #else
 199 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 200 #endif
 201
 202 /* NAND boot: 4K NAND loader config */
 203 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 204 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 205 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 206 #define CONFIG_SYS_NAND_U_BOOT_START \
 207         (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 208 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 209 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 210 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 211
 212 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 213 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, }
 214 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 215 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 216 #define CONFIG_CMD_NAND                 1
 217 #define CONFIG_NAND_FSL_ELBC            1
 218 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 219 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE_PHYS \
 220                                 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
 221                                 | BR_PS_8            /* Port Size = 8 bit */ \
 222                                 | BR_MS_FCM          /* MSEL = FCM */ \
 223                                 | BR_V)              /* valid */
 224 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000          /* length 256K */ \
 225                                 | OR_FCM_CSCT \
 226                                 | OR_FCM_CST \
 227                                 | OR_FCM_CHT \
 228                                 | OR_FCM_SCY_1 \
 229                                 | OR_FCM_TRLX \
 230                                 | OR_FCM_EHTR)
 231
 232 #ifdef CONFIG_RAMBOOT_NAND
 233 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 234 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
 235 #define CONFIG_SYS_BR3_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 236 #define CONFIG_SYS_OR3_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 237 #else
 238 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 239 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 240 #define CONFIG_SYS_BR3_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 241 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 242 #endif
 243
 244 #define CONFIG_SYS_LBC_LCRR     0x00000004      /* LB clock ratio reg */
 245 #define CONFIG_SYS_LBC_LBCR     0x00040000      /* LB config reg */
 246 #define CONFIG_SYS_LBC_LSRT     0x20000000      /* LB sdram refresh timer */
 247 #define CONFIG_SYS_LBC_MRTPR    0x00000000      /* LB refresh timer prescal*/
 248
 249 #define CONFIG_SYS_INIT_RAM_LOCK        1
 250 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000  /* Initial RAM address */
 251 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 252
 253 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 254                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 255 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 256
 257 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 258 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 259
 260 /* Serial Port */
 261 #define CONFIG_CONS_INDEX               1
 262 #define CONFIG_SYS_NS16550
 263 #define CONFIG_SYS_NS16550_SERIAL
 264 #define CONFIG_SYS_NS16550_REG_SIZE    1
 265 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 266 #ifdef CONFIG_NAND_SPL
 267 #define CONFIG_NS16550_MIN_FUNCTIONS
 268 #endif
 269
 270 #define CONFIG_SYS_BAUDRATE_TABLE  \
 271         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 272
 273 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 274 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 275
 276 /* Use the HUSH parser*/
 277 #define CONFIG_SYS_HUSH_PARSER
 278 #ifdef  CONFIG_SYS_HUSH_PARSER
 279 #endif
 280
 281 /* pass open firmware flat tree */
 282 #define CONFIG_OF_LIBFDT                1
 283 #define CONFIG_OF_BOARD_SETUP           1
 284 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 285
 286 /*
 287  * I2C
 288  */
 289 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 290 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 291 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 292 #define CONFIG_I2C_MULTI_BUS
 293 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 294 #define CONFIG_SYS_I2C_SLAVE    0x7F
 295 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 296 #define CONFIG_SYS_I2C_OFFSET   0x3000
 297 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 298
 299 /*
 300  * I2C2 EEPROM
 301  */
 302 #define CONFIG_ID_EEPROM
 303 #ifdef CONFIG_ID_EEPROM
 304 #define CONFIG_SYS_I2C_EEPROM_NXID
 305 #endif
 306 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 307 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 308 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 309
 310 #define PLPPAR1_I2C_BIT_MASK            0x0000000F
 311 #define PLPPAR1_I2C2_VAL                0x00000000
 312 #define PLPPAR1_ESDHC_VAL               0x0000000A
 313 #define PLPDIR1_I2C_BIT_MASK            0x0000000F
 314 #define PLPDIR1_I2C2_VAL                0x0000000F
 315 #define PLPDIR1_ESDHC_VAL               0x00000006
 316 #define PLPPAR1_UART0_BIT_MASK          0x00000fc0
 317 #define PLPPAR1_ESDHC_4BITS_VAL         0x00000a80
 318 #define PLPDIR1_UART0_BIT_MASK          0x00000fc0
 319 #define PLPDIR1_ESDHC_4BITS_VAL         0x00000a80
 320
 321 /*
 322  * General PCI
 323  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 324  */
 325 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 326 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 327 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 328 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 329 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 330 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 331 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 332 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 333 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 334
 335 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xC0000000
 336 #define CONFIG_SYS_SRIO1_MEM_BUS        0xC0000000
 337 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BUS
 338 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 339
 340 #ifdef CONFIG_QE
 341 /*
 342  * QE UEC ethernet configuration
 343  */
 344 #define CONFIG_SYS_UCC_RGMII_MODE       /* Set UCC work at RGMII by default */
 345 #undef CONFIG_SYS_UCC_RMII_MODE         /* Set UCC work at RMII mode */
 346
 347 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 348 #define CONFIG_UEC_ETH
 349 #define CONFIG_ETHPRIME         "UEC0"
 350 #define CONFIG_PHY_MODE_NEED_CHANGE
 351
 352 #define CONFIG_UEC_ETH1         /* GETH1 */
 353 #define CONFIG_HAS_ETH0
 354
 355 #ifdef CONFIG_UEC_ETH1
 356 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 357 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 358 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 359 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 360 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 361 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 362 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 363 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 364 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 365 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16 /* CLK16 for RMII */
 366 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 367 #define CONFIG_SYS_UEC1_PHY_ADDR       8        /* 0x8 for RMII */
 368 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 369 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 370 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 371 #endif /* CONFIG_UEC_ETH1 */
 372
 373 #define CONFIG_UEC_ETH2         /* GETH2 */
 374 #define CONFIG_HAS_ETH1
 375
 376 #ifdef CONFIG_UEC_ETH2
 377 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 378 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 379 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 380 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 381 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 382 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 383 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 384 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 385 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 386 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16 /* CLK 16 for RMII */
 387 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 388 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9      /* 0x9 for RMII */
 389 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 390 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 391 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 392 #endif /* CONFIG_UEC_ETH2 */
 393
 394 #define CONFIG_UEC_ETH3         /* GETH3 */
 395 #define CONFIG_HAS_ETH2
 396
 397 #ifdef CONFIG_UEC_ETH3
 398 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
 399 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
 400 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 401 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 402 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 403 #define CONFIG_SYS_UEC3_PHY_ADDR       2
 404 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 405 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 406 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 407 #define CONFIG_SYS_UEC3_TX_CLK          QE_CLK16 /* CLK_16 for RMII */
 408 #define CONFIG_SYS_UEC3_ETH_TYPE        FAST_ETH
 409 #define CONFIG_SYS_UEC3_PHY_ADDR        0xA     /* 0xA for RMII */
 410 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 411 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 412 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 413 #endif /* CONFIG_UEC_ETH3 */
 414
 415 #define CONFIG_UEC_ETH4         /* GETH4 */
 416 #define CONFIG_HAS_ETH3
 417
 418 #ifdef CONFIG_UEC_ETH4
 419 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
 420 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
 421 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 422 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 423 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 424 #define CONFIG_SYS_UEC4_PHY_ADDR       3
 425 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 426 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 427 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 428 #define CONFIG_SYS_UEC4_TX_CLK          QE_CLK16 /* CLK16 for RMII */
 429 #define CONFIG_SYS_UEC4_ETH_TYPE        FAST_ETH
 430 #define CONFIG_SYS_UEC4_PHY_ADDR        0xB     /* 0xB for RMII */
 431 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 432 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 433 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 434 #endif /* CONFIG_UEC_ETH4 */
 435
 436 #undef CONFIG_UEC_ETH6         /* GETH6 */
 437 #define CONFIG_HAS_ETH5
 438
 439 #ifdef CONFIG_UEC_ETH6
 440 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
 441 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
 442 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 443 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 444 #define CONFIG_SYS_UEC6_PHY_ADDR       4
 445 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 446 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 447 #endif /* CONFIG_UEC_ETH6 */
 448
 449 #undef CONFIG_UEC_ETH8         /* GETH8 */
 450 #define CONFIG_HAS_ETH7
 451
 452 #ifdef CONFIG_UEC_ETH8
 453 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
 454 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
 455 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 456 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 457 #define CONFIG_SYS_UEC8_PHY_ADDR       6
 458 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
 459 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 460 #endif /* CONFIG_UEC_ETH8 */
 461
 462 #endif /* CONFIG_QE */
 463
 464 #if defined(CONFIG_PCI)
 465
 466 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 467
 468 #undef CONFIG_EEPRO100
 469 #undef CONFIG_TULIP
 470 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
 471
 472 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 473
 474 #endif  /* CONFIG_PCI */
 475
 476 /*
 477  * Environment
 478  */
 479 #if defined(CONFIG_SYS_RAMBOOT)
 480 #if defined(CONFIG_RAMBOOT_NAND)
 481 #define CONFIG_ENV_IS_IN_NAND   1
 482 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 483 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 484 #endif
 485 #else
 486 #define CONFIG_ENV_IS_IN_FLASH  1
 487 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 488 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 489 #define CONFIG_ENV_SIZE         0x2000
 490 #endif
 491
 492 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 493 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 494
 495 /* QE microcode/firmware address */
 496 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 497 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xfff00000
 498
 499 /*
 500  * BOOTP options
 501  */
 502 #define CONFIG_BOOTP_BOOTFILESIZE
 503 #define CONFIG_BOOTP_BOOTPATH
 504 #define CONFIG_BOOTP_GATEWAY
 505 #define CONFIG_BOOTP_HOSTNAME
 506
 507
 508 /*
 509  * Command line configuration.
 510  */
 511 #include <config_cmd_default.h>
 512
 513 #define CONFIG_CMD_PING
 514 #define CONFIG_CMD_I2C
 515 #define CONFIG_CMD_MII
 516 #define CONFIG_CMD_ELF
 517 #define CONFIG_CMD_IRQ
 518 #define CONFIG_CMD_SETEXPR
 519 #define CONFIG_CMD_REGINFO
 520
 521 #if defined(CONFIG_PCI)
 522     #define CONFIG_CMD_PCI
 523 #endif
 524
 525
 526 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 527
 528 #define CONFIG_MMC     1
 529
 530 #ifdef CONFIG_MMC
 531 #define CONFIG_FSL_ESDHC
 532 #define CONFIG_FSL_ESDHC_PIN_MUX
 533 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 534 #define CONFIG_CMD_MMC
 535 #define CONFIG_GENERIC_MMC
 536 #define CONFIG_CMD_EXT2
 537 #define CONFIG_CMD_FAT
 538 #define CONFIG_DOS_PARTITION
 539 #endif
 540
 541 /*
 542  * Miscellaneous configurable options
 543  */
 544 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 545 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 546 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 547 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 548 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 549 #if defined(CONFIG_CMD_KGDB)
 550 #define CONFIG_SYS_CBSIZE       2048            /* Console I/O Buffer Size */
 551 #else
 552 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 553 #endif
 554 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 555                                                 /* Print Buffer Size */
 556 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
 557 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 558                                                 /* Boot Argument Buffer Size */
 559 #define CONFIG_SYS_HZ   1000            /* decrementer freq: 1ms ticks */
 560
 561 /*
 562  * For booting Linux, the board info and command line data
 563  * have to be in the first 64 MB of memory, since this is
 564  * the maximum mapped by the Linux kernel during initialization.
 565  */
 566 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux*/
 567 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 568
 569 #if defined(CONFIG_CMD_KGDB)
 570 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 571 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 572 #endif
 573
 574 /*
 575  * Environment Configuration
 576  */
 577 #define CONFIG_HOSTNAME mpc8569mds
 578 #define CONFIG_ROOTPATH  "/nfsroot"
 579 #define CONFIG_BOOTFILE  "your.uImage"
 580
 581 #define CONFIG_SERVERIP  192.168.1.1
 582 #define CONFIG_GATEWAYIP 192.168.1.1
 583 #define CONFIG_NETMASK   255.255.255.0
 584
 585 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 586
 587 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 588 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 589
 590 #define CONFIG_BAUDRATE 115200
 591
 592 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 593         "netdev=eth0\0"                                                 \
 594         "consoledev=ttyS0\0"                                            \
 595         "ramdiskaddr=600000\0"                                          \
 596         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 597         "fdtaddr=400000\0"                                              \
 598         "fdtfile=your.fdt.dtb\0"                                        \
 599         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 600         "nfsroot=$serverip:$rootpath "                                  \
 601         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 602         "console=$consoledev,$baudrate $othbootargs\0"                  \
 603         "ramargs=setenv bootargs root=/dev/ram rw "                     \
 604         "console=$consoledev,$baudrate $othbootargs\0"                  \
 605
 606 #define CONFIG_NFSBOOTCOMMAND                                           \
 607         "run nfsargs;"                                                  \
 608         "tftp $loadaddr $bootfile;"                                     \
 609         "tftp $fdtaddr $fdtfile;"                                       \
 610         "bootm $loadaddr - $fdtaddr"
 611
 612 #define CONFIG_RAMBOOTCOMMAND                                           \
 613         "run ramargs;"                                                  \
 614         "tftp $ramdiskaddr $ramdiskfile;"                               \
 615         "tftp $loadaddr $bootfile;"                                     \
 616         "bootm $loadaddr $ramdiskaddr"
 617
 618 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 619
 620 #endif  /* __CONFIG_H */