include/configs/MPC8572DS.h

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8572ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8572          1
  35 #define CONFIG_MPC8572DS        1
  36 #define CONFIG_MP               1       /* support multiple processors */
  37 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  38
  39 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  40 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  41 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  42 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  44 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  45
  46 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  47
  48 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50
  51 /*
  52  * When initializing flash, if we cannot find the manufacturer ID,
  53  * assume this is the AMD flash associated with the CDS board.
  54  * This allows booting from a promjet.
  55  */
  56 #define CONFIG_ASSUME_AMD_FLASH
  57
  58 #ifndef __ASSEMBLY__
  59 extern unsigned long get_board_sys_clk(unsigned long dummy);
  60 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  61 #endif
  62 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  63 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  64 #define CONFIG_ICS307_REFCLK_HZ 33333333  /* ICS307 clock chip ref freq */
  65 #define CONFIG_GET_CLK_FROM_ICS307        /* decode sysclk and ddrclk freq
  66                                              from ICS307 instead of switches */
  67
  68 /*
  69  * These can be toggled for performance analysis, otherwise use default.
  70  */
  71 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  72 #define CONFIG_BTB                      /* toggle branch predition */
  73 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  74
  75 #define CONFIG_ENABLE_36BIT_PHYS        1
  76
  77 #define CFG_MEMTEST_START       0x00000000      /* memtest works on */
  78 #define CFG_MEMTEST_END         0x7fffffff
  79 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  80
  81 /*
  82  * Base addresses -- Note these are effective addresses where the
  83  * actual resources get mapped (not physical addresses)
  84  */
  85 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  86 #define CFG_CCSRBAR             0xffe00000      /* relocated CCSRBAR */
  87 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
  88 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  89
  90 #define CFG_PCIE3_ADDR          (CFG_CCSRBAR+0x8000)
  91 #define CFG_PCIE2_ADDR          (CFG_CCSRBAR+0x9000)
  92 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
  93
  94 /* DDR Setup */
  95 #define CONFIG_FSL_DDR2
  96 #undef CONFIG_FSL_DDR_INTERACTIVE
  97 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  98 #define CONFIG_DDR_SPD
  99 #undef CONFIG_DDR_DLL
 100
 101 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 102
 103 #define CFG_DDR_SDRAM_BASE      0x00000000
 104 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 105
 106 #define CONFIG_NUM_DDR_CONTROLLERS      2
 107 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 108 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 109
 110 /* I2C addresses of SPD EEPROMs */
 111 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 112 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 1 DIMM 0 */
 113
 114 /* These are used when DDR doesn't use SPD.  */
 115 #define CFG_SDRAM_SIZE          256             /* DDR is 256MB */
 116 #define CFG_DDR_CS0_BNDS        0x0000001F
 117 #define CFG_DDR_CS0_CONFIG      0x80010102      /* Enable, no interleaving */
 118 #define CFG_DDR_TIMING_3        0x00000000
 119 #define CFG_DDR_TIMING_0        0x00260802
 120 #define CFG_DDR_TIMING_1        0x3935d322
 121 #define CFG_DDR_TIMING_2        0x14904cc8
 122 #define CFG_DDR_MODE_1          0x00480432
 123 #define CFG_DDR_MODE_2          0x00000000
 124 #define CFG_DDR_INTERVAL        0x06180100
 125 #define CFG_DDR_DATA_INIT       0xdeadbeef
 126 #define CFG_DDR_CLK_CTRL        0x03800000
 127 #define CFG_DDR_OCD_CTRL        0x00000000
 128 #define CFG_DDR_OCD_STATUS      0x00000000
 129 #define CFG_DDR_CONTROL         0xC3008000      /* Type = DDR2 */
 130 #define CFG_DDR_CONTROL2        0x04400010
 131
 132 #define CFG_DDR_ERR_INT_EN      0x0000000d
 133 #define CFG_DDR_ERR_DIS         0x00000000
 134 #define CFG_DDR_SBE             0x00010000
 135
 136 /*
 137  * FIXME: Not used in fixed_sdram function
 138  */
 139 #define CFG_DDR_MODE            0x00000022
 140 #define CFG_DDR_CS1_BNDS        0x00000000
 141 #define CFG_DDR_CS2_BNDS        0x00000FFF      /* Not done */
 142 #define CFG_DDR_CS3_BNDS        0x00000FFF      /* Not done */
 143 #define CFG_DDR_CS4_BNDS        0x00000FFF      /* Not done */
 144 #define CFG_DDR_CS5_BNDS        0x00000FFF      /* Not done */
 145
 146 /*
 147  * Make sure required options are set
 148  */
 149 #ifndef CONFIG_SPD_EEPROM
 150 #error ("CONFIG_SPD_EEPROM is required")
 151 #endif
 152
 153 #undef CONFIG_CLOCKS_IN_MHZ
 154
 155 /*
 156  * Memory map
 157  *
 158  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 159  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 160  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 161  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 162  *
 163  * Localbus cacheable (TBD)
 164  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 165  *
 166  * Localbus non-cacheable
 167  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 168  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 169  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 170  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 171  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 172  */
 173
 174 /*
 175  * Local Bus Definitions
 176  */
 177 #define CFG_FLASH_BASE          0xe0000000      /* start of FLASH 128M */
 178
 179 #define CFG_BR0_PRELIM          0xe8001001
 180 #define CFG_OR0_PRELIM          0xf8000ff7
 181
 182 #define CFG_BR1_PRELIM          0xe0001001
 183 #define CFG_OR1_PRELIM          0xf8000ff7
 184
 185 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE}
 186 #define CFG_FLASH_QUIET_TEST
 187 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 188
 189 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 190 #define CFG_MAX_FLASH_SECT      1024            /* sectors per device */
 191 #undef  CFG_FLASH_CHECKSUM
 192 #define CFG_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
 193 #define CFG_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
 194
 195 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 196
 197 #define CONFIG_FLASH_CFI_DRIVER
 198 #define CFG_FLASH_CFI
 199 #define CFG_FLASH_EMPTY_INFO
 200 #define CFG_FLASH_AMD_CHECK_DQ7
 201
 202 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 203
 204 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 205 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 206
 207 #define CFG_BR3_PRELIM  (PIXIS_BASE | 0x0801)   /* port size 8bit */
 208 #define CFG_OR3_PRELIM          0xffffeff7      /* 32KB but only 4k mapped */
 209
 210 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 211 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 212 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 213 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 214 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 215 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 216 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 217 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 218 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 219 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 220 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 221 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 222 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 223 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 224 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 225 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 226 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 227 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 228 #define PIXIS_VSYSCLK0          0x1C    /* VELA SYSCLK0 Register */
 229 #define PIXIS_VSYSCLK1          0x1D    /* VELA SYSCLK1 Register */
 230 #define PIXIS_VSYSCLK2          0x1E    /* VELA SYSCLK2 Register */
 231 #define PIXIS_VDDRCLK0          0x1F    /* VELA DDRCLK0 Register */
 232 #define PIXIS_VDDRCLK1          0x20    /* VELA DDRCLK1 Register */
 233 #define PIXIS_VDDRCLK2          0x21    /* VELA DDRCLK2 Register */
 234 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 235 #define PIXIS_LED               0x25    /* LED Register */
 236
 237 /* old pixis referenced names */
 238 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 239 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 240 #define CFG_PIXIS_VBOOT_MASK    0xc0
 241
 242 /* define to use L1 as initial stack */
 243 #define CONFIG_L1_INIT_RAM
 244 #define CFG_INIT_RAM_LOCK       1
 245 #define CFG_INIT_RAM_ADDR       0xffd00000      /* Initial L1 address */
 246 #define CFG_INIT_RAM_END        0x00004000      /* End of used area in RAM */
 247
 248 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data */
 249 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 250 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 251
 252 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 253 #define CFG_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc */
 254
 255 /* Serial Port - controlled on board with jumper J8
 256  * open - index 2
 257  * shorted - index 1
 258  */
 259 #define CONFIG_CONS_INDEX       1
 260 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 261 #define CFG_NS16550
 262 #define CFG_NS16550_SERIAL
 263 #define CFG_NS16550_REG_SIZE    1
 264 #define CFG_NS16550_CLK         get_bus_freq(0)
 265
 266 #define CFG_BAUDRATE_TABLE      \
 267         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 268
 269 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 270 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 271
 272 /* Use the HUSH parser */
 273 #define CFG_HUSH_PARSER
 274 #ifdef  CFG_HUSH_PARSER
 275 #define CFG_PROMPT_HUSH_PS2 "> "
 276 #endif
 277
 278 /*
 279  * Pass open firmware flat tree
 280  */
 281 #define CONFIG_OF_LIBFDT                1
 282 #define CONFIG_OF_BOARD_SETUP           1
 283 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 284
 285 #define CFG_64BIT_VSPRINTF      1
 286 #define CFG_64BIT_STRTOUL       1
 287
 288 /* new uImage format support */
 289 #define CONFIG_FIT              1
 290 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 291
 292 /* I2C */
 293 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 294 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 295 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 296 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 297 #define CFG_I2C_EEPROM_ADDR     0x57
 298 #define CFG_I2C_SLAVE           0x7F
 299 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 300 #define CFG_I2C_OFFSET          0x3100
 301
 302 /*
 303  * General PCI
 304  * Memory space is mapped 1-1, but I/O space must start from 0.
 305  */
 306
 307 /* PCI view of System Memory */
 308 #define CFG_PCI_MEMORY_BUS      0x00000000
 309 #define CFG_PCI_MEMORY_PHYS     0x00000000
 310 #define CFG_PCI_MEMORY_SIZE     0x80000000
 311
 312 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 313 #define CFG_PCIE3_MEM_BASE      0x80000000
 314 #define CFG_PCIE3_MEM_PHYS      CFG_PCIE3_MEM_BASE
 315 #define CFG_PCIE3_MEM_SIZE      0x20000000      /* 512M */
 316 #define CFG_PCIE3_IO_BASE       0x00000000
 317 #define CFG_PCIE3_IO_PHYS       0xffc00000
 318 #define CFG_PCIE3_IO_SIZE       0x00010000      /* 64k */
 319
 320 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 321 #define CFG_PCIE2_MEM_BASE      0xa0000000
 322 #define CFG_PCIE2_MEM_PHYS      CFG_PCIE2_MEM_BASE
 323 #define CFG_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 324 #define CFG_PCIE2_IO_BASE       0x00000000
 325 #define CFG_PCIE2_IO_PHYS       0xffc10000
 326 #define CFG_PCIE2_IO_SIZE       0x00010000      /* 64k */
 327
 328 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 329 #define CFG_PCIE1_MEM_BASE      0xc0000000
 330 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 331 #define CFG_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 332 #define CFG_PCIE1_IO_BASE       0x00000000
 333 #define CFG_PCIE1_IO_PHYS       0xffc20000
 334 #define CFG_PCIE1_IO_SIZE       0x00010000      /* 64k */
 335
 336 #if defined(CONFIG_PCI)
 337
 338 /*PCIE video card used*/
 339 #define VIDEO_IO_OFFSET         CFG_PCIE1_IO_PHYS
 340
 341 /* video */
 342 #define CONFIG_VIDEO
 343
 344 #if defined(CONFIG_VIDEO)
 345 #define CONFIG_BIOSEMU
 346 #define CONFIG_CFB_CONSOLE
 347 #define CONFIG_VIDEO_SW_CURSOR
 348 #define CONFIG_VGA_AS_SINGLE_DEVICE
 349 #define CONFIG_ATI_RADEON_FB
 350 #define CONFIG_VIDEO_LOGO
 351 /*#define CONFIG_CONSOLE_CURSOR*/
 352 #define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 353 #endif
 354
 355 #define CONFIG_NET_MULTI
 356 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 357
 358 #undef CONFIG_EEPRO100
 359 #undef CONFIG_TULIP
 360 #undef CONFIG_RTL8139
 361
 362 #ifdef CONFIG_RTL8139
 363 /* This macro is used by RTL8139 but not defined in PPC architecture */
 364 #define KSEG1ADDR(x)            (x)
 365 #define _IO_BASE        0x00000000
 366 #endif
 367
 368 #ifndef CONFIG_PCI_PNP
 369         #define PCI_ENET0_IOADDR        CFG_PCIE3_IO_BASE
 370         #define PCI_ENET0_MEMADDR       CFG_PCIE3_IO_BASE
 371         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 372 #endif
 373
 374 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 375 #define CONFIG_DOS_PARTITION
 376 #define CONFIG_SCSI_AHCI
 377
 378 #ifdef CONFIG_SCSI_AHCI
 379 #define CONFIG_SATA_ULI5288
 380 #define CFG_SCSI_MAX_SCSI_ID    4
 381 #define CFG_SCSI_MAX_LUN        1
 382 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 383 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 384 #endif /* SCSI */
 385
 386 #endif  /* CONFIG_PCI */
 387
 388
 389 #if defined(CONFIG_TSEC_ENET)
 390
 391 #ifndef CONFIG_NET_MULTI
 392 #define CONFIG_NET_MULTI        1
 393 #endif
 394
 395 #define CONFIG_MII              1       /* MII PHY management */
 396 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 397 #define CONFIG_TSEC1    1
 398 #define CONFIG_TSEC1_NAME       "eTSEC1"
 399 #define CONFIG_TSEC2    1
 400 #define CONFIG_TSEC2_NAME       "eTSEC2"
 401 #define CONFIG_TSEC3    1
 402 #define CONFIG_TSEC3_NAME       "eTSEC3"
 403 #define CONFIG_TSEC4    1
 404 #define CONFIG_TSEC4_NAME       "eTSEC4"
 405
 406 #define TSEC1_PHY_ADDR          0
 407 #define TSEC2_PHY_ADDR          1
 408 #define TSEC3_PHY_ADDR          2
 409 #define TSEC4_PHY_ADDR          3
 410
 411 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 412 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 413 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 414 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 415
 416 #define TSEC1_PHYIDX            0
 417 #define TSEC2_PHYIDX            0
 418 #define TSEC3_PHYIDX            0
 419 #define TSEC4_PHYIDX            0
 420
 421 #define CONFIG_ETHPRIME         "eTSEC1"
 422
 423 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 424 #endif  /* CONFIG_TSEC_ENET */
 425
 426 /*
 427  * Environment
 428  */
 429 #define CONFIG_ENV_IS_IN_FLASH  1
 430 #if CFG_MONITOR_BASE > 0xfff80000
 431 #define CONFIG_ENV_ADDR         0xfff80000
 432 #else
 433 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE + 0x70000)
 434 #endif
 435 #define CONFIG_ENV_SIZE         0x2000
 436 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 437
 438 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 439 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 440
 441 /*
 442  * Command line configuration.
 443  */
 444 #include <config_cmd_default.h>
 445
 446 #define CONFIG_CMD_IRQ
 447 #define CONFIG_CMD_PING
 448 #define CONFIG_CMD_I2C
 449 #define CONFIG_CMD_MII
 450 #define CONFIG_CMD_ELF
 451
 452 #if defined(CONFIG_PCI)
 453 #define CONFIG_CMD_PCI
 454 #define CONFIG_CMD_BEDBUG
 455 #define CONFIG_CMD_NET
 456 #define CONFIG_CMD_SCSI
 457 #define CONFIG_CMD_EXT2
 458 #endif
 459
 460 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 461
 462 /*
 463  * Miscellaneous configurable options
 464  */
 465 #define CFG_LONGHELP                    /* undef to save memory */
 466 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 467 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 468 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 469 #if defined(CONFIG_CMD_KGDB)
 470 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 471 #else
 472 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 473 #endif
 474 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 475 #define CFG_MAXARGS     16              /* max number of command args */
 476 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 477 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 478
 479 /*
 480  * For booting Linux, the board info and command line data
 481  * have to be in the first 8 MB of memory, since this is
 482  * the maximum mapped by the Linux kernel during initialization.
 483  */
 484 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 485
 486 /*
 487  * Internal Definitions
 488  *
 489  * Boot Flags
 490  */
 491 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 492 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 493
 494 #if defined(CONFIG_CMD_KGDB)
 495 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 496 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 497 #endif
 498
 499 /*
 500  * Environment Configuration
 501  */
 502
 503 /* The mac addresses for all ethernet interface */
 504 #if defined(CONFIG_TSEC_ENET)
 505 #define CONFIG_HAS_ETH0
 506 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 507 #define CONFIG_HAS_ETH1
 508 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 509 #define CONFIG_HAS_ETH2
 510 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 511 #define CONFIG_HAS_ETH3
 512 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 513 #endif
 514
 515 #define CONFIG_IPADDR           192.168.1.254
 516
 517 #define CONFIG_HOSTNAME         unknown
 518 #define CONFIG_ROOTPATH         /opt/nfsroot
 519 #define CONFIG_BOOTFILE         uImage
 520 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 521
 522 #define CONFIG_SERVERIP         192.168.1.1
 523 #define CONFIG_GATEWAYIP        192.168.1.1
 524 #define CONFIG_NETMASK          255.255.255.0
 525
 526 /* default location for tftp and bootm */
 527 #define CONFIG_LOADADDR         1000000
 528
 529 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 530 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 531
 532 #define CONFIG_BAUDRATE 115200
 533
 534 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 535  "netdev=eth0\0"                                                \
 536  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 537  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 538         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 539         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 540         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 541         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 542         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 543  "consoledev=ttyS0\0"                           \
 544  "ramdiskaddr=2000000\0"                        \
 545  "ramdiskfile=8572ds/ramdisk.uboot\0"           \
 546  "fdtaddr=c00000\0"                             \
 547  "fdtfile=8572ds/mpc8572ds.dtb\0"               \
 548  "bdev=sda3\0"
 549
 550 #define CONFIG_HDBOOT                           \
 551  "setenv bootargs root=/dev/$bdev rw "          \
 552  "console=$consoledev,$baudrate $othbootargs;"  \
 553  "tftp $loadaddr $bootfile;"                    \
 554  "tftp $fdtaddr $fdtfile;"                      \
 555  "bootm $loadaddr - $fdtaddr"
 556
 557 #define CONFIG_NFSBOOTCOMMAND           \
 558  "setenv bootargs root=/dev/nfs rw "    \
 559  "nfsroot=$serverip:$rootpath "         \
 560  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 561  "console=$consoledev,$baudrate $othbootargs;"  \
 562  "tftp $loadaddr $bootfile;"            \
 563  "tftp $fdtaddr $fdtfile;"              \
 564  "bootm $loadaddr - $fdtaddr"
 565
 566 #define CONFIG_RAMBOOTCOMMAND           \
 567  "setenv bootargs root=/dev/ram rw "    \
 568  "console=$consoledev,$baudrate $othbootargs;"  \
 569  "tftp $ramdiskaddr $ramdiskfile;"      \
 570  "tftp $loadaddr $bootfile;"            \
 571  "tftp $fdtaddr $fdtfile;"              \
 572  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 573
 574 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 575
 576 #endif  /* __CONFIG_H */