include/configs/MPC8572DS.h

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8572ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8572          1
  35 #define CONFIG_MPC8572DS        1
  36 #define CONFIG_MP               1       /* support multiple processors */
  37 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  38
  39 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  40 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  41 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  42 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  44 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  45 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  46
  47 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  48
  49 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  50 #define CONFIG_ENV_OVERWRITE
  51
  52 /*
  53  * When initializing flash, if we cannot find the manufacturer ID,
  54  * assume this is the AMD flash associated with the CDS board.
  55  * This allows booting from a promjet.
  56  */
  57 #define CONFIG_ASSUME_AMD_FLASH
  58
  59 #ifndef __ASSEMBLY__
  60 extern unsigned long get_board_sys_clk(unsigned long dummy);
  61 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  62 #endif
  63 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  64 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  65 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  66 #define CONFIG_GET_CLK_FROM_ICS307        /* decode sysclk and ddrclk freq
  67                                              from ICS307 instead of switches */
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  75
  76 #define CONFIG_ENABLE_36BIT_PHYS        1
  77
  78 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  79 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
  80 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  81
  82 /*
  83  * Base addresses -- Note these are effective addresses where the
  84  * actual resources get mapped (not physical addresses)
  85  */
  86 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  87 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  89 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  90
  91 #define CONFIG_SYS_PCIE3_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
  92 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
  93 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
  94
  95 /* DDR Setup */
  96 #define CONFIG_FSL_DDR2
  97 #undef CONFIG_FSL_DDR_INTERACTIVE
  98 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  99 #define CONFIG_DDR_SPD
 100 #undef CONFIG_DDR_DLL
 101
 102 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 103
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 106
 107 #define CONFIG_NUM_DDR_CONTROLLERS      2
 108 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 109 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 110
 111 /* I2C addresses of SPD EEPROMs */
 112 #define CONFIG_SYS_SPD_BUS_NUM          1       /* SPD EEPROMS locate on I2C bus 1 */
 113 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 114 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 1 DIMM 0 */
 115
 116 /* These are used when DDR doesn't use SPD.  */
 117 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 119 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 121 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 122 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 123 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 124 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 125 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 126 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 127 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 128 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 129 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 130 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 131 #define CONFIG_SYS_DDR_CONTROL          0xC3008000      /* Type = DDR2 */
 132 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 133
 134 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 135 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 136 #define CONFIG_SYS_DDR_SBE              0x00010000
 137
 138 /*
 139  * Make sure required options are set
 140  */
 141 #ifndef CONFIG_SPD_EEPROM
 142 #error ("CONFIG_SPD_EEPROM is required")
 143 #endif
 144
 145 #undef CONFIG_CLOCKS_IN_MHZ
 146
 147 /*
 148  * Memory map
 149  *
 150  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 151  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 152  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 153  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 154  *
 155  * Localbus cacheable (TBD)
 156  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 157  *
 158  * Localbus non-cacheable
 159  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 160  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 161  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 162  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 163  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 164  */
 165
 166 /*
 167  * Local Bus Definitions
 168  */
 169 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 170
 171 #define CONFIG_SYS_BR0_PRELIM           0xe8001001
 172 #define CONFIG_SYS_OR0_PRELIM           0xf8000ff7
 173
 174 #define CONFIG_SYS_BR1_PRELIM           0xe0001001
 175 #define CONFIG_SYS_OR1_PRELIM           0xf8000ff7
 176
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
 178 #define CONFIG_SYS_FLASH_QUIET_TEST
 179 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 180
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 182 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 183 #undef  CONFIG_SYS_FLASH_CHECKSUM
 184 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 185 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 186
 187 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 188
 189 #define CONFIG_FLASH_CFI_DRIVER
 190 #define CONFIG_SYS_FLASH_CFI
 191 #define CONFIG_SYS_FLASH_EMPTY_INFO
 192 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 193
 194 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 195
 196 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 197 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 198
 199 #define CONFIG_SYS_BR3_PRELIM   (PIXIS_BASE | 0x0801)   /* port size 8bit */
 200 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
 201
 202 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 203 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 204 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 205 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 206 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 207 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 208 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 209 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 210 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 211 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 212 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 213 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 214 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 215 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 216 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 217 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 218 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 219 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 220 #define PIXIS_VSYSCLK0          0x1C    /* VELA SYSCLK0 Register */
 221 #define PIXIS_VSYSCLK1          0x1D    /* VELA SYSCLK1 Register */
 222 #define PIXIS_VSYSCLK2          0x1E    /* VELA SYSCLK2 Register */
 223 #define PIXIS_VDDRCLK0          0x1F    /* VELA DDRCLK0 Register */
 224 #define PIXIS_VDDRCLK1          0x20    /* VELA DDRCLK1 Register */
 225 #define PIXIS_VDDRCLK2          0x21    /* VELA DDRCLK2 Register */
 226 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 227 #define PIXIS_LED               0x25    /* LED Register */
 228
 229 /* old pixis referenced names */
 230 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 231 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 232 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xc0
 233 #define PIXIS_VSPEED2_TSEC1SER  0x8
 234 #define PIXIS_VSPEED2_TSEC2SER  0x4
 235 #define PIXIS_VSPEED2_TSEC3SER  0x2
 236 #define PIXIS_VSPEED2_TSEC4SER  0x1
 237 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 238 #define PIXIS_VCFGEN1_TSEC2SER  0x20
 239 #define PIXIS_VCFGEN1_TSEC3SER  0x20
 240 #define PIXIS_VCFGEN1_TSEC4SER  0x20
 241 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER \
 242                                         | PIXIS_VSPEED2_TSEC2SER \
 243                                         | PIXIS_VSPEED2_TSEC3SER \
 244                                         | PIXIS_VSPEED2_TSEC4SER)
 245 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER \
 246                                         | PIXIS_VCFGEN1_TSEC2SER \
 247                                         | PIXIS_VCFGEN1_TSEC3SER \
 248                                         | PIXIS_VCFGEN1_TSEC4SER)
 249
 250 /* define to use L1 as initial stack */
 251 #define CONFIG_L1_INIT_RAM
 252 #define CONFIG_SYS_INIT_RAM_LOCK        1
 253 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 254 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 255
 256 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 257 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 258 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 259
 260 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 261 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 262
 263 /* Serial Port - controlled on board with jumper J8
 264  * open - index 2
 265  * shorted - index 1
 266  */
 267 #define CONFIG_CONS_INDEX       1
 268 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 269 #define CONFIG_SYS_NS16550
 270 #define CONFIG_SYS_NS16550_SERIAL
 271 #define CONFIG_SYS_NS16550_REG_SIZE     1
 272 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 273
 274 #define CONFIG_SYS_BAUDRATE_TABLE       \
 275         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 276
 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 279
 280 /* Use the HUSH parser */
 281 #define CONFIG_SYS_HUSH_PARSER
 282 #ifdef  CONFIG_SYS_HUSH_PARSER
 283 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 284 #endif
 285
 286 /*
 287  * Pass open firmware flat tree
 288  */
 289 #define CONFIG_OF_LIBFDT                1
 290 #define CONFIG_OF_BOARD_SETUP           1
 291 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 292
 293 #define CONFIG_SYS_64BIT_VSPRINTF       1
 294 #define CONFIG_SYS_64BIT_STRTOUL        1
 295
 296 /* new uImage format support */
 297 #define CONFIG_FIT              1
 298 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 299
 300 /* I2C */
 301 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 302 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 303 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 304 #define CONFIG_I2C_MULTI_BUS
 305 #define CONFIG_I2C_CMD_TREE
 306 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 307 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 308 #define CONFIG_SYS_I2C_SLAVE            0x7F
 309 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
 310 #define CONFIG_SYS_I2C_OFFSET           0x3000
 311 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 312
 313 /*
 314  * I2C2 EEPROM
 315  */
 316 #define CONFIG_ID_EEPROM
 317 #ifdef CONFIG_ID_EEPROM
 318 #define CONFIG_SYS_I2C_EEPROM_NXID
 319 #endif
 320 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 321 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 322 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 323
 324 /*
 325  * General PCI
 326  * Memory space is mapped 1-1, but I/O space must start from 0.
 327  */
 328
 329 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 330 #define CONFIG_SYS_PCIE3_MEM_BASE       0x80000000
 331 #define CONFIG_SYS_PCIE3_MEM_PHYS       CONFIG_SYS_PCIE3_MEM_BASE
 332 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 333 #define CONFIG_SYS_PCIE3_IO_BASE        0x00000000
 334 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 335 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 336
 337 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 338 #define CONFIG_SYS_PCIE2_MEM_BASE       0xa0000000
 339 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BASE
 340 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 341 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 342 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 343 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 344
 345 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 346 #define CONFIG_SYS_PCIE1_MEM_BASE       0xc0000000
 347 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 348 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 349 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 350 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 351 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 352
 353 #if defined(CONFIG_PCI)
 354
 355 /*PCIE video card used*/
 356 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_PHYS
 357
 358 /* video */
 359 #define CONFIG_VIDEO
 360
 361 #if defined(CONFIG_VIDEO)
 362 #define CONFIG_BIOSEMU
 363 #define CONFIG_CFB_CONSOLE
 364 #define CONFIG_VIDEO_SW_CURSOR
 365 #define CONFIG_VGA_AS_SINGLE_DEVICE
 366 #define CONFIG_ATI_RADEON_FB
 367 #define CONFIG_VIDEO_LOGO
 368 /*#define CONFIG_CONSOLE_CURSOR*/
 369 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 370 #endif
 371
 372 #define CONFIG_NET_MULTI
 373 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 374
 375 #undef CONFIG_EEPRO100
 376 #undef CONFIG_TULIP
 377 #undef CONFIG_RTL8139
 378
 379 #ifdef CONFIG_RTL8139
 380 /* This macro is used by RTL8139 but not defined in PPC architecture */
 381 #define KSEG1ADDR(x)            (x)
 382 #define _IO_BASE        0x00000000
 383 #endif
 384
 385 #ifndef CONFIG_PCI_PNP
 386         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BASE
 387         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BASE
 388         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 389 #endif
 390
 391 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 392 #define CONFIG_DOS_PARTITION
 393 #define CONFIG_SCSI_AHCI
 394
 395 #ifdef CONFIG_SCSI_AHCI
 396 #define CONFIG_SATA_ULI5288
 397 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 398 #define CONFIG_SYS_SCSI_MAX_LUN 1
 399 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 400 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 401 #endif /* SCSI */
 402
 403 #endif  /* CONFIG_PCI */
 404
 405
 406 #if defined(CONFIG_TSEC_ENET)
 407
 408 #ifndef CONFIG_NET_MULTI
 409 #define CONFIG_NET_MULTI        1
 410 #endif
 411
 412 #define CONFIG_MII              1       /* MII PHY management */
 413 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 414 #define CONFIG_TSEC1    1
 415 #define CONFIG_TSEC1_NAME       "eTSEC1"
 416 #define CONFIG_TSEC2    1
 417 #define CONFIG_TSEC2_NAME       "eTSEC2"
 418 #define CONFIG_TSEC3    1
 419 #define CONFIG_TSEC3_NAME       "eTSEC3"
 420 #define CONFIG_TSEC4    1
 421 #define CONFIG_TSEC4_NAME       "eTSEC4"
 422
 423 #define CONFIG_PIXIS_SGMII_CMD
 424 #define CONFIG_FSL_SGMII_RISER  1
 425 #define SGMII_RISER_PHY_OFFSET  0x1c
 426
 427 #ifdef CONFIG_FSL_SGMII_RISER
 428 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
 429 #endif
 430
 431 #define TSEC1_PHY_ADDR          0
 432 #define TSEC2_PHY_ADDR          1
 433 #define TSEC3_PHY_ADDR          2
 434 #define TSEC4_PHY_ADDR          3
 435
 436 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 437 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 438 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 439 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 440
 441 #define TSEC1_PHYIDX            0
 442 #define TSEC2_PHYIDX            0
 443 #define TSEC3_PHYIDX            0
 444 #define TSEC4_PHYIDX            0
 445
 446 #define CONFIG_ETHPRIME         "eTSEC1"
 447
 448 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 449 #endif  /* CONFIG_TSEC_ENET */
 450
 451 /*
 452  * Environment
 453  */
 454 #define CONFIG_ENV_IS_IN_FLASH  1
 455 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 456 #define CONFIG_ENV_ADDR         0xfff80000
 457 #else
 458 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x70000)
 459 #endif
 460 #define CONFIG_ENV_SIZE         0x2000
 461 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 462
 463 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 465
 466 /*
 467  * Command line configuration.
 468  */
 469 #include <config_cmd_default.h>
 470
 471 #define CONFIG_CMD_IRQ
 472 #define CONFIG_CMD_PING
 473 #define CONFIG_CMD_I2C
 474 #define CONFIG_CMD_MII
 475 #define CONFIG_CMD_ELF
 476 #define CONFIG_CMD_IRQ
 477 #define CONFIG_CMD_SETEXPR
 478
 479 #if defined(CONFIG_PCI)
 480 #define CONFIG_CMD_PCI
 481 #define CONFIG_CMD_BEDBUG
 482 #define CONFIG_CMD_NET
 483 #define CONFIG_CMD_SCSI
 484 #define CONFIG_CMD_EXT2
 485 #endif
 486
 487 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 488
 489 /*
 490  * Miscellaneous configurable options
 491  */
 492 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 493 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 494 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 495 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 496 #if defined(CONFIG_CMD_KGDB)
 497 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 498 #else
 499 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 500 #endif
 501 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 502 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 503 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 504 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 505
 506 /*
 507  * For booting Linux, the board info and command line data
 508  * have to be in the first 8 MB of memory, since this is
 509  * the maximum mapped by the Linux kernel during initialization.
 510  */
 511 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 512
 513 /*
 514  * Internal Definitions
 515  *
 516  * Boot Flags
 517  */
 518 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 519 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 520
 521 #if defined(CONFIG_CMD_KGDB)
 522 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 523 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 524 #endif
 525
 526 /*
 527  * Environment Configuration
 528  */
 529
 530 /* The mac addresses for all ethernet interface */
 531 #if defined(CONFIG_TSEC_ENET)
 532 #define CONFIG_HAS_ETH0
 533 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 534 #define CONFIG_HAS_ETH1
 535 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 536 #define CONFIG_HAS_ETH2
 537 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 538 #define CONFIG_HAS_ETH3
 539 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 540 #endif
 541
 542 #define CONFIG_IPADDR           192.168.1.254
 543
 544 #define CONFIG_HOSTNAME         unknown
 545 #define CONFIG_ROOTPATH         /opt/nfsroot
 546 #define CONFIG_BOOTFILE         uImage
 547 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 548
 549 #define CONFIG_SERVERIP         192.168.1.1
 550 #define CONFIG_GATEWAYIP        192.168.1.1
 551 #define CONFIG_NETMASK          255.255.255.0
 552
 553 /* default location for tftp and bootm */
 554 #define CONFIG_LOADADDR         1000000
 555
 556 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 557 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 558
 559 #define CONFIG_BAUDRATE 115200
 560
 561 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 562  "memctl_intlv_ctl=2\0"                                         \
 563  "netdev=eth0\0"                                                \
 564  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 565  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 566         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 567         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 568         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 569         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 570         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 571  "consoledev=ttyS0\0"                           \
 572  "ramdiskaddr=2000000\0"                        \
 573  "ramdiskfile=8572ds/ramdisk.uboot\0"           \
 574  "fdtaddr=c00000\0"                             \
 575  "fdtfile=8572ds/mpc8572ds.dtb\0"               \
 576  "bdev=sda3\0"
 577
 578 #define CONFIG_HDBOOT                           \
 579  "setenv bootargs root=/dev/$bdev rw "          \
 580  "console=$consoledev,$baudrate $othbootargs;"  \
 581  "tftp $loadaddr $bootfile;"                    \
 582  "tftp $fdtaddr $fdtfile;"                      \
 583  "bootm $loadaddr - $fdtaddr"
 584
 585 #define CONFIG_NFSBOOTCOMMAND           \
 586  "setenv bootargs root=/dev/nfs rw "    \
 587  "nfsroot=$serverip:$rootpath "         \
 588  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 589  "console=$consoledev,$baudrate $othbootargs;"  \
 590  "tftp $loadaddr $bootfile;"            \
 591  "tftp $fdtaddr $fdtfile;"              \
 592  "bootm $loadaddr - $fdtaddr"
 593
 594 #define CONFIG_RAMBOOTCOMMAND           \
 595  "setenv bootargs root=/dev/ram rw "    \
 596  "console=$consoledev,$baudrate $othbootargs;"  \
 597  "tftp $ramdiskaddr $ramdiskfile;"      \
 598  "tftp $loadaddr $bootfile;"            \
 599  "tftp $fdtaddr $fdtfile;"              \
 600  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 601
 602 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 603
 604 #endif  /* __CONFIG_H */