include/configs/MPC8610HPCD.h

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 /*
   8  * MPC8610HPCD board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  16
  17 /* video */
  18 #define CONFIG_FSL_DIU_FB
  19
  20 #ifdef CONFIG_FSL_DIU_FB
  21 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x2c000)
  22 #define CONFIG_VIDEO_LOGO
  23 #define CONFIG_VIDEO_BMP_LOGO
  24 #endif
  25
  26 #ifdef RUN_DIAG
  27 #define CONFIG_SYS_DIAG_ADDR            0xff800000
  28 #endif
  29
  30 /*
  31  * virtual address to be used for temporary mappings.  There
  32  * should be 128k free at this VA.
  33  */
  34 #define CONFIG_SYS_SCRATCH_VA   0xc0000000
  35
  36 #define CONFIG_PCI1             1       /* PCI controller 1 */
  37 #define CONFIG_PCIE1            1       /* PCIe 1 connected to ULI bridge */
  38 #define CONFIG_PCIE2            1       /* PCIe 2 connected to slot */
  39 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  40 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  41 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  42
  43 #define CONFIG_ENV_OVERWRITE
  44 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  45
  46 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  47 #define CONFIG_HIGH_BATS        1       /* High BATs supported & enabled */
  48 #define CONFIG_ALTIVEC          1
  49
  50 /*
  51  * L2CR setup -- make sure this is right for your board!
  52  */
  53 #define CONFIG_SYS_L2
  54 #define L2_INIT         0
  55 #define L2_ENABLE       (L2CR_L2E |0x00100000 )
  56
  57 #ifndef CONFIG_SYS_CLK_FREQ
  58 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  59 #endif
  60
  61 #define CONFIG_MISC_INIT_R              1
  62
  63 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  64 #define CONFIG_SYS_MEMTEST_END          0x00400000
  65
  66 /*
  67  * Base addresses -- Note these are effective addresses where the
  68  * actual resources get mapped (not physical addresses)
  69  */
  70 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  71 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  72
  73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  74 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  75 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  76
  77 /* DDR Setup */
  78 #undef CONFIG_FSL_DDR_INTERACTIVE
  79 #define CONFIG_SPD_EEPROM               /* Use SPD for DDR */
  80 #define CONFIG_DDR_SPD
  81
  82 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  83 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  84
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  86 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  87 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  88 #define CONFIG_VERY_BIG_RAM
  89
  90 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  91 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  92
  93 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  94
  95 /* These are used when DDR doesn't use SPD.  */
  96 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
  97
  98 #if 0 /* TODO */
  99 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 100 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 101 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 102 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 103 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 104 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 105 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 106 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 107 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 108 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 109 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 110 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 111 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 112 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 113 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 114
 115 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 116 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 117 #define CONFIG_SYS_DDR_SBE              0x000f0000
 118
 119 #endif
 120
 121 #define CONFIG_ID_EEPROM
 122 #define CONFIG_SYS_I2C_EEPROM_NXID
 123 #define CONFIG_ID_EEPROM
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 126
 127 #define CONFIG_SYS_FLASH_BASE           0xf0000000 /* start of FLASH 128M */
 128 #define CONFIG_SYS_FLASH_BASE2          0xf8000000
 129
 130 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 131
 132 #define CONFIG_SYS_BR0_PRELIM           0xf8001001 /* port size 16bit */
 133 #define CONFIG_SYS_OR0_PRELIM           0xf8006e65 /* 128MB NOR Flash*/
 134
 135 #define CONFIG_SYS_BR1_PRELIM           0xf0001001 /* port size 16bit */
 136 #define CONFIG_SYS_OR1_PRELIM           0xf8006e65 /* 128MB Promjet */
 137 #if 0 /* TODO */
 138 #define CONFIG_SYS_BR2_PRELIM           0xf0000000
 139 #define CONFIG_SYS_OR2_PRELIM           0xf0000000 /* 256MB NAND Flash - bank 1 */
 140 #endif
 141 #define CONFIG_SYS_BR3_PRELIM           0xe8000801 /* port size 8bit */
 142 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7 /* 1MB PIXIS area*/
 143
 144 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 145 #define PIXIS_BASE      0xe8000000      /* PIXIS registers */
 146 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 147 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 148 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 149 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 150 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch */
 151 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 152 #define PIXIS_BRDCFG0           0x8     /* PIXIS Board Configuration Register0*/
 153 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 154 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 155 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 156 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 157 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 158 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 159 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 160 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 161 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xC0    /* Reset altbank mask */
 162
 163 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 164 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 165
 166 #undef  CONFIG_SYS_FLASH_CHECKSUM
 167 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 168 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 170 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 171
 172 #define CONFIG_FLASH_CFI_DRIVER
 173 #define CONFIG_SYS_FLASH_CFI
 174 #define CONFIG_SYS_FLASH_EMPTY_INFO
 175
 176 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 177 #define CONFIG_SYS_RAMBOOT
 178 #else
 179 #undef  CONFIG_SYS_RAMBOOT
 180 #endif
 181
 182 #if defined(CONFIG_SYS_RAMBOOT)
 183 #undef CONFIG_SPD_EEPROM
 184 #define CONFIG_SYS_SDRAM_SIZE   256
 185 #endif
 186
 187 #undef CONFIG_CLOCKS_IN_MHZ
 188
 189 #define CONFIG_SYS_INIT_RAM_LOCK        1
 190 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 191 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 192 #else
 193 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4000000      /* Initial RAM address */
 194 #endif
 195 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 196
 197 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 198 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 201 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 202
 203 /* Serial Port */
 204 #define CONFIG_CONS_INDEX       1
 205 #define CONFIG_SYS_NS16550_SERIAL
 206 #define CONFIG_SYS_NS16550_REG_SIZE     1
 207 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 208
 209 #define CONFIG_SYS_BAUDRATE_TABLE \
 210         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 211
 212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 214
 215 /* maximum size of the flat tree (8K) */
 216 #define OF_FLAT_TREE_MAX_SIZE   8192
 217
 218 /*
 219  * I2C
 220  */
 221 #define CONFIG_SYS_I2C
 222 #define CONFIG_SYS_I2C_FSL
 223 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 224 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 225 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 226 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 227
 228 /*
 229  * General PCI
 230  * Addresses are mapped 1-1.
 231  */
 232 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 233 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 234 #define CONFIG_SYS_PCI1_MEM_VIRT        CONFIG_SYS_PCI1_MEM_BUS
 235 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 236 #define CONFIG_SYS_PCI1_IO_BUS  0x0000000
 237 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 238 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 239 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 240
 241 /* controller 1, Base address 0xa000 */
 242 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 243 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 244 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 245 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 246 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 247 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 248 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /* 1M */
 249
 250 /* controller 2, Base Address 0x9000 */
 251 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 252 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 253 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 254 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 255 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000      /* reuse mem LAW */
 256 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe2000000
 257 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00100000      /* 1M */
 258
 259 #if defined(CONFIG_PCI)
 260
 261 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 262
 263 #define CONFIG_ULI526X
 264 #ifdef CONFIG_ULI526X
 265 #endif
 266
 267 /************************************************************
 268  * USB support
 269  ************************************************************/
 270 #define CONFIG_PCI_OHCI         1
 271 #define CONFIG_USB_OHCI_NEW             1
 272 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 273 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 274 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 275
 276 #if !defined(CONFIG_PCI_PNP)
 277 #define PCI_ENET0_IOADDR        0xe0000000
 278 #define PCI_ENET0_MEMADDR       0xe0000000
 279 #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 280 #endif
 281
 282 #ifdef CONFIG_SCSI_AHCI
 283 #define CONFIG_SATA_ULI5288
 284 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 285 #define CONFIG_SYS_SCSI_MAX_LUN 1
 286 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 287 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 288 #endif
 289
 290 #endif  /* CONFIG_PCI */
 291
 292 /*
 293  * BAT0         2G      Cacheable, non-guarded
 294  * 0x0000_0000  2G      DDR
 295  */
 296 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW)
 297 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW)
 298
 299 /*
 300  * BAT1         1G      Cache-inhibited, guarded
 301  * 0x8000_0000  256M    PCI-1 Memory
 302  * 0xa000_0000  256M    PCI-Express 1 Memory
 303  * 0x9000_0000  256M    PCI-Express 2 Memory
 304  */
 305
 306 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 307                         | BATL_GUARDEDSTORAGE)
 308 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 309 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 310 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 311
 312 /*
 313  * BAT2         16M     Cache-inhibited, guarded
 314  * 0xe100_0000  1M      PCI-1 I/O
 315  */
 316
 317 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 318                         | BATL_GUARDEDSTORAGE)
 319 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 320 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 321 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 322
 323 /*
 324  * BAT3         4M      Cache-inhibited, guarded
 325  * 0xe000_0000  4M      CCSR
 326  */
 327
 328 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 329                         | BATL_GUARDEDSTORAGE)
 330 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
 331 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 332 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 333
 334 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 335 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 336                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 337                                        | BATL_GUARDEDSTORAGE)
 338 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 339                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 340 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 341                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 342 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 343 #endif
 344
 345 /*
 346  * BAT4         32M     Cache-inhibited, guarded
 347  * 0xe200_0000  1M      PCI-Express 2 I/O
 348  * 0xe300_0000  1M      PCI-Express 1 I/O
 349  */
 350
 351 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 352                         | BATL_GUARDEDSTORAGE)
 353 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 354 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 355 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 356
 357 /*
 358  * BAT5         128K    Cacheable, non-guarded
 359  * 0xe400_0000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 360  */
 361 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 362 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 363 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 364 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 365
 366 /*
 367  * BAT6         256M    Cache-inhibited, guarded
 368  * 0xf000_0000  256M    FLASH
 369  */
 370 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE   | BATL_PP_RW | BATL_CACHEINHIBIT \
 371                         | BATL_GUARDEDSTORAGE)
 372 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE   | BATU_BL_256M | BATU_VS | BATU_VP)
 373 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 374 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 375
 376 /* Map the last 1M of flash where we're running from reset */
 377 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 378                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 379 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 380 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 381                                  | BATL_MEMCOHERENCE)
 382 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 383
 384 /*
 385  * BAT7         4M      Cache-inhibited, guarded
 386  * 0xe800_0000  4M      PIXIS
 387  */
 388 #define CONFIG_SYS_DBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 389                         | BATL_GUARDEDSTORAGE)
 390 #define CONFIG_SYS_DBAT7U       (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 391 #define CONFIG_SYS_IBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 392 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 393
 394 /*
 395  * Environment
 396  */
 397 #ifndef CONFIG_SYS_RAMBOOT
 398 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 399 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 126k (one sector) for env */
 400 #define CONFIG_ENV_SIZE         0x2000
 401 #else
 402 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 403 #define CONFIG_ENV_SIZE         0x2000
 404 #endif
 405
 406 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 407 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 408
 409 /*
 410  * BOOTP options
 411  */
 412 #define CONFIG_BOOTP_BOOTFILESIZE
 413
 414 /*
 415  * Command line configuration.
 416  */
 417
 418 #define CONFIG_WATCHDOG                 /* watchdog enabled */
 419 #define CONFIG_SYS_WATCHDOG_FREQ        5000    /* Feed interval, 5s */
 420
 421 /*
 422  * Miscellaneous configurable options
 423  */
 424 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 425
 426 /*
 427  * For booting Linux, the board info and command line data
 428  * have to be in the first 8 MB of memory, since this is
 429  * the maximum mapped by the Linux kernel during initialization.
 430  */
 431 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 432 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 433
 434 #if defined(CONFIG_CMD_KGDB)
 435 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 436 #endif
 437
 438 /*
 439  * Environment Configuration
 440  */
 441 #define CONFIG_IPADDR           192.168.1.100
 442
 443 #define CONFIG_HOSTNAME         unknown
 444 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 445 #define CONFIG_BOOTFILE         "uImage"
 446 #define CONFIG_UBOOTPATH        8610hpcd/u-boot.bin
 447
 448 #define CONFIG_SERVERIP         192.168.1.1
 449 #define CONFIG_GATEWAYIP        192.168.1.1
 450 #define CONFIG_NETMASK          255.255.255.0
 451
 452 /* default location for tftp and bootm */
 453 #define CONFIG_LOADADDR         0x10000000
 454
 455 #if defined(CONFIG_PCI1)
 456 #define PCI_ENV \
 457  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 458         "echo e;md ${a}e00 9\0" \
 459  "pci1regs=setenv a e0008; run pcireg\0" \
 460  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 461         "pci d.w $b.0 56 1\0" \
 462  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
 463         "pci w.w $b.0 56 ffff\0"        \
 464  "pci1err=setenv a e0008; run pcierr\0" \
 465  "pci1errc=setenv a e0008; run pcierrc\0"
 466 #else
 467 #define PCI_ENV ""
 468 #endif
 469
 470 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
 471 #define PCIE_ENV \
 472  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 473         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 474  "pcie1regs=setenv a e000a; run pciereg\0"      \
 475  "pcie2regs=setenv a e0009; run pciereg\0"      \
 476  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
 477         "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"        \
 478         "pci d $b.0 130 1\0" \
 479  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
 480         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
 481         "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"            \
 482  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 483  "pcie1err=setenv a e000a; run pcieerr\0"       \
 484  "pcie2err=setenv a e0009; run pcieerr\0"       \
 485  "pcie1errc=setenv a e000a; run pcieerrc\0"     \
 486  "pcie2errc=setenv a e0009; run pcieerrc\0"
 487 #else
 488 #define PCIE_ENV ""
 489 #endif
 490
 491 #define DMA_ENV \
 492  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
 493         "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
 494  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
 495         "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
 496  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
 497         "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
 498  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 499         "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 500
 501 #ifdef ENV_DEBUG
 502 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 503 "netdev=eth0\0"                                                 \
 504 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 505 "tftpflash=tftpboot $loadaddr $uboot; "                         \
 506         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 507                 " +$filesize; " \
 508         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 509                 " +$filesize; " \
 510         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 511                 " $filesize; "  \
 512         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 513                 " +$filesize; " \
 514         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 515                 " $filesize\0"  \
 516 "consoledev=ttyS0\0"                                            \
 517 "ramdiskaddr=0x18000000\0"                                      \
 518 "ramdiskfile=8610hpcd/ramdisk.uboot\0"                          \
 519 "fdtaddr=0x17c00000\0"                                          \
 520 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                           \
 521 "bdev=sda3\0"                                   \
 522 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 523 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 524 "maxcpus=1"     \
 525 "eoi=mw e00400b0 0\0"                                           \
 526 "iack=md e00400a0 1\0"                                          \
 527 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
 528         "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
 529         "md ${a}f00 5\0" \
 530 "ddr1regs=setenv a e0002; run ddrreg\0" \
 531 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
 532         "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
 533         "md ${a}e60 1; md ${a}ef0 1d\0" \
 534 "guregs=setenv a e00e0; run gureg\0" \
 535 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
 536 "mcmregs=setenv a e0001; run mcmreg\0" \
 537 "diuregs=md e002c000 1d\0" \
 538 "dium=mw e002c01c\0" \
 539 "diuerr=md e002c014 1\0" \
 540 "pmregs=md e00e1000 2b\0" \
 541 "lawregs=md e0000c08 4b\0" \
 542 "lbcregs=md e0005000 36\0" \
 543 "dma0regs=md e0021100 12\0" \
 544 "dma1regs=md e0021180 12\0" \
 545 "dma2regs=md e0021200 12\0" \
 546 "dma3regs=md e0021280 12\0" \
 547  PCI_ENV \
 548  PCIE_ENV \
 549  DMA_ENV
 550 #else
 551 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 552         "netdev=eth0\0"                                         \
 553         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 554         "consoledev=ttyS0\0"                                    \
 555         "ramdiskaddr=0x18000000\0"                              \
 556         "ramdiskfile=8610hpcd/ramdisk.uboot\0"                  \
 557         "fdtaddr=0x17c00000\0"                                  \
 558         "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                   \
 559         "bdev=sda3\0"
 560 #endif
 561
 562 #define CONFIG_NFSBOOTCOMMAND                                   \
 563  "setenv bootargs root=/dev/nfs rw "                            \
 564         "nfsroot=$serverip:$rootpath "                          \
 565         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 566         "console=$consoledev,$baudrate $othbootargs;"           \
 567  "tftp $loadaddr $bootfile;"                                    \
 568  "tftp $fdtaddr $fdtfile;"                                      \
 569  "bootm $loadaddr - $fdtaddr"
 570
 571 #define CONFIG_RAMBOOTCOMMAND \
 572  "setenv bootargs root=/dev/ram rw "                            \
 573         "console=$consoledev,$baudrate $othbootargs;"           \
 574  "tftp $ramdiskaddr $ramdiskfile;"                              \
 575  "tftp $loadaddr $bootfile;"                                    \
 576  "tftp $fdtaddr $fdtfile;"                                      \
 577  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 578
 579 #define CONFIG_BOOTCOMMAND              \
 580  "setenv bootargs root=/dev/$bdev rw "  \
 581         "console=$consoledev,$baudrate $othbootargs;"   \
 582  "tftp $loadaddr $bootfile;"            \
 583  "tftp $fdtaddr $fdtfile;"              \
 584  "bootm $loadaddr - $fdtaddr"
 585
 586 #endif  /* __CONFIG_H */