include/configs/MPC8610HPCD.h

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 /*
   8  * MPC8610HPCD board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_MPC8610          1       /* MPC8610 specific */
  16 #define CONFIG_MPC8610HPCD      1       /* MPC8610HPCD board specific */
  17 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  20
  21 /* video */
  22 #define CONFIG_FSL_DIU_FB
  23
  24 #ifdef CONFIG_FSL_DIU_FB
  25 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x2c000)
  26 #define CONFIG_CMD_BMP
  27 #define CONFIG_CFB_CONSOLE
  28 #define CONFIG_VIDEO_SW_CURSOR
  29 #define CONFIG_VGA_AS_SINGLE_DEVICE
  30 #define CONFIG_VIDEO_LOGO
  31 #define CONFIG_VIDEO_BMP_LOGO
  32 #endif
  33
  34 #ifdef RUN_DIAG
  35 #define CONFIG_SYS_DIAG_ADDR            0xff800000
  36 #endif
  37
  38 /*
  39  * virtual address to be used for temporary mappings.  There
  40  * should be 128k free at this VA.
  41  */
  42 #define CONFIG_SYS_SCRATCH_VA   0xc0000000
  43
  44 #define CONFIG_PCI              1       /* Enable PCI/PCIE*/
  45 #define CONFIG_PCI1             1       /* PCI controller 1 */
  46 #define CONFIG_PCIE1            1       /* PCIe 1 connected to ULI bridge */
  47 #define CONFIG_PCIE2            1       /* PCIe 2 connected to slot */
  48 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  49 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  50 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  51 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  52
  53 #define CONFIG_ENV_OVERWRITE
  54 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  55
  56 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  57 #define CONFIG_HIGH_BATS        1       /* High BATs supported & enabled */
  58 #define CONFIG_ALTIVEC          1
  59
  60 /*
  61  * L2CR setup -- make sure this is right for your board!
  62  */
  63 #define CONFIG_SYS_L2
  64 #define L2_INIT         0
  65 #define L2_ENABLE       (L2CR_L2E |0x00100000 )
  66
  67 #ifndef CONFIG_SYS_CLK_FREQ
  68 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  69 #endif
  70
  71 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  72 #define CONFIG_MISC_INIT_R              1
  73
  74 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  75 #define CONFIG_SYS_MEMTEST_END          0x00400000
  76
  77 /*
  78  * Base addresses -- Note these are effective addresses where the
  79  * actual resources get mapped (not physical addresses)
  80  */
  81 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  82 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  83 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  84
  85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  86 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  87 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  88
  89 /* DDR Setup */
  90 #define CONFIG_SYS_FSL_DDR2
  91 #undef CONFIG_FSL_DDR_INTERACTIVE
  92 #define CONFIG_SPD_EEPROM               /* Use SPD for DDR */
  93 #define CONFIG_DDR_SPD
  94
  95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  96 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  97
  98 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 100 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 101 #define CONFIG_VERY_BIG_RAM
 102
 103 #define CONFIG_NUM_DDR_CONTROLLERS      1
 104 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 105 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 106
 107 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 108
 109 /* These are used when DDR doesn't use SPD.  */
 110 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 111
 112 #if 0 /* TODO */
 113 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 114 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
 115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 116 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 117 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 118 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 119 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 120 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 121 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 122 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 123 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 124 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 125 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 126 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 127 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 128
 129 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 130 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 131 #define CONFIG_SYS_DDR_SBE              0x000f0000
 132
 133 #endif
 134
 135 #define CONFIG_ID_EEPROM
 136 #define CONFIG_SYS_I2C_EEPROM_NXID
 137 #define CONFIG_ID_EEPROM
 138 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 140
 141 #define CONFIG_SYS_FLASH_BASE           0xf0000000 /* start of FLASH 128M */
 142 #define CONFIG_SYS_FLASH_BASE2          0xf8000000
 143
 144 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 145
 146 #define CONFIG_SYS_BR0_PRELIM           0xf8001001 /* port size 16bit */
 147 #define CONFIG_SYS_OR0_PRELIM           0xf8006e65 /* 128MB NOR Flash*/
 148
 149 #define CONFIG_SYS_BR1_PRELIM           0xf0001001 /* port size 16bit */
 150 #define CONFIG_SYS_OR1_PRELIM           0xf8006e65 /* 128MB Promjet */
 151 #if 0 /* TODO */
 152 #define CONFIG_SYS_BR2_PRELIM           0xf0000000
 153 #define CONFIG_SYS_OR2_PRELIM           0xf0000000 /* 256MB NAND Flash - bank 1 */
 154 #endif
 155 #define CONFIG_SYS_BR3_PRELIM           0xe8000801 /* port size 8bit */
 156 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7 /* 1MB PIXIS area*/
 157
 158 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 159 #define PIXIS_BASE      0xe8000000      /* PIXIS registers */
 160 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 161 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 162 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 163 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 164 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch */
 165 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 166 #define PIXIS_BRDCFG0           0x8     /* PIXIS Board Configuration Register0*/
 167 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 168 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 169 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 170 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 171 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 172 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 173 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 174 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 175 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xC0    /* Reset altbank mask */
 176
 177 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 178 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 179
 180 #undef  CONFIG_SYS_FLASH_CHECKSUM
 181 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 182 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 183 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 184 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 185
 186 #define CONFIG_FLASH_CFI_DRIVER
 187 #define CONFIG_SYS_FLASH_CFI
 188 #define CONFIG_SYS_FLASH_EMPTY_INFO
 189
 190 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 191 #define CONFIG_SYS_RAMBOOT
 192 #else
 193 #undef  CONFIG_SYS_RAMBOOT
 194 #endif
 195
 196 #if defined(CONFIG_SYS_RAMBOOT)
 197 #undef CONFIG_SPD_EEPROM
 198 #define CONFIG_SYS_SDRAM_SIZE   256
 199 #endif
 200
 201 #undef CONFIG_CLOCKS_IN_MHZ
 202
 203 #define CONFIG_SYS_INIT_RAM_LOCK        1
 204 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 205 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 206 #else
 207 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4000000      /* Initial RAM address */
 208 #endif
 209 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 210
 211 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 212 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 213
 214 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 215 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 216
 217 /* Serial Port */
 218 #define CONFIG_CONS_INDEX       1
 219 #define CONFIG_SYS_NS16550_SERIAL
 220 #define CONFIG_SYS_NS16550_REG_SIZE     1
 221 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 222
 223 #define CONFIG_SYS_BAUDRATE_TABLE \
 224         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 225
 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 228
 229 /* maximum size of the flat tree (8K) */
 230 #define OF_FLAT_TREE_MAX_SIZE   8192
 231
 232 /*
 233  * I2C
 234  */
 235 #define CONFIG_SYS_I2C
 236 #define CONFIG_SYS_I2C_FSL
 237 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 238 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 239 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 240 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 241
 242 /*
 243  * General PCI
 244  * Addresses are mapped 1-1.
 245  */
 246 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 247 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 248 #define CONFIG_SYS_PCI1_MEM_VIRT        CONFIG_SYS_PCI1_MEM_BUS
 249 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 250 #define CONFIG_SYS_PCI1_IO_BUS  0x0000000
 251 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 252 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 253 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 254
 255 /* controller 1, Base address 0xa000 */
 256 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 257 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 258 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 259 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 260 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 261 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 262 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /* 1M */
 263
 264 /* controller 2, Base Address 0x9000 */
 265 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 266 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 267 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 268 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 269 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000      /* reuse mem LAW */
 270 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe2000000
 271 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00100000      /* 1M */
 272
 273 #if defined(CONFIG_PCI)
 274
 275 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 276
 277 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 278 #define CONFIG_CMD_REGINFO
 279
 280 #define CONFIG_ULI526X
 281 #ifdef CONFIG_ULI526X
 282 #endif
 283
 284 /************************************************************
 285  * USB support
 286  ************************************************************/
 287 #define CONFIG_PCI_OHCI         1
 288 #define CONFIG_USB_OHCI_NEW             1
 289 #define CONFIG_USB_KEYBOARD     1
 290 #define CONFIG_SYS_STDIO_DEREGISTER
 291 #define CONFIG_SYS_USB_EVENT_POLL       1
 292 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 293 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 294 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 295
 296 #if !defined(CONFIG_PCI_PNP)
 297 #define PCI_ENET0_IOADDR        0xe0000000
 298 #define PCI_ENET0_MEMADDR       0xe0000000
 299 #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 300 #endif
 301
 302 #define CONFIG_DOS_PARTITION
 303 #define CONFIG_SCSI_AHCI
 304
 305 #ifdef CONFIG_SCSI_AHCI
 306 #define CONFIG_LIBATA
 307 #define CONFIG_SATA_ULI5288
 308 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 309 #define CONFIG_SYS_SCSI_MAX_LUN 1
 310 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 311 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 312 #endif
 313
 314 #endif  /* CONFIG_PCI */
 315
 316 /*
 317  * BAT0         2G      Cacheable, non-guarded
 318  * 0x0000_0000  2G      DDR
 319  */
 320 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW)
 321 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW)
 322
 323 /*
 324  * BAT1         1G      Cache-inhibited, guarded
 325  * 0x8000_0000  256M    PCI-1 Memory
 326  * 0xa000_0000  256M    PCI-Express 1 Memory
 327  * 0x9000_0000  256M    PCI-Express 2 Memory
 328  */
 329
 330 #define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 331                         | BATL_GUARDEDSTORAGE)
 332 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 333 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 334 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 335
 336 /*
 337  * BAT2         16M     Cache-inhibited, guarded
 338  * 0xe100_0000  1M      PCI-1 I/O
 339  */
 340
 341 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 342                         | BATL_GUARDEDSTORAGE)
 343 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 344 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 345 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 346
 347 /*
 348  * BAT3         4M      Cache-inhibited, guarded
 349  * 0xe000_0000  4M      CCSR
 350  */
 351
 352 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 353                         | BATL_GUARDEDSTORAGE)
 354 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
 355 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 356 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 357
 358 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 359 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 360                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 361                                        | BATL_GUARDEDSTORAGE)
 362 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 363                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 364 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 365                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 366 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 367 #endif
 368
 369 /*
 370  * BAT4         32M     Cache-inhibited, guarded
 371  * 0xe200_0000  1M      PCI-Express 2 I/O
 372  * 0xe300_0000  1M      PCI-Express 1 I/O
 373  */
 374
 375 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 376                         | BATL_GUARDEDSTORAGE)
 377 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 378 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 379 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 380
 381 /*
 382  * BAT5         128K    Cacheable, non-guarded
 383  * 0xe400_0000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 384  */
 385 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 386 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 387 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 388 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 389
 390 /*
 391  * BAT6         256M    Cache-inhibited, guarded
 392  * 0xf000_0000  256M    FLASH
 393  */
 394 #define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE   | BATL_PP_RW | BATL_CACHEINHIBIT \
 395                         | BATL_GUARDEDSTORAGE)
 396 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE   | BATU_BL_256M | BATU_VS | BATU_VP)
 397 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 398 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 399
 400 /* Map the last 1M of flash where we're running from reset */
 401 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 402                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 403 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 404 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 405                                  | BATL_MEMCOHERENCE)
 406 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 407
 408 /*
 409  * BAT7         4M      Cache-inhibited, guarded
 410  * 0xe800_0000  4M      PIXIS
 411  */
 412 #define CONFIG_SYS_DBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 413                         | BATL_GUARDEDSTORAGE)
 414 #define CONFIG_SYS_DBAT7U       (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 415 #define CONFIG_SYS_IBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 416 #define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 417
 418 /*
 419  * Environment
 420  */
 421 #ifndef CONFIG_SYS_RAMBOOT
 422 #define CONFIG_ENV_IS_IN_FLASH  1
 423 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 424 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 126k (one sector) for env */
 425 #define CONFIG_ENV_SIZE         0x2000
 426 #else
 427 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 428 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 429 #define CONFIG_ENV_SIZE         0x2000
 430 #endif
 431
 432 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 433 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 434
 435 /*
 436  * BOOTP options
 437  */
 438 #define CONFIG_BOOTP_BOOTFILESIZE
 439 #define CONFIG_BOOTP_BOOTPATH
 440 #define CONFIG_BOOTP_GATEWAY
 441 #define CONFIG_BOOTP_HOSTNAME
 442
 443 /*
 444  * Command line configuration.
 445  */
 446
 447 #if defined(CONFIG_PCI)
 448 #define CONFIG_CMD_PCI
 449 #define CONFIG_SCSI
 450 #endif
 451
 452 #define CONFIG_WATCHDOG                 /* watchdog enabled */
 453 #define CONFIG_SYS_WATCHDOG_FREQ        5000    /* Feed interval, 5s */
 454
 455 /*
 456  * Miscellaneous configurable options
 457  */
 458 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 459 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 460 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 461
 462 #if defined(CONFIG_CMD_KGDB)
 463 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 464 #else
 465 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 466 #endif
 467
 468 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 469 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 470 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 471
 472 /*
 473  * For booting Linux, the board info and command line data
 474  * have to be in the first 8 MB of memory, since this is
 475  * the maximum mapped by the Linux kernel during initialization.
 476  */
 477 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 478 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 479
 480 #if defined(CONFIG_CMD_KGDB)
 481 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 482 #endif
 483
 484 /*
 485  * Environment Configuration
 486  */
 487 #define CONFIG_IPADDR           192.168.1.100
 488
 489 #define CONFIG_HOSTNAME         unknown
 490 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 491 #define CONFIG_BOOTFILE         "uImage"
 492 #define CONFIG_UBOOTPATH        8610hpcd/u-boot.bin
 493
 494 #define CONFIG_SERVERIP         192.168.1.1
 495 #define CONFIG_GATEWAYIP        192.168.1.1
 496 #define CONFIG_NETMASK          255.255.255.0
 497
 498 /* default location for tftp and bootm */
 499 #define CONFIG_LOADADDR         0x10000000
 500
 501 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 502
 503 #define CONFIG_BAUDRATE 115200
 504
 505 #if defined(CONFIG_PCI1)
 506 #define PCI_ENV \
 507  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 508         "echo e;md ${a}e00 9\0" \
 509  "pci1regs=setenv a e0008; run pcireg\0" \
 510  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 511         "pci d.w $b.0 56 1\0" \
 512  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
 513         "pci w.w $b.0 56 ffff\0"        \
 514  "pci1err=setenv a e0008; run pcierr\0" \
 515  "pci1errc=setenv a e0008; run pcierrc\0"
 516 #else
 517 #define PCI_ENV ""
 518 #endif
 519
 520 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
 521 #define PCIE_ENV \
 522  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 523         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 524  "pcie1regs=setenv a e000a; run pciereg\0"      \
 525  "pcie2regs=setenv a e0009; run pciereg\0"      \
 526  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
 527         "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"        \
 528         "pci d $b.0 130 1\0" \
 529  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
 530         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
 531         "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"            \
 532  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 533  "pcie1err=setenv a e000a; run pcieerr\0"       \
 534  "pcie2err=setenv a e0009; run pcieerr\0"       \
 535  "pcie1errc=setenv a e000a; run pcieerrc\0"     \
 536  "pcie2errc=setenv a e0009; run pcieerrc\0"
 537 #else
 538 #define PCIE_ENV ""
 539 #endif
 540
 541 #define DMA_ENV \
 542  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
 543         "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
 544  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
 545         "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
 546  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
 547         "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
 548  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 549         "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 550
 551 #ifdef ENV_DEBUG
 552 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 553 "netdev=eth0\0"                                                 \
 554 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 555 "tftpflash=tftpboot $loadaddr $uboot; "                         \
 556         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 557                 " +$filesize; " \
 558         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 559                 " +$filesize; " \
 560         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 561                 " $filesize; "  \
 562         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 563                 " +$filesize; " \
 564         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 565                 " $filesize\0"  \
 566 "consoledev=ttyS0\0"                                            \
 567 "ramdiskaddr=0x18000000\0"                                      \
 568 "ramdiskfile=8610hpcd/ramdisk.uboot\0"                          \
 569 "fdtaddr=0x17c00000\0"                                          \
 570 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                           \
 571 "bdev=sda3\0"                                   \
 572 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 573 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 574 "maxcpus=1"     \
 575 "eoi=mw e00400b0 0\0"                                           \
 576 "iack=md e00400a0 1\0"                                          \
 577 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
 578         "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
 579         "md ${a}f00 5\0" \
 580 "ddr1regs=setenv a e0002; run ddrreg\0" \
 581 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
 582         "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
 583         "md ${a}e60 1; md ${a}ef0 1d\0" \
 584 "guregs=setenv a e00e0; run gureg\0" \
 585 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
 586 "mcmregs=setenv a e0001; run mcmreg\0" \
 587 "diuregs=md e002c000 1d\0" \
 588 "dium=mw e002c01c\0" \
 589 "diuerr=md e002c014 1\0" \
 590 "pmregs=md e00e1000 2b\0" \
 591 "lawregs=md e0000c08 4b\0" \
 592 "lbcregs=md e0005000 36\0" \
 593 "dma0regs=md e0021100 12\0" \
 594 "dma1regs=md e0021180 12\0" \
 595 "dma2regs=md e0021200 12\0" \
 596 "dma3regs=md e0021280 12\0" \
 597  PCI_ENV \
 598  PCIE_ENV \
 599  DMA_ENV
 600 #else
 601 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 602         "netdev=eth0\0"                                         \
 603         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 604         "consoledev=ttyS0\0"                                    \
 605         "ramdiskaddr=0x18000000\0"                              \
 606         "ramdiskfile=8610hpcd/ramdisk.uboot\0"                  \
 607         "fdtaddr=0x17c00000\0"                                  \
 608         "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                   \
 609         "bdev=sda3\0"
 610 #endif
 611
 612 #define CONFIG_NFSBOOTCOMMAND                                   \
 613  "setenv bootargs root=/dev/nfs rw "                            \
 614         "nfsroot=$serverip:$rootpath "                          \
 615         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 616         "console=$consoledev,$baudrate $othbootargs;"           \
 617  "tftp $loadaddr $bootfile;"                                    \
 618  "tftp $fdtaddr $fdtfile;"                                      \
 619  "bootm $loadaddr - $fdtaddr"
 620
 621 #define CONFIG_RAMBOOTCOMMAND \
 622  "setenv bootargs root=/dev/ram rw "                            \
 623         "console=$consoledev,$baudrate $othbootargs;"           \
 624  "tftp $ramdiskaddr $ramdiskfile;"                              \
 625  "tftp $loadaddr $bootfile;"                                    \
 626  "tftp $fdtaddr $fdtfile;"                                      \
 627  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 628
 629 #define CONFIG_BOOTCOMMAND              \
 630  "setenv bootargs root=/dev/$bdev rw "  \
 631         "console=$consoledev,$baudrate $othbootargs;"   \
 632  "tftp $loadaddr $bootfile;"            \
 633  "tftp $fdtaddr $fdtfile;"              \
 634  "bootm $loadaddr - $fdtaddr"
 635
 636 #endif  /* __CONFIG_H */