include/configs/MVBLUE.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define MV_VERSION      "v0.2.0"
  13
  14 /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
  15 #define ERR_NONE                0
  16 #define ERR_ENV                 1
  17 #define ERR_BOOTM_BADMAGIC      2
  18 #define ERR_BOOTM_BADCRC        3
  19 #define ERR_BOOTM_GUNZIP        4
  20 #define ERR_BOOTP_TIMEOUT       5
  21 #define ERR_DHCP                6
  22 #define ERR_TFTP                7
  23 #define ERR_NOLAN               8
  24 #define ERR_LANDRV              9
  25
  26 #define CONFIG_BOARD_TYPES      1
  27 #define MVBLUE_BOARD_BOX        1
  28 #define MVBLUE_BOARD_LYNX       2
  29
  30 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  31 #define CONFIG_SYS_LDSCRIPT     "board/mvblue/u-boot.lds"
  32
  33 #if 0
  34 #define ERR_LED(code)   do { if (code) \
  35                 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
  36         else \
  37                 *(volatile char *)(0xff000003) = ( 1 ); \
  38 } while(0)
  39 #else
  40 #define ERR_LED(code)
  41 #endif
  42
  43 #define CONFIG_MPC8245          1
  44 #define CONFIG_MVBLUE           1
  45
  46 #define CONFIG_CLOCKS_IN_MHZ    1
  47
  48 #define CONFIG_BOARD_TYPES      1
  49
  50 #define CONFIG_CONS_INDEX       1
  51 #define CONFIG_BAUDRATE         115200
  52
  53 #define CONFIG_BOOTDELAY        3
  54 #define CONFIG_BOOT_RETRY_TIME  -1
  55
  56 #define CONFIG_AUTOBOOT_KEYED
  57 #define CONFIG_AUTOBOOT_PROMPT          \
  58         "autoboot in %d seconds (stop with 's')...\n", bootdelay
  59 #define CONFIG_AUTOBOOT_STOP_STR        "s"
  60 #define CONFIG_ZERO_BOOTDELAY_CHECK
  61 #define CONFIG_RESET_TO_RETRY           60
  62
  63
  64 /*
  65  * Command line configuration.
  66  */
  67
  68 #define CONFIG_CMD_ASKENV
  69 #define CONFIG_CMD_BOOTD
  70 #define CONFIG_CMD_CACHE
  71 #define CONFIG_CMD_DHCP
  72 #define CONFIG_CMD_ECHO
  73 #define CONFIG_CMD_SAVEENV
  74 #define CONFIG_CMD_FLASH
  75 #define CONFIG_CMD_IMI
  76 #define CONFIG_CMD_NET
  77 #define CONFIG_CMD_PCI
  78 #define CONFIG_CMD_RUN
  79
  80
  81 /*
  82  * BOOTP options
  83  */
  84 #define CONFIG_BOOTP_SUBNETMASK
  85 #define CONFIG_BOOTP_GATEWAY
  86 #define CONFIG_BOOTP_HOSTNAME
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_BOOTFILESIZE
  89 #define CONFIG_BOOTP_SUBNETMASK
  90 #define CONFIG_BOOTP_GATEWAY
  91 #define CONFIG_BOOTP_HOSTNAME
  92 #define CONFIG_BOOTP_NISDOMAIN
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_DNS
  95 #define CONFIG_BOOTP_DNS2
  96 #define CONFIG_BOOTP_SEND_HOSTNAME
  97 #define CONFIG_BOOTP_NTPSERVER
  98 #define CONFIG_BOOTP_TIMEOFFSET
  99
 100
 101 /*
 102  * Miscellaneous configurable options
 103  */
 104 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 105 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 106
 107 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 108 #define CONFIG_SYS_MAXARGS      16              /* Max number of command args   */
 109 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 110 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address                 */
 111
 112 #define CONFIG_BOOTCOMMAND      "run nfsboot"
 113 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock5 ro rootfstype=jffs2"
 114
 115 #define CONFIG_NFSBOOTCOMMAND   "bootp; run nfsargs addcons;bootm"
 116
 117 #define CONFIG_EXTRA_ENV_SETTINGS                       \
 118         "console_nr=0\0"                                \
 119     "dhcp_client_id=mvBOX-XP\0"                         \
 120     "dhcp_vendor-class-identifier=mvBOX\0"              \
 121     "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"    \
 122     "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"    \
 123     "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"    \
 124     "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"        \
 125         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 126                         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"   \
 127         "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
 128     "mv_version=" MV_VERSION "\0"       \
 129         "bootretry=30\0"
 130
 131 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 132
 133 /*-----------------------------------------------------------------------
 134  * PCI stuff
 135  *-----------------------------------------------------------------------
 136  */
 137
 138 #define CONFIG_PCI
 139 #define CONFIG_PCI_INDIRECT_BRIDGE
 140 #define CONFIG_PCI_PNP
 141 #define CONFIG_PCI_SCAN_SHOW
 142
 143 #define CONFIG_NET_RETRY_COUNT          5
 144
 145 #define CONFIG_TULIP
 146 #define CONFIG_TULIP_FIX_DAVICOM        1
 147 #define CONFIG_ETHADDR                  b6:b4:45:eb:fb:c0
 148
 149 #define CONFIG_HW_WATCHDOG
 150
 151 /*-----------------------------------------------------------------------
 152  * Start addresses for the final memory configuration
 153  * (Set up by the startup code)
 154  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 155  */
 156 #define CONFIG_SYS_SDRAM_BASE       0x00000000
 157
 158 #define CONFIG_SYS_FLASH_BASE      0xFFF00000
 159 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 160
 161 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 162 #define CONFIG_SYS_EUMB_ADDR        0xFC000000
 163
 164 #define CONFIG_SYS_MONITOR_LEN     0x00100000
 165 #define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
 166
 167 #define CONFIG_SYS_MEMTEST_START   0x00100000   /* memtest works on             */
 168 #define CONFIG_SYS_MEMTEST_END      0x00800000  /* 1M ... 8M in DRAM            */
 169
 170 /* Maximum amount of RAM.  */
 171 #define CONFIG_SYS_MAX_RAM_SIZE    0x10000000   /* 0 .. 256MB of (S)DRAM */
 172
 173
 174 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 175 #undef CONFIG_SYS_RAMBOOT
 176 #else
 177 #define CONFIG_SYS_RAMBOOT
 178 #endif
 179
 180 #define CONFIG_SYS_ISA_IO      0xFE000000
 181
 182 /*
 183  * serial configuration
 184  */
 185 #define CONFIG_SYS_NS16550
 186 #define CONFIG_SYS_NS16550_SERIAL
 187
 188 #define CONFIG_SYS_NS16550_REG_SIZE    1
 189
 190 #define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)
 191
 192 #define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
 193 #define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)
 194
 195 /*-----------------------------------------------------------------------
 196  * Definitions for initial stack pointer and data area
 197  */
 198 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 199 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 200 #define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 201
 202 /*
 203  * Low Level Configuration Settings
 204  * (address mappings, register initial values, etc.)
 205  * You should know what you are doing if you make changes here.
 206  * For the detail description refer to the MPC8240 user's manual.
 207  */
 208
 209 #define CONFIG_SYS_CLK_FREQ  33000000
 210
 211 /* Bit-field values for MCCR1.  */
 212 #define CONFIG_SYS_ROMNAL      7
 213 #define CONFIG_SYS_ROMFAL      11
 214
 215 /* Bit-field values for MCCR2.  */
 216 #define CONFIG_SYS_TSWAIT      0x5
 217 #define CONFIG_SYS_REFINT      430
 218
 219 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
 220 #define CONFIG_SYS_BSTOPRE     121
 221
 222 /* Bit-field values for MCCR3.  */
 223 #define CONFIG_SYS_REFREC      8
 224
 225 /* Bit-field values for MCCR4.  */
 226 #define CONFIG_SYS_PRETOACT    3
 227 #define CONFIG_SYS_ACTTOPRE    5
 228 #define CONFIG_SYS_ACTORW      3
 229 #define CONFIG_SYS_SDMODE_CAS_LAT  3
 230 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 231 #define CONFIG_SYS_EXTROM      1
 232 #define CONFIG_SYS_REGDIMM     0
 233 #define CONFIG_SYS_DBUS_SIZE2  1
 234 #define CONFIG_SYS_SDMODE_WRAP 0
 235
 236 #define CONFIG_SYS_PGMAX       0x32
 237 #define CONFIG_SYS_SDRAM_DSCD  0x20
 238
 239 /* Memory bank settings.
 240  * Only bits 20-29 are actually used from these vales to set the
 241  * start/end addresses. The upper two bits will always be 0, and the lower
 242  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 243  * address. Refer to the MPC8240 book.
 244  */
 245
 246 #define CONFIG_SYS_BANK0_START      0x00000000
 247 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 248 #define CONFIG_SYS_BANK0_ENABLE    1
 249 #define CONFIG_SYS_BANK1_START     0x3ff00000
 250 #define CONFIG_SYS_BANK1_END       0x3fffffff
 251 #define CONFIG_SYS_BANK1_ENABLE    0
 252 #define CONFIG_SYS_BANK2_START     0x3ff00000
 253 #define CONFIG_SYS_BANK2_END       0x3fffffff
 254 #define CONFIG_SYS_BANK2_ENABLE    0
 255 #define CONFIG_SYS_BANK3_START     0x3ff00000
 256 #define CONFIG_SYS_BANK3_END       0x3fffffff
 257 #define CONFIG_SYS_BANK3_ENABLE    0
 258 #define CONFIG_SYS_BANK4_START     0x3ff00000
 259 #define CONFIG_SYS_BANK4_END       0x3fffffff
 260 #define CONFIG_SYS_BANK4_ENABLE    0
 261 #define CONFIG_SYS_BANK5_START     0x3ff00000
 262 #define CONFIG_SYS_BANK5_END       0x3fffffff
 263 #define CONFIG_SYS_BANK5_ENABLE    0
 264 #define CONFIG_SYS_BANK6_START     0x3ff00000
 265 #define CONFIG_SYS_BANK6_END       0x3fffffff
 266 #define CONFIG_SYS_BANK6_ENABLE    0
 267 #define CONFIG_SYS_BANK7_START     0x3ff00000
 268 #define CONFIG_SYS_BANK7_END       0x3fffffff
 269 #define CONFIG_SYS_BANK7_ENABLE    0
 270
 271 #define CONFIG_SYS_ODCR     0xff
 272
 273 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 274 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 275
 276 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 277 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 278
 279 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 280 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 281
 282 #define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 283 #define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 284
 285 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 286 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 287 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 288 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 289 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 290 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 291 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 292 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 293
 294 /*
 295  * For booting Linux, the board info and command line data
 296  * have to be in the first 8 MB of memory, since this is
 297  * the maximum mapped by the Linux kernel during initialization.
 298  */
 299 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 300
 301 /*-----------------------------------------------------------------------
 302  * FLASH organization
 303  */
 304 #undef  CONFIG_SYS_FLASH_PROTECTION
 305 #define CONFIG_SYS_MAX_FLASH_BANKS              1       /* Max number of flash banks            */
 306 #define CONFIG_SYS_MAX_FLASH_SECT               63      /* Max number of sectors per flash      */
 307
 308 #define CONFIG_SYS_FLASH_ERASE_TOUT     12000
 309 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000
 310
 311
 312 #define CONFIG_ENV_IS_IN_FLASH
 313
 314 #define CONFIG_ENV_OFFSET               0x00010000
 315 #define CONFIG_ENV_SIZE         0x00010000
 316 #define CONFIG_ENV_SECT_SIZE    0x00010000
 317
 318 /*-----------------------------------------------------------------------
 319  * Cache Configuration
 320  */
 321 #define CONFIG_SYS_CACHELINE_SIZE       32
 322 #if defined(CONFIG_CMD_KGDB)
 323 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value        */
 324 #endif
 325 #endif  /* __CONFIG_H */