include/configs/MVBLUE.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #define MV_VERSION      "v0.2.0"
  29
  30 /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
  31 #define ERR_NONE                0
  32 #define ERR_ENV                 1
  33 #define ERR_BOOTM_BADMAGIC      2
  34 #define ERR_BOOTM_BADCRC        3
  35 #define ERR_BOOTM_GUNZIP        4
  36 #define ERR_BOOTP_TIMEOUT       5
  37 #define ERR_DHCP                6
  38 #define ERR_TFTP                7
  39 #define ERR_NOLAN               8
  40 #define ERR_LANDRV              9
  41
  42 #define CONFIG_BOARD_TYPES      1
  43 #define MVBLUE_BOARD_BOX        1
  44 #define MVBLUE_BOARD_LYNX       2
  45
  46 #if 0
  47 #define ERR_LED(code)   do { if (code) \
  48                 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
  49         else \
  50                 *(volatile char *)(0xff000003) = ( 1 ); \
  51 } while(0)
  52 #else
  53 #define ERR_LED(code)
  54 #endif
  55
  56 #define CONFIG_MPC824X          1
  57 #define CONFIG_MPC8245          1
  58 #define CONFIG_MVBLUE           1
  59
  60 #define CONFIG_CLOCKS_IN_MHZ    1
  61
  62 #define CONFIG_BOARD_TYPES    1
  63
  64 #define CONFIG_CONS_INDEX       1
  65 #define CONFIG_BAUDRATE         115200
  66 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  67
  68 #define CONFIG_BOOTDELAY                3
  69 #define CONFIG_BOOT_RETRY_TIME  -1
  70
  71 #define CONFIG_AUTOBOOT_KEYED
  72 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds (stop with 's')...\n"
  73 #define CONFIG_AUTOBOOT_STOP_STR        "s"
  74 #define CONFIG_ZERO_BOOTDELAY_CHECK
  75 #define CONFIG_RESET_TO_RETRY           60
  76
  77
  78 /*
  79  * Command line configuration.
  80  */
  81
  82 #define CONFIG_CMD_ASKENV
  83 #define CONFIG_CMD_BOOTD
  84 #define CONFIG_CMD_CACHE
  85 #define CONFIG_CMD_DHCP
  86 #define CONFIG_CMD_ECHO
  87 #define CONFIG_CMD_ENV
  88 #define CONFIG_CMD_FLASH
  89 #define CONFIG_CMD_IMI
  90 #define CONFIG_CMD_IRQ
  91 #define CONFIG_CMD_NET
  92 #define CONFIG_CMD_PCI
  93 #define CONFIG_CMD_RUN
  94
  95
  96 /*
  97  * BOOTP options
  98  */
  99 #define CONFIG_BOOTP_SUBNETMASK
 100 #define CONFIG_BOOTP_GATEWAY
 101 #define CONFIG_BOOTP_HOSTNAME
 102 #define CONFIG_BOOTP_BOOTPATH
 103 #define CONFIG_BOOTP_BOOTFILESIZE
 104 #define CONFIG_BOOTP_SUBNETMASK
 105 #define CONFIG_BOOTP_GATEWAY
 106 #define CONFIG_BOOTP_HOSTNAME
 107 #define CONFIG_BOOTP_NISDOMAIN
 108 #define CONFIG_BOOTP_BOOTPATH
 109 #define CONFIG_BOOTP_DNS
 110 #define CONFIG_BOOTP_DNS2
 111 #define CONFIG_BOOTP_SEND_HOSTNAME
 112 #define CONFIG_BOOTP_NTPSERVER
 113 #define CONFIG_BOOTP_TIMEOFFSET
 114
 115
 116 /*
 117  * Miscellaneous configurable options
 118  */
 119 #define CFG_LONGHELP                    /* undef to save memory         */
 120 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 121 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 122
 123 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 124 #define CFG_MAXARGS     16              /* Max number of command args   */
 125 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 126 #define CFG_LOAD_ADDR   0x00100000      /* Default load address                 */
 127
 128 #define CONFIG_BOOTCOMMAND      "run nfsboot"
 129 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock5 ro rootfstype=jffs2"
 130
 131 #define CONFIG_NFSBOOTCOMMAND   "bootp; run nfsargs addcons;bootm"
 132
 133 #define CONFIG_EXTRA_ENV_SETTINGS                       \
 134         "console_nr=0\0"                                \
 135     "dhcp_client_id=mvBOX-XP\0"                         \
 136     "dhcp_vendor-class-identifier=mvBOX\0"              \
 137     "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"    \
 138     "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"    \
 139     "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"    \
 140     "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"        \
 141         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 142                         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"   \
 143         "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
 144     "mv_version=" MV_VERSION "\0"       \
 145         "bootretry=30\0"
 146
 147 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 148
 149 /*-----------------------------------------------------------------------
 150  * PCI stuff
 151  *-----------------------------------------------------------------------
 152  */
 153
 154 #define CONFIG_PCI
 155 #define CONFIG_PCI_PNP
 156 #define CONFIG_PCI_SCAN_SHOW
 157
 158 #define CONFIG_NET_MULTI
 159 #define CONFIG_NET_RETRY_COUNT          5
 160
 161 #define CONFIG_TULIP
 162 #define CONFIG_TULIP_FIX_DAVICOM        1
 163 #define CONFIG_ETHADDR                  b6:b4:45:eb:fb:c0
 164
 165 #define CONFIG_HW_WATCHDOG
 166
 167 /*-----------------------------------------------------------------------
 168  * Start addresses for the final memory configuration
 169  * (Set up by the startup code)
 170  * Please note that CFG_SDRAM_BASE _must_ start at 0
 171  */
 172 #define CFG_SDRAM_BASE      0x00000000
 173
 174 #define CFG_FLASH_BASE      0xFFF00000
 175 #define CFG_MONITOR_BASE    TEXT_BASE
 176
 177 #define CFG_RESET_ADDRESS   0xFFF00100
 178 #define CFG_EUMB_ADDR       0xFC000000
 179
 180 #define CFG_MONITOR_LEN     0x00100000
 181 #define CFG_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
 182
 183 #define CFG_MEMTEST_START   0x00100000  /* memtest works on             */
 184 #define CFG_MEMTEST_END     0x00800000  /* 1M ... 8M in DRAM            */
 185
 186 /* Maximum amount of RAM.  */
 187 #define CFG_MAX_RAM_SIZE    0x10000000  /* 0 .. 256MB of (S)DRAM */
 188
 189
 190 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 191 #undef CFG_RAMBOOT
 192 #else
 193 #define CFG_RAMBOOT
 194 #endif
 195
 196 #define CFG_ISA_IO      0xFE000000
 197
 198 /*
 199  * serial configuration
 200  */
 201 #define CFG_NS16550
 202 #define CFG_NS16550_SERIAL
 203
 204 #define CFG_NS16550_REG_SIZE    1
 205
 206 #define CFG_NS16550_CLK     get_bus_freq(0)
 207
 208 #define CFG_NS16550_COM1    (CFG_EUMB_ADDR + 0x4500)
 209 #define CFG_NS16550_COM2    (CFG_EUMB_ADDR + 0x4600)
 210
 211 /*-----------------------------------------------------------------------
 212  * Definitions for initial stack pointer and data area
 213  */
 214 #define CFG_INIT_RAM_ADDR     0x40000000
 215 #define CFG_INIT_RAM_END      0x1000
 216 #define CFG_GBL_DATA_SIZE     128
 217 #define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 218
 219 /*
 220  * Low Level Configuration Settings
 221  * (address mappings, register initial values, etc.)
 222  * You should know what you are doing if you make changes here.
 223  * For the detail description refer to the MPC8240 user's manual.
 224  */
 225
 226 #define CONFIG_SYS_CLK_FREQ  33000000
 227 #define CFG_HZ                   10000
 228
 229 /* Bit-field values for MCCR1.  */
 230 #define CFG_ROMNAL      7
 231 #define CFG_ROMFAL      11
 232
 233 /* Bit-field values for MCCR2.  */
 234 #define CFG_TSWAIT      0x5
 235 #define CFG_REFINT      430
 236
 237 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
 238 #define CFG_BSTOPRE     121
 239
 240 /* Bit-field values for MCCR3.  */
 241 #define CFG_REFREC      8
 242
 243 /* Bit-field values for MCCR4.  */
 244 #define CFG_PRETOACT    3
 245 #define CFG_ACTTOPRE    5
 246 #define CFG_ACTORW      3
 247 #define CFG_SDMODE_CAS_LAT  3
 248 #define CFG_REGISTERD_TYPE_BUFFER 1
 249 #define CFG_EXTROM      1
 250 #define CFG_REGDIMM     0
 251 #define CFG_DBUS_SIZE2  1
 252 #define CFG_SDMODE_WRAP 0
 253
 254 #define CFG_PGMAX       0x32
 255 #define CFG_SDRAM_DSCD  0x20
 256
 257 /* Memory bank settings.
 258  * Only bits 20-29 are actually used from these vales to set the
 259  * start/end addresses. The upper two bits will always be 0, and the lower
 260  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 261  * address. Refer to the MPC8240 book.
 262  */
 263
 264 #define CFG_BANK0_START     0x00000000
 265 #define CFG_BANK0_END       (CFG_MAX_RAM_SIZE - 1)
 266 #define CFG_BANK0_ENABLE    1
 267 #define CFG_BANK1_START     0x3ff00000
 268 #define CFG_BANK1_END       0x3fffffff
 269 #define CFG_BANK1_ENABLE    0
 270 #define CFG_BANK2_START     0x3ff00000
 271 #define CFG_BANK2_END       0x3fffffff
 272 #define CFG_BANK2_ENABLE    0
 273 #define CFG_BANK3_START     0x3ff00000
 274 #define CFG_BANK3_END       0x3fffffff
 275 #define CFG_BANK3_ENABLE    0
 276 #define CFG_BANK4_START     0x3ff00000
 277 #define CFG_BANK4_END       0x3fffffff
 278 #define CFG_BANK4_ENABLE    0
 279 #define CFG_BANK5_START     0x3ff00000
 280 #define CFG_BANK5_END       0x3fffffff
 281 #define CFG_BANK5_ENABLE    0
 282 #define CFG_BANK6_START     0x3ff00000
 283 #define CFG_BANK6_END       0x3fffffff
 284 #define CFG_BANK6_ENABLE    0
 285 #define CFG_BANK7_START     0x3ff00000
 286 #define CFG_BANK7_END       0x3fffffff
 287 #define CFG_BANK7_ENABLE    0
 288
 289 #define CFG_ODCR            0xff
 290
 291 #define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 292 #define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 293
 294 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 295 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 296
 297 #define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 298 #define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 299
 300 #define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 301 #define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 302
 303 #define CFG_DBAT0L  CFG_IBAT0L
 304 #define CFG_DBAT0U  CFG_IBAT0U
 305 #define CFG_DBAT1L  CFG_IBAT1L
 306 #define CFG_DBAT1U  CFG_IBAT1U
 307 #define CFG_DBAT2L  CFG_IBAT2L
 308 #define CFG_DBAT2U  CFG_IBAT2U
 309 #define CFG_DBAT3L  CFG_IBAT3L
 310 #define CFG_DBAT3U  CFG_IBAT3U
 311
 312 /*
 313  * For booting Linux, the board info and command line data
 314  * have to be in the first 8 MB of memory, since this is
 315  * the maximum mapped by the Linux kernel during initialization.
 316  */
 317 #define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 318
 319 /*-----------------------------------------------------------------------
 320  * FLASH organization
 321  */
 322 #undef  CFG_FLASH_PROTECTION
 323 #define CFG_MAX_FLASH_BANKS             1       /* Max number of flash banks            */
 324 #define CFG_MAX_FLASH_SECT              63      /* Max number of sectors per flash      */
 325
 326 #define CFG_FLASH_ERASE_TOUT    12000
 327 #define CFG_FLASH_WRITE_TOUT    1000
 328
 329
 330 #define CFG_ENV_IS_IN_FLASH
 331
 332 #define CFG_ENV_OFFSET          0x00010000
 333 #define CFG_ENV_SIZE            0x00010000
 334 #define CFG_ENV_SECT_SIZE       0x00010000
 335
 336 /*-----------------------------------------------------------------------
 337  * Cache Configuration
 338  */
 339 #define CFG_CACHELINE_SIZE      32
 340 #if defined(CONFIG_CMD_KGDB)
 341 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 342 #endif
 343
 344 /*
 345  * Internal Definitions
 346  *
 347  * Boot Flags
 348  */
 349 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 350 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 351
 352 #endif  /* __CONFIG_H */