include/configs/NC650.h

   1 /*
   2  * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
   3  * (C) Copyright 2005
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36 #define CONFIG_MPC852T          1
  37 #define CONFIG_NC650            1
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40700000
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         115200
  45 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  46
  47 /*
  48  * 10 MHz - PLL input clock
  49  */
  50 #define CONFIG_8xx_OSCLK                10000000
  51
  52 /*
  53  * 50 MHz - default CPU clock
  54  */
  55 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  56
  57 /*
  58  * 15 MHz - CPU minimum clock
  59  */
  60 #define CONFIG_SYS_8xx_CPUCLK_MIN               15000000
  61
  62 /*
  63  * 133 MHz - CPU maximum clock
  64  */
  65 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000
  66
  67 #define CONFIG_SYS_MEASURE_CPUCLK
  68 #define CONFIG_SYS_8XX_XIN                      CONFIG_8xx_OSCLK
  69
  70 #define CONFIG_BOOTDELAY                5       /* autoboot after 5 seconds     */
  71 #define CONFIG_AUTOBOOT_KEYED
  72 #define CONFIG_AUTOBOOT_PROMPT          \
  73         "\nEnter password - autoboot in %d seconds...\n", bootdelay
  74 #define CONFIG_AUTOBOOT_DELAY_STR       "ids"
  75 #define CONFIG_BOOT_RETRY_TIME          900
  76 #define CONFIG_BOOT_RETRY_MIN           30
  77
  78 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  79
  80 #undef  CONFIG_BOOTARGS
  81 #define CONFIG_BOOTCOMMAND                                                      \
  82         "bootp;"                                                                \
  83         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  84         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  85         "bootm"
  86
  87 #define CONFIG_WATCHDOG                 /* watchdog enabled             */
  88
  89 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
  90
  91 /*
  92  * BOOTP options
  93  */
  94 #define CONFIG_BOOTP_SUBNETMASK
  95 #define CONFIG_BOOTP_GATEWAY
  96 #define CONFIG_BOOTP_HOSTNAME
  97 #define CONFIG_BOOTP_BOOTPATH
  98 #define CONFIG_BOOTP_BOOTFILESIZE
  99
 100
 101 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 102 #define FEC_ENET
 103 #define CONFIG_MII
 104 #define CONFIG_SYS_DISCOVER_PHY 1
 105
 106
 107 /* enable I2C and select the hardware/software driver */
 108 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 109 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 110 #define CONFIG_SYS_I2C_SPEED            100000  /* 100 kHz                      */
 111 #define CONFIG_SYS_I2C_SLAVE            0x7f
 112
 113 /*
 114  * Software (bit-bang) I2C driver configuration
 115  */
 116 #if defined(CONFIG_IDS852_REV1)
 117
 118 #define SCL             0x1000          /* PA 3 */
 119 #define SDA             0x2000          /* PA 2 */
 120
 121 #define __I2C_DIR       immr->im_ioport.iop_padir
 122 #define __I2C_DAT       immr->im_ioport.iop_padat
 123 #define __I2C_PAR       immr->im_ioport.iop_papar
 124
 125 #elif defined(CONFIG_IDS852_REV2)
 126
 127 #define SCL             0x0002          /* PB 30 */
 128 #define SDA             0x0001          /* PB 31 */
 129
 130 #define __I2C_PAR       immr->im_cpm.cp_pbpar
 131 #define __I2C_DIR       immr->im_cpm.cp_pbdir
 132 #define __I2C_DAT       immr->im_cpm.cp_pbdat
 133
 134 #endif
 135
 136 #define I2C_INIT        { __I2C_PAR &= ~(SDA|SCL);      \
 137                           __I2C_DIR |= (SDA|SCL);       }
 138 #define I2C_READ        ((__I2C_DAT & SDA) ? 1 : 0)
 139 #define I2C_SDA(x)      { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
 140 #define I2C_SCL(x)      { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
 141 #define I2C_DELAY       { udelay(5); }
 142 #define I2C_ACTIVE      { __I2C_DIR |= SDA; }
 143 #define I2C_TRISTATE    { __I2C_DIR &= ~SDA; }
 144
 145 #define CONFIG_RTC_PCF8563
 146 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 147
 148
 149 /*
 150  * Command line configuration.
 151  */
 152 #include <config_cmd_default.h>
 153
 154 #define CONFIG_CMD_ASKENV
 155 #define CONFIG_CMD_DATE
 156 #define CONFIG_CMD_DHCP
 157 #define CONFIG_CMD_I2C
 158 #define CONFIG_CMD_NAND
 159 #define CONFIG_CMD_JFFS2
 160 #define CONFIG_CMD_NFS
 161 #define CONFIG_CMD_SNTP
 162
 163
 164 /*
 165  * Miscellaneous configurable options
 166  */
 167 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 168 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 169 #if defined(CONFIG_CMD_KGDB)
 170 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 171 #else
 172 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 173 #endif
 174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 175 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 176 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 177
 178 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 179 #define CONFIG_SYS_MEMTEST_END          0x0400000       /* 1 ... 4 MB in DRAM   */
 180
 181 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 182
 183 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 184
 185 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 186
 187 /*
 188  * Low Level Configuration Settings
 189  * (address mappings, register initial values, etc.)
 190  * You should know what you are doing if you make changes here.
 191  */
 192 /*-----------------------------------------------------------------------
 193  * Internal Memory Mapped Register
 194  */
 195 #define CONFIG_SYS_IMMR         0xF0000000
 196 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
 197
 198 /*-----------------------------------------------------------------------
 199  * Definitions for initial stack pointer and data area (in DPRAM)
 200  */
 201 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 202 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 203 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 204 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 /*-----------------------------------------------------------------------
 208  * Start addresses for the final memory configuration
 209  * (Set up by the startup code)
 210  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 211  */
 212 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 213 #define CONFIG_SYS_FLASH_BASE           0x40000000
 214
 215 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 216
 217 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 219 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 220
 221 /*
 222  * For booting Linux, the board info and command line data
 223  * have to be in the first 8 MB of memory, since this is
 224  * the maximum mapped by the Linux kernel during initialization.
 225  */
 226 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 227 /*-----------------------------------------------------------------------
 228  * FLASH organization
 229  */
 230 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 231 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip    */
 232
 233 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 235
 236
 237 #define CONFIG_ENV_IS_IN_FLASH  1
 238 #define CONFIG_ENV_OFFSET               0x00740000
 239
 240 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment sector     */
 241 #define CONFIG_ENV_SIZE         0x4000  /* Used Size of Environment Sector      */
 242
 243 /*-----------------------------------------------------------------------
 244  * Cache Configuration
 245  */
 246 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 247 #if defined(CONFIG_CMD_KGDB)
 248 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 249 #endif
 250
 251 /*
 252  * NAND flash support
 253  */
 254 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 255
 256 /*-----------------------------------------------------------------------
 257  * SYPCR - System Protection Control                                    11-9
 258  * SYPCR can only be written once after reset!
 259  *-----------------------------------------------------------------------
 260  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 261  */
 262 #if defined(CONFIG_WATCHDOG)
 263 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 264                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 265 #else
 266 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 267 #endif
 268
 269 /*-----------------------------------------------------------------------
 270  * SIUMCR - SIU Module Configuration                                    11-6
 271  *-----------------------------------------------------------------------
 272  */
 273 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 274
 275 /*-----------------------------------------------------------------------
 276  * TBSCR - Time Base Status and Control                                 11-26
 277  *-----------------------------------------------------------------------
 278  * Clear Reference Interrupt Status, Timebase freezing enabled
 279  */
 280 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 281
 282 /*-----------------------------------------------------------------------
 283  * PISCR - Periodic Interrupt Status and Control                11-31
 284  *-----------------------------------------------------------------------
 285  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 286  */
 287 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 288
 289 /*-----------------------------------------------------------------------
 290  * SCCR - System Clock and reset Control Register               15-27
 291  *-----------------------------------------------------------------------
 292  * Set clock output, timebase and RTC source and divider,
 293  * power management and some other internal clocks
 294  */
 295 #define SCCR_MASK       SCCR_EBDF11
 296 #define CONFIG_SYS_SCCR (SCCR_COM00     | SCCR_DFSYNC00 | \
 297                          SCCR_DFBRG00   | SCCR_DFNL000  | SCCR_DFNH000  | \
 298                          SCCR_DFLCD000  | SCCR_DFALCD00)
 299
 300  /*-----------------------------------------------------------------------
 301  *
 302  *-----------------------------------------------------------------------
 303  *
 304  */
 305 #define CONFIG_SYS_DER          0
 306
 307 /*
 308  * Init Memory Controller:
 309  *
 310  * BR0 and OR0 (FLASH)
 311  */
 312
 313 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 314
 315 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 316 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 317
 318 /* FLASH timing: Default value of OR0 after reset */
 319 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
 320                                  OR_SCY_15_CLK | OR_TRLX)
 321
 322 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 323 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 324 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 325
 326 /*
 327  * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
 328  * rev2 only uses the chipselect
 329  */
 330 #define CONFIG_SYS_NAND_BASE            0x50000000
 331 #define CONFIG_SYS_NAND_SIZE            0x04000000
 332
 333 #define CONFIG_SYS_OR_TIMING_NAND       (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 334                                  OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
 335
 336 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
 337 #define CONFIG_SYS_OR2_PRELIM  (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI )
 338
 339 /*
 340  * BR3 and OR3 (SDRAM)
 341  */
 342 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank           */
 343 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 344
 345  /*
 346   * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 347   */
 348 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 349
 350 #define CONFIG_SYS_OR3_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
 351 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 352
 353 /*
 354  * BR4 and OR4 (CPLD)
 355  */
 356 #define CONFIG_SYS_CPLD_BASE           0x80000000      /* CPLD                 */
 357 #define CONFIG_SYS_CPLD_SIZE           0x10000         /* only 16 used         */
 358
 359 #define CONFIG_SYS_OR_TIMING_CPLD       (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 360                                  OR_SCY_1_CLK)
 361
 362 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 363 #define CONFIG_SYS_OR4_PRELIM  (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD)
 364
 365 /*
 366  * BR5 and OR5 (SRAM)
 367  */
 368 #define CONFIG_SYS_SRAM_BASE            0x60000000
 369 #define CONFIG_SYS_SRAM_SIZE            0x00080000
 370
 371 #define CONFIG_SYS_OR_TIMING_SRAM       (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 372                                  OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
 373
 374 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 375 #define CONFIG_SYS_OR5_PRELIM  (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM)
 376
 377 #if defined(CONFIG_CP850)
 378 /*
 379  *  BR6 and OR6 (DPRAM) - only on CP850
 380  */
 381 #define CONFIG_SYS_OR6_PRELIM          0xffff8170
 382 #define CONFIG_SYS_BR6_PRELIM          0xa0000401
 383 #define DPRAM_BASE_ADDR         0xa0000000
 384
 385 #define CONFIG_MISC_INIT_R      1
 386 #endif
 387
 388 /*
 389  * 4096 Rows from SDRAM example configuration
 390  * 1000 factor s -> ms
 391  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 392  * 4    Number of refresh cycles per period
 393  * 64   Refresh cycle in ms per number of rows
 394  */
 395 #define CONFIG_SYS_PTA_PER_CLK          ((4096 * 64 * 1000) / (4 * 64))
 396
 397 /*
 398  * Memory Periodic Timer Prescaler
 399  */
 400
 401 /* periodic timer for refresh */
 402 #define CONFIG_SYS_MAMR_PTA             39
 403
 404 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 405 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 406 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 407
 408 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 409 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 410 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 411
 412 /*
 413  * MAMR settings for SDRAM
 414  */
 415
 416 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 417                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
 418                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 419 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 420                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
 421                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 422
 423 /*
 424  * MBMR settings for NAND flash
 425  */
 426
 427 #define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X )
 428
 429 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 430 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
 431
 432 /*
 433  * JFFS2 partitions
 434  */
 435
 436 /* No command line, one static partition */
 437 #undef CONFIG_CMD_MTDPARTS
 438 #define CONFIG_JFFS2_DEV                "nand0"
 439 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 440 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 441
 442 /* mtdparts command line support */
 443 #define CONFIG_CMD_MTDPARTS
 444 #define MTDIDS_DEFAULT          "nor0=nc650-0,nand0=nc650-nand"
 445
 446 #define MTDPARTS_DEFAULT        "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
 447                                         "4m(cramfs1),1m(cramfs2)," \
 448                                         "256k(u-boot),128k(env);" \
 449                                 "nc650-nand:4m(jffs1),28m(jffs2)"
 450
 451 #endif  /* __CONFIG_H */