include/configs/NETPHONE.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26  * U-Boot port on NetTA4 board
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #define CONFIG_MPC870           1       /* This is a MPC885 CPU         */
  38 #define CONFIG_NETPHONE         1       /* ...on a NetPhone board       */
  39
  40 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  41 #undef  CONFIG_8xx_CONS_SMC2
  42 #undef  CONFIG_8xx_CONS_NONE
  43
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  45
  46 /* #define CONFIG_XIN            10000000 */
  47 #define CONFIG_XIN               50000000
  48 #define MPC8XX_HZ               120000000
  49
  50 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ
  51
  52 #if 0
  53 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  54 #else
  55 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  56 #endif
  57
  58 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  59
  60 #define CONFIG_PREBOOT  "echo;"
  61
  62 #undef  CONFIG_BOOTARGS
  63 #define CONFIG_BOOTCOMMAND                                                      \
  64         "tftpboot; "                                                            \
  65         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  66         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  67         "bootm"
  68
  69 #define CONFIG_AUTOSCRIPT
  70 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  71 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  72
  73 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  74
  75 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  76
  77 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  78 #define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
  79
  80 #define CONFIG_BOOTP_MASK               (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
  81
  82 #undef CONFIG_MAC_PARTITION
  83 #undef CONFIG_DOS_PARTITION
  84
  85 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  86
  87 #define CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
  88 #define FEC_ENET                1       /* eth.c needs it that way... */
  89 #undef CFG_DISCOVER_PHY
  90 #define CONFIG_MII              1
  91 #define CONFIG_RMII             1       /* use RMII interface */
  92
  93 #define CONFIG_ETHER_ON_FEC1    1
  94 #define CONFIG_FEC1_PHY         8       /* phy address of FEC */
  95 #define CONFIG_FEC1_PHY_NORXERR 1
  96
  97 #define CONFIG_ETHER_ON_FEC2    1
  98 #define CONFIG_FEC2_PHY         4
  99 #define CONFIG_FEC2_PHY_NORXERR 1
 100
 101 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 102
 103 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 104                                 CFG_CMD_NAND    | \
 105                                 CFG_CMD_DHCP    | \
 106                                 CFG_CMD_PING    | \
 107                                 CFG_CMD_MII     | \
 108                                 CFG_CMD_CDP       \
 109                                 )
 110
 111 #define CONFIG_BOARD_EARLY_INIT_F       1
 112 #define CONFIG_MISC_INIT_R
 113
 114 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 115 #include <cmd_confdefs.h>
 116
 117 /*
 118  * Miscellaneous configurable options
 119  */
 120 #define CFG_LONGHELP                    /* undef to save memory         */
 121 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 122
 123 #define CFG_HUSH_PARSER 1
 124 #define CFG_PROMPT_HUSH_PS2     "> "
 125
 126 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 127 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 128 #else
 129 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 130 #endif
 131 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 132 #define CFG_MAXARGS     16              /* max number of command args   */
 133 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 134
 135 #define CFG_MEMTEST_START       0x0300000       /* memtest works on     */
 136 #define CFG_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
 137
 138 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 139
 140 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 141
 142 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 143
 144 /*
 145  * Low Level Configuration Settings
 146  * (address mappings, register initial values, etc.)
 147  * You should know what you are doing if you make changes here.
 148  */
 149 /*-----------------------------------------------------------------------
 150  * Internal Memory Mapped Register
 151  */
 152 #define CFG_IMMR                0xFF000000
 153
 154 /*-----------------------------------------------------------------------
 155  * Definitions for initial stack pointer and data area (in DPRAM)
 156  */
 157 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 158 #define CFG_INIT_RAM_END        0x3000  /* End of used area in DPRAM    */
 159 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 160 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 161 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 162
 163 /*-----------------------------------------------------------------------
 164  * Start addresses for the final memory configuration
 165  * (Set up by the startup code)
 166  * Please note that CFG_SDRAM_BASE _must_ start at 0
 167  */
 168 #define CFG_SDRAM_BASE          0x00000000
 169 #define CFG_FLASH_BASE          0x40000000
 170 #if defined(DEBUG)
 171 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 172 #else
 173 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 174 #endif
 175 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 176 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 177
 178 /*
 179  * For booting Linux, the board info and command line data
 180  * have to be in the first 8 MB of memory, since this is
 181  * the maximum mapped by the Linux kernel during initialization.
 182  */
 183 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 184
 185 /*-----------------------------------------------------------------------
 186  * FLASH organization
 187  */
 188 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 189 #define CFG_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
 190
 191 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 192 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 193
 194 #define CFG_ENV_IS_IN_FLASH     1
 195 #define CFG_ENV_SECT_SIZE       0x10000
 196
 197 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x60000)
 198 #define CFG_ENV_OFFSET          0
 199 #define CFG_ENV_SIZE            0x4000
 200
 201 #define CFG_ENV_ADDR_REDUND     (CFG_FLASH_BASE + 0x70000)
 202 #define CFG_ENV_OFFSET_REDUND   0
 203 #define CFG_ENV_SIZE_REDUND     CFG_ENV_SIZE
 204
 205 /*-----------------------------------------------------------------------
 206  * Cache Configuration
 207  */
 208 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 209 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 210 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 211 #endif
 212
 213 /*-----------------------------------------------------------------------
 214  * SYPCR - System Protection Control                            11-9
 215  * SYPCR can only be written once after reset!
 216  *-----------------------------------------------------------------------
 217  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 218  */
 219 #if defined(CONFIG_WATCHDOG)
 220 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 221                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 222 #else
 223 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 224 #endif
 225
 226 /*-----------------------------------------------------------------------
 227  * SIUMCR - SIU Module Configuration                            11-6
 228  *-----------------------------------------------------------------------
 229  * PCMCIA config., multi-function pin tri-state
 230  */
 231 #ifndef CONFIG_CAN_DRIVER
 232 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 233 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 234 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 235 #endif  /* CONFIG_CAN_DRIVER */
 236
 237 /*-----------------------------------------------------------------------
 238  * TBSCR - Time Base Status and Control                         11-26
 239  *-----------------------------------------------------------------------
 240  * Clear Reference Interrupt Status, Timebase freezing enabled
 241  */
 242 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 243
 244 /*-----------------------------------------------------------------------
 245  * RTCSC - Real-Time Clock Status and Control Register          11-27
 246  *-----------------------------------------------------------------------
 247  */
 248 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 249
 250 /*-----------------------------------------------------------------------
 251  * PISCR - Periodic Interrupt Status and Control                11-31
 252  *-----------------------------------------------------------------------
 253  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 254  */
 255 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 256
 257 /*-----------------------------------------------------------------------
 258  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 259  *-----------------------------------------------------------------------
 260  * Reset PLL lock status sticky bit, timer expired status bit and timer
 261  * interrupt status bit
 262  *
 263  */
 264
 265 #if CONFIG_XIN == 10000000
 266
 267 #if MPC8XX_HZ == 120000000
 268 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 269                          (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 270                          PLPRCR_TEXPS)
 271 #elif MPC8XX_HZ == 100000000
 272 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 273                          (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 274                          PLPRCR_TEXPS)
 275 #elif MPC8XX_HZ == 50000000
 276 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 277                          (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 278                          PLPRCR_TEXPS)
 279 #elif MPC8XX_HZ == 25000000
 280 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 281                          (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 282                          PLPRCR_TEXPS)
 283 #elif MPC8XX_HZ == 40000000
 284 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 285                          (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 286                          PLPRCR_TEXPS)
 287 #elif MPC8XX_HZ == 75000000
 288 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 289                          (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 290                          PLPRCR_TEXPS)
 291 #else
 292 #error unsupported CPU freq for XIN = 10MHz
 293 #endif
 294
 295 #elif CONFIG_XIN == 50000000
 296
 297 #if MPC8XX_HZ == 120000000
 298 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 299                          (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 300                          PLPRCR_TEXPS)
 301 #elif MPC8XX_HZ == 100000000
 302 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 303                          (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 304                          PLPRCR_TEXPS)
 305 #else
 306 #error unsupported CPU freq for XIN = 50MHz
 307 #endif
 308
 309 #else
 310
 311 #error unsupported XIN freq
 312 #endif
 313
 314
 315 /*
 316  *-----------------------------------------------------------------------
 317  * SCCR - System Clock and reset Control Register               15-27
 318  *-----------------------------------------------------------------------
 319  * Set clock output, timebase and RTC source and divider,
 320  * power management and some other internal clocks
 321  */
 322
 323 #define SCCR_MASK       SCCR_EBDF11
 324 #if MPC8XX_HZ > 66666666
 325 #define CFG_SCCR        (SCCR_TBS     | \
 326                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 327                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 328                          SCCR_DFALCD00 | SCCR_EBDF01)
 329 #else
 330 #define CFG_SCCR        (SCCR_TBS     | \
 331                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 332                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 333                          SCCR_DFALCD00)
 334 #endif
 335
 336 /*-----------------------------------------------------------------------
 337  *
 338  *-----------------------------------------------------------------------
 339  *
 340  */
 341 /*#define       CFG_DER 0x2002000F*/
 342 #define CFG_DER 0
 343
 344 /*
 345  * Init Memory Controller:
 346  *
 347  * BR0/1 and OR0/1 (FLASH)
 348  */
 349
 350 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 351
 352 /* used to re-map FLASH both when starting from SRAM or FLASH:
 353  * restrict access enough to keep SRAM working (if any)
 354  * but not too much to meddle with FLASH accesses
 355  */
 356 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 357 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 358
 359 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 360 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 361
 362 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 363 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 364 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 365
 366 /*
 367  * BR3 and OR3 (SDRAM)
 368  *
 369  */
 370 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
 371 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
 372
 373 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 374 #define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
 375
 376 #define CFG_OR3_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
 377 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
 378
 379 /*
 380  * Memory Periodic Timer Prescaler
 381  */
 382
 383 /*
 384  * Memory Periodic Timer Prescaler
 385  *
 386  * The Divider for PTA (refresh timer) configuration is based on an
 387  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 388  * the number of chip selects (NCS) and the actually needed refresh
 389  * rate is done by setting MPTPR.
 390  *
 391  * PTA is calculated from
 392  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 393  *
 394  *      gclk      CPU clock (not bus clock!)
 395  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 396  *
 397  * 4096  Rows from SDRAM example configuration
 398  * 1000  factor s -> ms
 399  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 400  *    4  Number of refresh cycles per period
 401  *   64  Refresh cycle in ms per number of rows
 402  * --------------------------------------------
 403  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 404  *
 405  * 50 MHz => 50.000.000 / Divider =  98
 406  * 66 Mhz => 66.000.000 / Divider = 129
 407  * 80 Mhz => 80.000.000 / Divider = 156
 408  */
 409
 410 #define CFG_MAMR_PTA             234
 411
 412 /*
 413  * For 16 MBit, refresh rates could be 31.3 us
 414  * (= 64 ms / 2K = 125 / quad bursts).
 415  * For a simpler initialization, 15.6 us is used instead.
 416  *
 417  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 418  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 419  */
 420 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 421 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 422
 423 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 424 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 425 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 426
 427 /*
 428  * MAMR settings for SDRAM
 429  */
 430
 431 /* 8 column SDRAM */
 432 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 433                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 434                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 435
 436 /* 9 column SDRAM */
 437 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 438                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 439                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 440
 441 /*
 442  * Internal Definitions
 443  *
 444  * Boot Flags
 445  */
 446 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 447 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 448
 449 #define CONFIG_ARTOS                    /* include ARTOS support */
 450
 451 #define CONFIG_LAST_STAGE_INIT          /* needed to reset the damn phys */
 452
 453 /****************************************************************/
 454
 455 #define DSP_SIZE        0x00010000      /* 64K */
 456 #define NAND_SIZE       0x00010000      /* 64K */
 457 #define ER_SIZE         0x00010000      /* 64K */
 458
 459 #define DSP_BASE        0xF1000000
 460 #define NAND_BASE       0xF1010000
 461 #define ER_BASE         0xF1020000
 462
 463 /****************************************************************/
 464
 465 /* NAND */
 466 #define CFG_NAND_BASE           NAND_BASE
 467 #define CONFIG_MTD_NAND_ECC_JFFS2
 468
 469 #define CFG_MAX_NAND_DEVICE     1
 470
 471 #define SECTORSIZE              512
 472 #define ADDR_COLUMN             1
 473 #define ADDR_PAGE               2
 474 #define ADDR_COLUMN_PAGE        3
 475 #define NAND_ChipID_UNKNOWN     0x00
 476 #define NAND_MAX_FLOORS         1
 477 #define NAND_MAX_CHIPS          1
 478
 479 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
 480 #define NAND_DISABLE_CE(nand) \
 481         do { \
 482                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
 483         } while(0)
 484
 485 #define NAND_ENABLE_CE(nand) \
 486         do { \
 487                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
 488         } while(0)
 489
 490 #define NAND_CTL_CLRALE(nandptr) \
 491         do { \
 492                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
 493         } while(0)
 494
 495 #define NAND_CTL_SETALE(nandptr) \
 496         do { \
 497                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
 498         } while(0)
 499
 500 #define NAND_CTL_CLRCLE(nandptr) \
 501         do { \
 502                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
 503         } while(0)
 504
 505 #define NAND_CTL_SETCLE(nandptr) \
 506         do { \
 507                 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
 508         } while(0)
 509
 510 #define NAND_WAIT_READY(nand) \
 511         do { \
 512                 while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
 513                         ; \
 514         } while (0)
 515
 516 #define WRITE_NAND_COMMAND(d, adr) \
 517         do { \
 518                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 519         } while(0)
 520
 521 #define WRITE_NAND_ADDRESS(d, adr) \
 522         do { \
 523                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 524         } while(0)
 525
 526 #define WRITE_NAND(d, adr) \
 527         do { \
 528                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 529         } while(0)
 530
 531 #define READ_NAND(adr) \
 532         ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
 533
 534 /*****************************************************************************/
 535
 536 #define STATUS_LED_BIT          0x00000008              /* bit 28 */
 537 #define STATUS_LED_PERIOD       (CFG_HZ / 2)
 538 #define STATUS_LED_STATE        STATUS_LED_BLINKING
 539
 540 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 541 #define STATUS_LED_BOOT         0               /* LED 0 used for boot status */
 542
 543 #ifndef __ASSEMBLY__
 544
 545 /* LEDs */
 546
 547 /* led_id_t is unsigned int mask */
 548 typedef unsigned int led_id_t;
 549
 550 #define __led_toggle(_msk) \
 551         do { \
 552                 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
 553         } while(0)
 554
 555 #define __led_set(_msk, _st) \
 556         do { \
 557                 if ((_st)) \
 558                         ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
 559                 else \
 560                         ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
 561         } while(0)
 562
 563 #define __led_init(msk, st) __led_set(msk, st)
 564
 565 #endif
 566
 567 /***********************************************************************************************************
 568
 569    Pin definitions:
 570
 571  +------+----------------+--------+------------------------------------------------------------
 572  |  #   | Name           | Type   | Comment
 573  +------+----------------+--------+------------------------------------------------------------
 574  | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
 575  | PA7  | DSP_INT        | Output | DSP interrupt
 576  | PA10 | DSP_RESET      | Output | DSP reset
 577  | PA14 | USBOE          | Output | USB (1)
 578  | PA15 | USBRXD         | Output | USB (1)
 579  | PB19 | BT_RTS         | Output | Bluetooth (0)
 580  | PB23 | BT_CTS         | Output | Bluetooth (0)
 581  | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
 582  | PB27 | SPICS_DISP     | Output | Display chip select
 583  | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
 584  | PB29 | SPI_TXD        | Output | SPI Data Tx
 585  | PB30 | SPI_CLK        | Output | SPI Clock
 586  | PC10 | DISPA0         | Output | Display A0
 587  | PC11 | BACKLIGHT      | Output | Display backlit
 588  | PC12 | SPI2RXD        | Input  | 2nd SPI RXD
 589  | PC13 | SPI2TXD        | Output | 2nd SPI TXD
 590  | PC15 | SPI2CLK        | Output | 2nd SPI CLK
 591  | PE17 | F_ALE          | Output | NAND F_ALE
 592  | PE18 | F_CLE          | Output | NAND F_CLE
 593  | PE20 | F_CE           | Output | NAND F_CE
 594  | PE24 | SPICS_SCOUT    | Output | Codec chip select
 595  | PE27 | SPICS_ER       | Output | External serial register CS
 596  | PE28 | LEDIO1         | Output | LED
 597  | PE29 | LEDIO2         | Output | LED hook for A (TA2)
 598  | PE30 | LEDIO3         | Output | LED hook for A (TA2)
 599  | PE31 | F_RY_BY        | Input  | NAND F_RY_BY
 600  +------+----------------+--------+---------------------------------------------------
 601
 602  Chip selects:
 603
 604  +------+----------------+------------------------------------------------------------
 605  |  #   | Name           | Comment
 606  +------+----------------+------------------------------------------------------------
 607  | CS0  | CS0            | Boot flash
 608  | CS1  | CS_FLASH       | NAND flash
 609  | CS2  | CS_DSP         | DSP
 610  | CS3  | DCS_DRAM       | DRAM
 611  +------+----------------+------------------------------------------------------------
 612
 613  Interrupts:
 614
 615  +------+----------------+------------------------------------------------------------
 616  |  #   | Name           | Comment
 617  +------+----------------+------------------------------------------------------------
 618  | IRQ1 | IRQ_DSP        | DSP interrupt
 619  | IRQ3 | S_INTER        | DUSLIC ???
 620  | IRQ4 | F_RY_BY        | NAND
 621  | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
 622  +------+----------------+------------------------------------------------------------
 623
 624  Interrupts on PCMCIA pins:
 625
 626  +------+----------------+------------------------------------------------------------
 627  |  #   | Name           | Comment
 628  +------+----------------+------------------------------------------------------------
 629  | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
 630  | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
 631  | IP_A2| RMII1_MDINT    | PHY interrupt for #1
 632  | IP_A3| RMII2_MDINT    | PHY interrupt for #2
 633  +------+----------------+------------------------------------------------------------
 634
 635 *************************************************************************************************/
 636
 637 #define CONFIG_SED156X                  1       /* use SED156X */
 638 #define CONFIG_SED156X_PG12864Q         1       /* type of display used */
 639
 640 /* serial interfacing macros */
 641
 642 #define SED156X_SPI_RXD_PORT    (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
 643 #define SED156X_SPI_RXD_MASK    0x00000008
 644
 645 #define SED156X_SPI_TXD_PORT    (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
 646 #define SED156X_SPI_TXD_MASK    0x00000004
 647
 648 #define SED156X_SPI_CLK_PORT    (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
 649 #define SED156X_SPI_CLK_MASK    0x00000002
 650
 651 #define SED156X_CS_PORT         (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
 652 #define SED156X_CS_MASK         0x00000010
 653
 654 #define SED156X_A0_PORT         (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
 655 #define SED156X_A0_MASK         0x0020
 656
 657 /*************************************************************************************************/
 658
 659 #define CFG_CONSOLE_IS_IN_ENV           1
 660 #define CFG_CONSOLE_OVERWRITE_ROUTINE   1
 661 #define CFG_CONSOLE_ENV_OVERWRITE       1
 662
 663 /*************************************************************************************************/
 664
 665 /* use board specific hardware */
 666 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 667 #define CONFIG_HW_WATCHDOG
 668 #define CONFIG_SHOW_ACTIVITY
 669
 670 /*************************************************************************************************/
 671
 672 /* phone console configuration */
 673
 674 #define PHONE_CONSOLE_POLL_HZ           (CFG_HZ/200)    /* poll every 5ms */
 675
 676 /*************************************************************************************************/
 677
 678 #define CONFIG_CDP_DEVICE_ID            20
 679 #define CONFIG_CDP_DEVICE_ID_PREFIX     "NP"    /* netphone */
 680 #define CONFIG_CDP_PORT_ID              "eth%d"
 681 #define CONFIG_CDP_CAPABILITIES         0x00000010
 682 #define CONFIG_CDP_VERSION              "u-boot" " " __DATE__ " " __TIME__
 683 #define CONFIG_CDP_PLATFORM             "Intracom NetPhone"
 684 #define CONFIG_CDP_TRIGGER              0x20020001
 685 #define CONFIG_CDP_POWER_CONSUMPTION    4300    /* 90 mA @ 48V */
 686 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE  0x01    /* ipphone */
 687
 688 /*************************************************************************************************/
 689
 690 #define CONFIG_AUTO_COMPLETE    1
 691
 692 /*************************************************************************************************/
 693
 694 #endif  /* __CONFIG_H */