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* Modify KUP4X board configuration to use SL811 driver for USB memory
[people/ms/u-boot.git] / include / configs / NETPHONE.h
1 /*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29 #ifndef __CONFIG_H
30 #define __CONFIG_H
31
32 #if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
33 #error Unsupported CONFIG_NETPHONE version
34 #endif
35
36 /*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41 #define CONFIG_MPC870 1 /* This is a MPC885 CPU */
42 #define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
43
44 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45 #undef CONFIG_8xx_CONS_SMC2
46 #undef CONFIG_8xx_CONS_NONE
47
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49
50 /* #define CONFIG_XIN 10000000 */
51 #define CONFIG_XIN 50000000
52 #define MPC8XX_HZ 120000000
53 /* #define MPC8XX_HZ 66666666 */
54
55 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56
57 #if 0
58 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59 #else
60 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #endif
62
63 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
64
65 #define CONFIG_PREBOOT "echo;"
66
67 #undef CONFIG_BOOTARGS
68 #define CONFIG_BOOTCOMMAND \
69 "tftpboot; " \
70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
72 "bootm"
73
74 #define CONFIG_AUTOSCRIPT
75 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
76 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
77
78 #undef CONFIG_WATCHDOG /* watchdog disabled */
79
80 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
82 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
83 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
84
85 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
86
87 #undef CONFIG_MAC_PARTITION
88 #undef CONFIG_DOS_PARTITION
89
90 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
91
92 #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
93 #define FEC_ENET 1 /* eth.c needs it that way... */
94 #undef CFG_DISCOVER_PHY
95 #define CONFIG_MII 1
96 #define CONFIG_RMII 1 /* use RMII interface */
97
98 #define CONFIG_ETHER_ON_FEC1 1
99 #define CONFIG_FEC1_PHY 8 /* phy address of FEC */
100 #define CONFIG_FEC1_PHY_NORXERR 1
101
102 #define CONFIG_ETHER_ON_FEC2 1
103 #define CONFIG_FEC2_PHY 4
104 #define CONFIG_FEC2_PHY_NORXERR 1
105
106 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
107
108 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
109 CFG_CMD_NAND | \
110 CFG_CMD_DHCP | \
111 CFG_CMD_PING | \
112 CFG_CMD_MII | \
113 CFG_CMD_CDP \
114 )
115
116 #define CONFIG_BOARD_EARLY_INIT_F 1
117 #define CONFIG_MISC_INIT_R
118
119 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120 #include <cmd_confdefs.h>
121
122 /*
123 * Miscellaneous configurable options
124 */
125 #define CFG_LONGHELP /* undef to save memory */
126 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
127
128 #define CFG_HUSH_PARSER 1
129 #define CFG_PROMPT_HUSH_PS2 "> "
130
131 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
132 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
133 #else
134 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
135 #endif
136 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
137 #define CFG_MAXARGS 16 /* max number of command args */
138 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
139
140 #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
141 #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
142
143 #define CFG_LOAD_ADDR 0x100000 /* default load address */
144
145 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
146
147 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
148
149 /*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
154 /*-----------------------------------------------------------------------
155 * Internal Memory Mapped Register
156 */
157 #define CFG_IMMR 0xFF000000
158
159 /*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
161 */
162 #define CFG_INIT_RAM_ADDR CFG_IMMR
163 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
164 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
165 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
166 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
167
168 /*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
171 * Please note that CFG_SDRAM_BASE _must_ start at 0
172 */
173 #define CFG_SDRAM_BASE 0x00000000
174 #define CFG_FLASH_BASE 0x40000000
175 #if defined(DEBUG)
176 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177 #else
178 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
179 #endif
180 #define CFG_MONITOR_BASE CFG_FLASH_BASE
181 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
182 #if CONFIG_NETPHONE_VERSION == 2
183 #define CFG_FLASH_BASE4 0x40080000
184 #endif
185
186 #define CFG_RESET_ADDRESS 0x80000000
187
188 /*
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
192 */
193 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
194
195 /*-----------------------------------------------------------------------
196 * FLASH organization
197 */
198 #if CONFIG_NETPHONE_VERSION == 1
199 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
200 #elif CONFIG_NETPHONE_VERSION == 2
201 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
202 #endif
203 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
204
205 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
206 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
207
208 #define CFG_ENV_IS_IN_FLASH 1
209 #define CFG_ENV_SECT_SIZE 0x10000
210
211 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
212 #define CFG_ENV_OFFSET 0
213 #define CFG_ENV_SIZE 0x4000
214
215 #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
216 #define CFG_ENV_OFFSET_REDUND 0
217 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
218
219 /*-----------------------------------------------------------------------
220 * Cache Configuration
221 */
222 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
223 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
224 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
225 #endif
226
227 /*-----------------------------------------------------------------------
228 * SYPCR - System Protection Control 11-9
229 * SYPCR can only be written once after reset!
230 *-----------------------------------------------------------------------
231 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
232 */
233 #if defined(CONFIG_WATCHDOG)
234 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
235 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
236 #else
237 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
238 #endif
239
240 /*-----------------------------------------------------------------------
241 * SIUMCR - SIU Module Configuration 11-6
242 *-----------------------------------------------------------------------
243 * PCMCIA config., multi-function pin tri-state
244 */
245 #ifndef CONFIG_CAN_DRIVER
246 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
247 #else /* we must activate GPL5 in the SIUMCR for CAN */
248 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
249 #endif /* CONFIG_CAN_DRIVER */
250
251 /*-----------------------------------------------------------------------
252 * TBSCR - Time Base Status and Control 11-26
253 *-----------------------------------------------------------------------
254 * Clear Reference Interrupt Status, Timebase freezing enabled
255 */
256 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
257
258 /*-----------------------------------------------------------------------
259 * RTCSC - Real-Time Clock Status and Control Register 11-27
260 *-----------------------------------------------------------------------
261 */
262 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263
264 /*-----------------------------------------------------------------------
265 * PISCR - Periodic Interrupt Status and Control 11-31
266 *-----------------------------------------------------------------------
267 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268 */
269 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
270
271 /*-----------------------------------------------------------------------
272 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
273 *-----------------------------------------------------------------------
274 * Reset PLL lock status sticky bit, timer expired status bit and timer
275 * interrupt status bit
276 *
277 */
278
279 #if CONFIG_XIN == 10000000
280
281 #if MPC8XX_HZ == 120000000
282 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
283 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
284 PLPRCR_TEXPS)
285 #elif MPC8XX_HZ == 100000000
286 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
287 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
288 PLPRCR_TEXPS)
289 #elif MPC8XX_HZ == 50000000
290 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
291 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
292 PLPRCR_TEXPS)
293 #elif MPC8XX_HZ == 25000000
294 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
295 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
296 PLPRCR_TEXPS)
297 #elif MPC8XX_HZ == 40000000
298 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
299 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
300 PLPRCR_TEXPS)
301 #elif MPC8XX_HZ == 75000000
302 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
303 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
304 PLPRCR_TEXPS)
305 #else
306 #error unsupported CPU freq for XIN = 10MHz
307 #endif
308
309 #elif CONFIG_XIN == 50000000
310
311 #if MPC8XX_HZ == 120000000
312 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
313 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
314 PLPRCR_TEXPS)
315 #elif MPC8XX_HZ == 100000000
316 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
317 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
318 PLPRCR_TEXPS)
319 #elif MPC8XX_HZ == 66666666
320 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
321 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
322 PLPRCR_TEXPS)
323 #else
324 #error unsupported CPU freq for XIN = 50MHz
325 #endif
326
327 #else
328
329 #error unsupported XIN freq
330 #endif
331
332
333 /*
334 *-----------------------------------------------------------------------
335 * SCCR - System Clock and reset Control Register 15-27
336 *-----------------------------------------------------------------------
337 * Set clock output, timebase and RTC source and divider,
338 * power management and some other internal clocks
339 */
340
341 #define SCCR_MASK SCCR_EBDF11
342 #if MPC8XX_HZ > 66666666
343 #define CFG_SCCR (SCCR_TBS | \
344 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
345 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
346 SCCR_DFALCD00 | SCCR_EBDF01)
347 #else
348 #define CFG_SCCR (SCCR_TBS | \
349 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
350 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
351 SCCR_DFALCD00)
352 #endif
353
354 /*-----------------------------------------------------------------------
355 *
356 *-----------------------------------------------------------------------
357 *
358 */
359 /*#define CFG_DER 0x2002000F*/
360 #define CFG_DER 0
361
362 /*
363 * Init Memory Controller:
364 *
365 * BR0/1 and OR0/1 (FLASH)
366 */
367
368 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369
370 /* used to re-map FLASH both when starting from SRAM or FLASH:
371 * restrict access enough to keep SRAM working (if any)
372 * but not too much to meddle with FLASH accesses
373 */
374 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
375 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
376
377 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
378 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
379
380 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
381 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
382 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
383
384 #if CONFIG_NETPHONE_VERSION == 2
385
386 #define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
387
388 #define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
389 #define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
390 #define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
391
392 #endif
393
394 /*
395 * BR3 and OR3 (SDRAM)
396 *
397 */
398 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
399 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
400
401 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
402 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
403
404 #define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
405 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
406
407 /*
408 * Memory Periodic Timer Prescaler
409 */
410
411 /*
412 * Memory Periodic Timer Prescaler
413 *
414 * The Divider for PTA (refresh timer) configuration is based on an
415 * example SDRAM configuration (64 MBit, one bank). The adjustment to
416 * the number of chip selects (NCS) and the actually needed refresh
417 * rate is done by setting MPTPR.
418 *
419 * PTA is calculated from
420 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
421 *
422 * gclk CPU clock (not bus clock!)
423 * Trefresh Refresh cycle * 4 (four word bursts used)
424 *
425 * 4096 Rows from SDRAM example configuration
426 * 1000 factor s -> ms
427 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
428 * 4 Number of refresh cycles per period
429 * 64 Refresh cycle in ms per number of rows
430 * --------------------------------------------
431 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
432 *
433 * 50 MHz => 50.000.000 / Divider = 98
434 * 66 Mhz => 66.000.000 / Divider = 129
435 * 80 Mhz => 80.000.000 / Divider = 156
436 */
437
438 #define CFG_MAMR_PTA 234
439
440 /*
441 * For 16 MBit, refresh rates could be 31.3 us
442 * (= 64 ms / 2K = 125 / quad bursts).
443 * For a simpler initialization, 15.6 us is used instead.
444 *
445 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
446 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
447 */
448 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
449 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
450
451 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
452 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
453 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
454
455 /*
456 * MAMR settings for SDRAM
457 */
458
459 /* 8 column SDRAM */
460 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
461 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
462 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
463
464 /* 9 column SDRAM */
465 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
466 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
468
469 /*
470 * Internal Definitions
471 *
472 * Boot Flags
473 */
474 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
475 #define BOOTFLAG_WARM 0x02 /* Software reboot */
476
477 #define CONFIG_ARTOS /* include ARTOS support */
478
479 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
480
481 /****************************************************************/
482
483 #define DSP_SIZE 0x00010000 /* 64K */
484 #define NAND_SIZE 0x00010000 /* 64K */
485
486 #define DSP_BASE 0xF1000000
487 #define NAND_BASE 0xF1010000
488
489 /****************************************************************/
490
491 /* NAND */
492 #define CFG_NAND_BASE NAND_BASE
493 #define CONFIG_MTD_NAND_ECC_JFFS2
494
495 #define CFG_MAX_NAND_DEVICE 1
496
497 #define SECTORSIZE 512
498 #define ADDR_COLUMN 1
499 #define ADDR_PAGE 2
500 #define ADDR_COLUMN_PAGE 3
501 #define NAND_ChipID_UNKNOWN 0x00
502 #define NAND_MAX_FLOORS 1
503 #define NAND_MAX_CHIPS 1
504
505 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
506 #define NAND_DISABLE_CE(nand) \
507 do { \
508 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
509 } while(0)
510
511 #define NAND_ENABLE_CE(nand) \
512 do { \
513 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
514 } while(0)
515
516 #define NAND_CTL_CLRALE(nandptr) \
517 do { \
518 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
519 } while(0)
520
521 #define NAND_CTL_SETALE(nandptr) \
522 do { \
523 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
524 } while(0)
525
526 #define NAND_CTL_CLRCLE(nandptr) \
527 do { \
528 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
529 } while(0)
530
531 #define NAND_CTL_SETCLE(nandptr) \
532 do { \
533 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
534 } while(0)
535
536 #if CONFIG_NETPHONE_VERSION == 1
537 #define NAND_WAIT_READY(nand) \
538 do { \
539 int _tries = 0; \
540 while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
541 if (++_tries > 100000) \
542 break; \
543 } while (0)
544 #elif CONFIG_NETPHONE_VERSION == 2
545 #define NAND_WAIT_READY(nand) \
546 do { \
547 int _tries = 0; \
548 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
549 if (++_tries > 100000) \
550 break; \
551 } while (0)
552 #endif
553
554 #define WRITE_NAND_COMMAND(d, adr) \
555 do { \
556 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
557 } while(0)
558
559 #define WRITE_NAND_ADDRESS(d, adr) \
560 do { \
561 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
562 } while(0)
563
564 #define WRITE_NAND(d, adr) \
565 do { \
566 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
567 } while(0)
568
569 #define READ_NAND(adr) \
570 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
571
572 /*****************************************************************************/
573
574 #if CONFIG_NETPHONE_VERSION == 1
575 #define STATUS_LED_BIT 0x00000008 /* bit 28 */
576 #elif CONFIG_NETPHONE_VERSION == 2
577 #define STATUS_LED_BIT 0x00000080 /* bit 24 */
578 #endif
579
580 #define STATUS_LED_PERIOD (CFG_HZ / 2)
581 #define STATUS_LED_STATE STATUS_LED_BLINKING
582
583 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
584 #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
585
586 #ifndef __ASSEMBLY__
587
588 /* LEDs */
589
590 /* led_id_t is unsigned int mask */
591 typedef unsigned int led_id_t;
592
593 #define __led_toggle(_msk) \
594 do { \
595 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
596 } while(0)
597
598 #define __led_set(_msk, _st) \
599 do { \
600 if ((_st)) \
601 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
602 else \
603 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
604 } while(0)
605
606 #define __led_init(msk, st) __led_set(msk, st)
607
608 #endif
609
610 /***********************************************************************************************************
611
612 ----------------------------------------------------------------------------------------------
613
614 (V1) version 1 of the board
615 (V2) version 2 of the board
616
617 ----------------------------------------------------------------------------------------------
618
619 Pin definitions:
620
621 +------+----------------+--------+------------------------------------------------------------
622 | # | Name | Type | Comment
623 +------+----------------+--------+------------------------------------------------------------
624 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
625 | PA7 | DSP_INT | Output | DSP interrupt
626 | PA10 | DSP_RESET | Output | DSP reset
627 | PA14 | USBOE | Output | USB (1)
628 | PA15 | USBRXD | Output | USB (1)
629 | PB19 | BT_RTS | Output | Bluetooth (0)
630 | PB23 | BT_CTS | Output | Bluetooth (0)
631 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
632 | PB27 | SPICS_DISP | Output | Display chip select
633 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
634 | PB29 | SPI_TXD | Output | SPI Data Tx
635 | PB30 | SPI_CLK | Output | SPI Clock
636 | PC10 | DISPA0 | Output | Display A0
637 | PC11 | BACKLIGHT | Output | Display backlit
638 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
639 | | IO_RESET | Output | (V2) General I/O reset
640 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
641 | | HOOK | Input | (V2) Hook input interrupt
642 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
643 | | F_RY_BY | Input | (V2) NAND F_RY_BY
644 | PE17 | F_ALE | Output | NAND F_ALE
645 | PE18 | F_CLE | Output | NAND F_CLE
646 | PE20 | F_CE | Output | NAND F_CE
647 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
648 | | LED | Output | (V2) LED
649 | PE27 | SPICS_ER | Output | External serial register CS
650 | PE28 | LEDIO1 | Output | (V1) LED
651 | | BKBR1 | Input | (V2) Keyboard input scan
652 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
653 | | BKBR2 | Input | (V2) Keyboard input scan
654 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
655 | | BKBR3 | Input | (V2) Keyboard input scan
656 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
657 | | BKBR4 | Input | (V2) Keyboard input scan
658 +------+----------------+--------+---------------------------------------------------
659
660 ----------------------------------------------------------------------------------------------
661
662 Serial register input:
663
664 +------+----------------+------------------------------------------------------------
665 | # | Name | Comment
666 +------+----------------+------------------------------------------------------------
667 | 0 | BKBR1 | (V1) Keyboard input scan
668 | 1 | BKBR3 | (V1) Keyboard input scan
669 | 2 | BKBR4 | (V1) Keyboard input scan
670 | 3 | BKBR2 | (V1) Keyboard input scan
671 | 4 | HOOK | (V1) Hook switch
672 | 5 | BT_LINK | (V1) Bluetooth link status
673 | 6 | HOST_WAKE | (V1) Bluetooth host wake up
674 | 7 | OK_ETH | (V1) Cisco inline power OK status
675 +------+----------------+------------------------------------------------------------
676
677 ----------------------------------------------------------------------------------------------
678
679 Serial register output:
680
681 +------+----------------+------------------------------------------------------------
682 | # | Name | Comment
683 +------+----------------+------------------------------------------------------------
684 | 0 | KEY1 | Keyboard output scan
685 | 1 | KEY2 | Keyboard output scan
686 | 2 | KEY3 | Keyboard output scan
687 | 3 | KEY4 | Keyboard output scan
688 | 4 | KEY5 | Keyboard output scan
689 | 5 | KEY6 | Keyboard output scan
690 | 6 | KEY7 | Keyboard output scan
691 | 7 | BT_WAKE | Bluetooth wake up
692 +------+----------------+------------------------------------------------------------
693
694 ----------------------------------------------------------------------------------------------
695
696 Chip selects:
697
698 +------+----------------+------------------------------------------------------------
699 | # | Name | Comment
700 +------+----------------+------------------------------------------------------------
701 | CS0 | CS0 | Boot flash
702 | CS1 | CS_FLASH | NAND flash
703 | CS2 | CS_DSP | DSP
704 | CS3 | DCS_DRAM | DRAM
705 | CS4 | CS_FLASH2 | (V2) 2nd flash
706 +------+----------------+------------------------------------------------------------
707
708 ----------------------------------------------------------------------------------------------
709
710 Interrupts:
711
712 +------+----------------+------------------------------------------------------------
713 | # | Name | Comment
714 +------+----------------+------------------------------------------------------------
715 | IRQ1 | IRQ_DSP | DSP interrupt
716 | IRQ3 | S_INTER | DUSLIC ???
717 | IRQ4 | F_RY_BY | NAND
718 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
719 +------+----------------+------------------------------------------------------------
720
721 ----------------------------------------------------------------------------------------------
722
723 Interrupts on PCMCIA pins:
724
725 +------+----------------+------------------------------------------------------------
726 | # | Name | Comment
727 +------+----------------+------------------------------------------------------------
728 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
729 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
730 | IP_A2| RMII1_MDINT | PHY interrupt for #1
731 | IP_A3| RMII2_MDINT | PHY interrupt for #2
732 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
733 | IP_A6| OK_ETH | (V2) Cisco inline power OK
734 +------+----------------+------------------------------------------------------------
735
736 *************************************************************************************************/
737
738 #define CONFIG_SED156X 1 /* use SED156X */
739 #define CONFIG_SED156X_PG12864Q 1 /* type of display used */
740
741 /* serial interfacing macros */
742
743 #define SED156X_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
744 #define SED156X_SPI_RXD_MASK 0x00000008
745
746 #define SED156X_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
747 #define SED156X_SPI_TXD_MASK 0x00000004
748
749 #define SED156X_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
750 #define SED156X_SPI_CLK_MASK 0x00000002
751
752 #define SED156X_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
753 #define SED156X_CS_MASK 0x00000010
754
755 #define SED156X_A0_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
756 #define SED156X_A0_MASK 0x0020
757
758 /*************************************************************************************************/
759
760 #define CFG_CONSOLE_IS_IN_ENV 1
761 #define CFG_CONSOLE_OVERWRITE_ROUTINE 1
762 #define CFG_CONSOLE_ENV_OVERWRITE 1
763
764 /*************************************************************************************************/
765
766 /* use board specific hardware */
767 #undef CONFIG_WATCHDOG /* watchdog disabled */
768 #define CONFIG_HW_WATCHDOG
769 #define CONFIG_SHOW_ACTIVITY
770
771 /*************************************************************************************************/
772
773 /* phone console configuration */
774
775 #define PHONE_CONSOLE_POLL_HZ (CFG_HZ/200) /* poll every 5ms */
776
777 /*************************************************************************************************/
778
779 #define CONFIG_CDP_DEVICE_ID 20
780 #define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */
781 #define CONFIG_CDP_PORT_ID "eth%d"
782 #define CONFIG_CDP_CAPABILITIES 0x00000010
783 #define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__
784 #define CONFIG_CDP_PLATFORM "Intracom NetPhone"
785 #define CONFIG_CDP_TRIGGER 0x20020001
786 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
787 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */
788
789 /*************************************************************************************************/
790
791 #define CONFIG_AUTO_COMPLETE 1
792
793 /*************************************************************************************************/
794
795 #define CONFIG_CRC32_VERIFY 1
796
797 /*************************************************************************************************/
798
799 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
800
801 /*************************************************************************************************/
802 #endif /* __CONFIG_H */
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