include/configs/NETVIA.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26  * U-Boot port on NetVia board
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  38 #define CONFIG_NETVIA           1       /* ...on a NetVia board         */
  39
  40 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #else
  45 #define CONFIG_8xx_CONS_NONE
  46 #define CONFIG_MAX3100_SERIAL
  47 #endif
  48
  49 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  50
  51 #define CONFIG_XIN              10000000
  52 #define CONFIG_8xx_GCLK_FREQ    80000000
  53
  54 #if 0
  55 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  56 #else
  57 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  58 #endif
  59
  60 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  61
  62 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  63
  64 #undef  CONFIG_BOOTARGS
  65 #define CONFIG_BOOTCOMMAND                                                      \
  66         "tftpboot; "                                                            \
  67         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  68         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  69         "bootm"
  70
  71 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  72 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  73
  74 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  75
  76 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  77
  78 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
  79 #define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
  80 #endif
  81
  82 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  83
  84 /*
  85  * BOOTP options
  86  */
  87 #define CONFIG_BOOTP_SUBNETMASK
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90 #define CONFIG_BOOTP_BOOTPATH
  91 #define CONFIG_BOOTP_BOOTFILESIZE
  92 #define CONFIG_BOOTP_NISDOMAIN
  93
  94
  95 #undef CONFIG_MAC_PARTITION
  96 #undef CONFIG_DOS_PARTITION
  97
  98 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  99
 100
 101 /*
 102  * Command line configuration.
 103  */
 104 #include <config_cmd_default.h>
 105
 106 #define CONFIG_CMD_DHCP
 107 #define CONFIG_CMD_PING
 108
 109 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 110 #define CONFIG_CMD_NAND
 111 #endif
 112
 113
 114 #define CONFIG_BOARD_EARLY_INIT_F 1
 115 #define CONFIG_MISC_INIT_R
 116
 117 /*
 118  * Miscellaneous configurable options
 119  */
 120 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 121 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 124 #else
 125 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 126 #endif
 127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 128 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 129 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 130
 131 #define CONFIG_SYS_MEMTEST_START        0x0300000       /* memtest works on     */
 132 #define CONFIG_SYS_MEMTEST_END          0x0700000       /* 3 ... 7 MB in DRAM   */
 133
 134 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 135
 136 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 137
 138 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 139
 140 /*
 141  * Low Level Configuration Settings
 142  * (address mappings, register initial values, etc.)
 143  * You should know what you are doing if you make changes here.
 144  */
 145 /*-----------------------------------------------------------------------
 146  * Internal Memory Mapped Register
 147  */
 148 #define CONFIG_SYS_IMMR         0xFF000000
 149
 150 /*-----------------------------------------------------------------------
 151  * Definitions for initial stack pointer and data area (in DPRAM)
 152  */
 153 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 154 #define CONFIG_SYS_INIT_RAM_END 0x3000  /* End of used area in DPRAM    */
 155 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 156 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 157 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 158
 159 /*-----------------------------------------------------------------------
 160  * Start addresses for the final memory configuration
 161  * (Set up by the startup code)
 162  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 163  */
 164 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 165 #define CONFIG_SYS_FLASH_BASE           0x40000000
 166 #if defined(DEBUG)
 167 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 168 #else
 169 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 170 #endif
 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 172 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 173
 174 /*
 175  * For booting Linux, the board info and command line data
 176  * have to be in the first 8 MB of memory, since this is
 177  * the maximum mapped by the Linux kernel during initialization.
 178  */
 179 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 180
 181 /*-----------------------------------------------------------------------
 182  * FLASH organization
 183  */
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 185 #define CONFIG_SYS_MAX_FLASH_SECT       8       /* max number of sectors on one chip    */
 186
 187 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 188 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 189
 190 #define CONFIG_ENV_IS_IN_FLASH  1
 191 #define CONFIG_ENV_SECT_SIZE    0x10000
 192
 193 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x60000)
 194 #define CONFIG_ENV_OFFSET               0
 195 #define CONFIG_ENV_SIZE         0x4000
 196
 197 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_SYS_FLASH_BASE + 0x70000)
 198 #define CONFIG_ENV_OFFSET_REDUND        0
 199 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 200
 201 /*-----------------------------------------------------------------------
 202  * Cache Configuration
 203  */
 204 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 205 #if defined(CONFIG_CMD_KGDB)
 206 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 207 #endif
 208
 209 /*-----------------------------------------------------------------------
 210  * SYPCR - System Protection Control                            11-9
 211  * SYPCR can only be written once after reset!
 212  *-----------------------------------------------------------------------
 213  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 214  */
 215 #if defined(CONFIG_WATCHDOG)
 216 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 217                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 218 #else
 219 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 220 #endif
 221
 222 /*-----------------------------------------------------------------------
 223  * SIUMCR - SIU Module Configuration                            11-6
 224  *-----------------------------------------------------------------------
 225  * PCMCIA config., multi-function pin tri-state
 226  */
 227 #ifndef CONFIG_CAN_DRIVER
 228 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 229 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 230 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 231 #endif  /* CONFIG_CAN_DRIVER */
 232
 233 /*-----------------------------------------------------------------------
 234  * TBSCR - Time Base Status and Control                         11-26
 235  *-----------------------------------------------------------------------
 236  * Clear Reference Interrupt Status, Timebase freezing enabled
 237  */
 238 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 239
 240 /*-----------------------------------------------------------------------
 241  * RTCSC - Real-Time Clock Status and Control Register          11-27
 242  *-----------------------------------------------------------------------
 243  */
 244 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 245
 246 /*-----------------------------------------------------------------------
 247  * PISCR - Periodic Interrupt Status and Control                11-31
 248  *-----------------------------------------------------------------------
 249  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 250  */
 251 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 252
 253 /*-----------------------------------------------------------------------
 254  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 255  *-----------------------------------------------------------------------
 256  * Reset PLL lock status sticky bit, timer expired status bit and timer
 257  * interrupt status bit
 258  *
 259  *
 260  *-----------------------------------------------------------------------
 261  * SCCR - System Clock and reset Control Register               15-27
 262  *-----------------------------------------------------------------------
 263  * Set clock output, timebase and RTC source and divider,
 264  * power management and some other internal clocks
 265  */
 266
 267 #define SCCR_MASK       SCCR_EBDF11
 268
 269 #if CONFIG_8xx_GCLK_FREQ == 50000000
 270
 271 #define CONFIG_SYS_PLPRCR       ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 272 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 273                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 274                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 275                          SCCR_DFALCD00)
 276
 277 #elif CONFIG_8xx_GCLK_FREQ == 80000000
 278
 279 #define CONFIG_SYS_PLPRCR       ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 280 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 281                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 282                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 283                          SCCR_DFALCD00 | SCCR_EBDF01)
 284
 285 #endif
 286
 287 /*-----------------------------------------------------------------------
 288  *
 289  *-----------------------------------------------------------------------
 290  *
 291  */
 292 /*#define       CONFIG_SYS_DER  0x2002000F*/
 293 #define CONFIG_SYS_DER  0
 294
 295 /*
 296  * Init Memory Controller:
 297  *
 298  * BR0/1 and OR0/1 (FLASH)
 299  */
 300
 301 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 302
 303 /* used to re-map FLASH both when starting from SRAM or FLASH:
 304  * restrict access enough to keep SRAM working (if any)
 305  * but not too much to meddle with FLASH accesses
 306  */
 307 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 308 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 309
 310 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 311 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 312
 313 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 314 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 315 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 316
 317 /*
 318  * BR3 and OR3 (SDRAM)
 319  *
 320  */
 321 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
 322 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 323
 324 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 325 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_CSNT_SAM | OR_G5LS)
 326
 327 #define CONFIG_SYS_OR3_PRELIM   ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
 328 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 329
 330 /*
 331  * Memory Periodic Timer Prescaler
 332  */
 333
 334 /* periodic timer for refresh */
 335 #define CONFIG_SYS_MAMR_PTA     208
 336
 337 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 338 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 339
 340 /*
 341  * MAMR settings for SDRAM
 342  */
 343
 344 /* 9 column SDRAM */
 345 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 346                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 347                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 348
 349 /*
 350  * Internal Definitions
 351  *
 352  * Boot Flags
 353  */
 354 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 355 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 356
 357 /* Ethernet at SCC2 */
 358 #define CONFIG_SCC2_ENET
 359
 360 /****************************************************************/
 361
 362 #define DSP_SIZE        0x00010000      /* 64K */
 363 #define FPGA_SIZE       0x00010000      /* 64K */
 364
 365 #define DSP0_BASE       0xF1000000
 366 #define DSP1_BASE       (DSP0_BASE + DSP_SIZE)
 367 #define FPGA_BASE       (DSP1_BASE + DSP_SIZE)
 368
 369 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 370
 371 #define ER_SIZE         0x00010000      /* 64K */
 372 #define ER_BASE         (FPGA_BASE + FPGA_SIZE)
 373
 374 #define NAND_SIZE       0x00010000      /* 64K */
 375 #define NAND_BASE       (ER_BASE + ER_SIZE)
 376
 377 #endif
 378
 379 /****************************************************************/
 380
 381 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 382
 383 #define STATUS_LED_BIT          0x00000001              /* bit 31 */
 384 #define STATUS_LED_PERIOD       (CONFIG_SYS_HZ / 2)
 385 #define STATUS_LED_STATE        STATUS_LED_BLINKING
 386
 387 #define STATUS_LED_BIT1         0x00000002              /* bit 30 */
 388 #define STATUS_LED_PERIOD1      (CONFIG_SYS_HZ / 2)
 389 #define STATUS_LED_STATE1       STATUS_LED_OFF
 390
 391 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 392 #define STATUS_LED_BOOT         0               /* LED 0 used for boot status */
 393
 394 #endif
 395
 396
 397 /*****************************************************************************/
 398
 399 #ifndef __ASSEMBLY__
 400
 401 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 402
 403 /* LEDs */
 404
 405 /* last value written to the external register; we cannot read back */
 406 extern unsigned int last_er_val;
 407
 408 /* led_id_t is unsigned long mask */
 409 typedef unsigned int led_id_t;
 410
 411 static inline void __led_init(led_id_t mask, int state)
 412 {
 413         unsigned int new_er_val;
 414
 415         if (state)
 416                 new_er_val = last_er_val & ~mask;
 417         else
 418                 new_er_val = last_er_val |  mask;
 419
 420         *(volatile unsigned int *)ER_BASE = new_er_val;
 421         last_er_val = new_er_val;
 422 }
 423
 424 static inline void __led_toggle(led_id_t mask)
 425 {
 426         unsigned int new_er_val;
 427
 428         new_er_val = last_er_val ^ mask;
 429         *(volatile unsigned int *)ER_BASE = new_er_val;
 430         last_er_val = new_er_val;
 431 }
 432
 433 static inline void __led_set(led_id_t mask, int state)
 434 {
 435         unsigned int new_er_val;
 436
 437         if (state)
 438                 new_er_val = last_er_val & ~mask;
 439         else
 440                 new_er_val = last_er_val |  mask;
 441
 442         *(volatile unsigned int *)ER_BASE = new_er_val;
 443         last_er_val = new_er_val;
 444 }
 445
 446 /* MAX3100 console */
 447 #define MAX3100_SPI_RXD_PORT    (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 448 #define MAX3100_SPI_RXD_BIT     0x00000008
 449
 450 #define MAX3100_SPI_TXD_PORT    (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 451 #define MAX3100_SPI_TXD_BIT     0x00000004
 452
 453 #define MAX3100_SPI_CLK_PORT    (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 454 #define MAX3100_SPI_CLK_BIT     0x00000002
 455
 456 #define MAX3100_CS_PORT         (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
 457 #define MAX3100_CS_BIT          0x0010
 458
 459 #endif
 460
 461 #endif
 462
 463 /*************************************************************************************************/
 464
 465 #endif  /* __CONFIG_H */