include/configs/NSCU.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  37 #define CONFIG_TQM855M          1       /* ...on a TQM8xxM module       */
  38 #define CONFIG_NSCU             1
  39
  40 #define CONFIG_8xx_CONS_SCC1    1       /* Console is on SMC1           */
  41
  42 #define CONFIG_66MHz            1       /* running at 66 MHz, 1:1 clock */
  43
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  45
  46 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  47
  48 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  49
  50 #define CONFIG_PREBOOT  "echo;" \
  51         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  52         "echo"
  53
  54 #undef  CONFIG_BOOTARGS
  55
  56 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  57         "netdev=eth0\0"                                                 \
  58         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  59                 "nfsroot=${serverip}:${rootpath}\0"                     \
  60         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  61         "addip=setenv bootargs ${bootargs} "                            \
  62                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  63                 ":${hostname}:${netdev}:off panic=1\0"                  \
  64         "flash_nfs=run nfsargs addip;"                                  \
  65                 "bootm ${kernel_addr}\0"                                \
  66         "flash_self=run ramargs addip;"                                 \
  67                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  68         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  69         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  70         "hostname=NSCU\0"                                               \
  71         "bootfile=${hostname}/uImage\0"                                 \
  72         "kernel_addr=40080000\0"                                        \
  73         "ramdisk_addr=40180000\0"                                       \
  74         "u-boot=${hostname}/u-image.bin\0"                              \
  75         "load=tftp 200000 ${u-boot}\0"                                  \
  76         "update=prot off 40000000 +${filesize};"                        \
  77                 "era 40000000 +${filesize};"                            \
  78                 "cp.b 200000 40000000 ${filesize};"                     \
  79                 "sete filesize;save\0"                                  \
  80         ""
  81 #define CONFIG_BOOTCOMMAND      "run flash_self"
  82
  83 #define CONFIG_MISC_INIT_R        1
  84
  85 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  86 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  87
  88 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  89
  90 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  91
  92 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  93
  94 /*
  95  * BOOTP options
  96  */
  97 #define CONFIG_BOOTP_SUBNETMASK
  98 #define CONFIG_BOOTP_GATEWAY
  99 #define CONFIG_BOOTP_HOSTNAME
 100 #define CONFIG_BOOTP_BOOTPATH
 101 #define CONFIG_BOOTP_BOOTFILESIZE
 102
 103
 104 #define CONFIG_MAC_PARTITION
 105 #define CONFIG_DOS_PARTITION
 106
 107 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 108
 109 #define CONFIG_ISP1362_USB              /* ISP1362 USB OTG controller   */
 110
 111
 112 /*
 113  * Command line configuration.
 114  */
 115 #include <config_cmd_default.h>
 116
 117 #define CONFIG_CMD_ASKENV
 118 #define CONFIG_CMD_DATE
 119 #define CONFIG_CMD_DHCP
 120 #define CONFIG_CMD_ELF
 121 #define CONFIG_CMD_IDE
 122 #define CONFIG_CMD_NFS
 123 #define CONFIG_CMD_SNTP
 124
 125
 126 #define CONFIG_NETCONSOLE
 127
 128
 129 /*
 130  * Miscellaneous configurable options
 131  */
 132 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 133 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 134
 135 #define CONFIG_CMDLINE_EDITING  1       /* add command line history
 136 */
 137 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 138 #ifdef  CONFIG_SYS_HUSH_PARSER
 139 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 140 #endif
 141
 142 #if defined(CONFIG_CMD_KGDB)
 143 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 144 #else
 145 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 146 #endif
 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 148 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 149 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 150
 151 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 152 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 153
 154 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 155
 156 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 157
 158 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 159
 160 /*
 161  * Low Level Configuration Settings
 162  * (address mappings, register initial values, etc.)
 163  * You should know what you are doing if you make changes here.
 164  */
 165 /*-----------------------------------------------------------------------
 166  * Internal Memory Mapped Register
 167  */
 168 #define CONFIG_SYS_IMMR         0xFFF00000
 169
 170 /*-----------------------------------------------------------------------
 171  * Definitions for initial stack pointer and data area (in DPRAM)
 172  */
 173 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 174 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 175 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 176 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 177 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 178
 179 /*-----------------------------------------------------------------------
 180  * Start addresses for the final memory configuration
 181  * (Set up by the startup code)
 182  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 183  */
 184 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 185 #define CONFIG_SYS_FLASH_BASE           0x40000000
 186 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 188 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200
 201 /* use CFI flash driver */
 202 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 203 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 204 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 205 #define CONFIG_SYS_FLASH_EMPTY_INFO
 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 209
 210 #define CONFIG_ENV_IS_IN_FLASH  1
 211 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 212 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 213
 214 /* Address and size of Redundant Environment Sector     */
 215 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 216 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 217
 218 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 219
 220 /*-----------------------------------------------------------------------
 221  * Hardware Information Block
 222  */
 223 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 224 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 225 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 226
 227 /*-----------------------------------------------------------------------
 228  * Cache Configuration
 229  */
 230 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 231 #if defined(CONFIG_CMD_KGDB)
 232 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 233 #endif
 234
 235 /*-----------------------------------------------------------------------
 236  * SYPCR - System Protection Control                            11-9
 237  * SYPCR can only be written once after reset!
 238  *-----------------------------------------------------------------------
 239  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 240  */
 241 #if defined(CONFIG_WATCHDOG)
 242 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 243                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 244 #else
 245 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 246 #endif
 247
 248 /*-----------------------------------------------------------------------
 249  * SIUMCR - SIU Module Configuration                            11-6
 250  *-----------------------------------------------------------------------
 251  * PCMCIA config., multi-function pin tri-state
 252  */
 253 #ifndef CONFIG_CAN_DRIVER
 254 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 255 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 256 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 257 #endif  /* CONFIG_CAN_DRIVER */
 258
 259 /*-----------------------------------------------------------------------
 260  * TBSCR - Time Base Status and Control                         11-26
 261  *-----------------------------------------------------------------------
 262  * Clear Reference Interrupt Status, Timebase freezing enabled
 263  */
 264 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 265
 266 /*-----------------------------------------------------------------------
 267  * RTCSC - Real-Time Clock Status and Control Register          11-27
 268  *-----------------------------------------------------------------------
 269  */
 270 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 271
 272 /*-----------------------------------------------------------------------
 273  * PISCR - Periodic Interrupt Status and Control                11-31
 274  *-----------------------------------------------------------------------
 275  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 276  */
 277 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 278
 279 /*-----------------------------------------------------------------------
 280  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 281  *-----------------------------------------------------------------------
 282  * Reset PLL lock status sticky bit, timer expired status bit and timer
 283  * interrupt status bit
 284  */
 285 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 286
 287 /*-----------------------------------------------------------------------
 288  * SCCR - System Clock and reset Control Register               15-27
 289  *-----------------------------------------------------------------------
 290  * Set clock output, timebase and RTC source and divider,
 291  * power management and some other internal clocks
 292  */
 293 #define SCCR_MASK       SCCR_EBDF11
 294 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 295                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 296                          SCCR_DFALCD00)
 297
 298 /*-----------------------------------------------------------------------
 299  * PCMCIA stuff
 300  *-----------------------------------------------------------------------
 301  *
 302  */
 303 /* NSCU use both slots, SLOT_A as "primary". */
 304 #define CONFIG_PCMCIA_SLOT_A 1
 305
 306 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 307 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 308 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 309 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 310 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 311 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 312 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 313 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 314 #define PCMCIA_MEM_WIN_NO       8 /* override default 4 in pcmcia.h */
 315 #define PCMCIA_SOCKETS_NO       2 /* we have two sockets */
 316 #undef  NSCU_OE_INV             /* PCMCIA_GCRX_CXOE was inverted on early boards */
 317
 318 /*-----------------------------------------------------------------------
 319  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 320  *-----------------------------------------------------------------------
 321  */
 322
 323 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 324
 325 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 326 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 327 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 328
 329 #define CONFIG_SYS_IDE_MAXBUS           2       /* max. 2 IDE buses             */
 330 #define CONFIG_SYS_IDE_MAXDEVICE        4       /* max. 2 drives per IDE bus    */
 331
 332 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 333 #define CONFIG_SYS_ATA_IDE1_OFFSET      (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */
 334
 335 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 336
 337 /* Offset for data I/O                  */
 338 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 339
 340 /* Offset for normal register accesses  */
 341 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 342
 343 /* Offset for alternate registers       */
 344 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 345
 346 /*-----------------------------------------------------------------------
 347  *
 348  *-----------------------------------------------------------------------
 349  *
 350  */
 351 #define CONFIG_SYS_DER  0
 352
 353 /*
 354  * Init Memory Controller:
 355  *
 356  * BR0/1 and OR0/1 (FLASH)
 357  */
 358
 359 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 360 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 361
 362 /* used to re-map FLASH both when starting from SRAM or FLASH:
 363  * restrict access enough to keep SRAM working (if any)
 364  * but not too much to meddle with FLASH accesses
 365  */
 366 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 367 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 368
 369 /*
 370  * FLASH timing:
 371  */
 372 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 373                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 374
 375 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 376 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 377 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 378
 379 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 380 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 381 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 382
 383 /*
 384  * BR2/3 and OR2/3 (SDRAM)
 385  *
 386  */
 387 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 388 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 389 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 390
 391 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 392 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 393
 394 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 395 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 396
 397 #ifndef CONFIG_CAN_DRIVER
 398 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 399 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 400 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 401 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 402 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 403 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 404 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 405                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 406 #endif  /* CONFIG_CAN_DRIVER */
 407
 408 #ifdef  CONFIG_ISP1362_USB
 409 #define CONFIG_SYS_ISP1362_BASE 0xD0000000      /* ISP1362 mapped at 0xD0000000 */
 410 #define CONFIG_SYS_ISP1362_OR_AM        0xFFFF8000      /* 32 kB address mask           */
 411 #define CONFIG_SYS_OR5_ISP1362          (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \
 412                                  OR_ACS_DIV2       | OR_BI       | OR_SCY_5_CLK)
 413 #define CONFIG_SYS_BR5_ISP1362          ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \
 414                                  BR_PS_16          | BR_MS_GPCM | BR_V )
 415 #endif  /* CONFIG_ISP1362_USB */
 416
 417 /*
 418  * Memory Periodic Timer Prescaler
 419  *
 420  * The Divider for PTA (refresh timer) configuration is based on an
 421  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 422  * the number of chip selects (NCS) and the actually needed refresh
 423  * rate is done by setting MPTPR.
 424  *
 425  * PTA is calculated from
 426  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 427  *
 428  *      gclk      CPU clock (not bus clock!)
 429  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 430  *
 431  * 4096  Rows from SDRAM example configuration
 432  * 1000  factor s -> ms
 433  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 434  *    4  Number of refresh cycles per period
 435  *   64  Refresh cycle in ms per number of rows
 436  * --------------------------------------------
 437  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 438  *
 439  * 50 MHz => 50.000.000 / Divider =  98
 440  * 66 Mhz => 66.000.000 / Divider = 129
 441  * 80 Mhz => 80.000.000 / Divider = 156
 442  */
 443
 444 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 445 #define CONFIG_SYS_MAMR_PTA     98
 446
 447 /*
 448  * For 16 MBit, refresh rates could be 31.3 us
 449  * (= 64 ms / 2K = 125 / quad bursts).
 450  * For a simpler initialization, 15.6 us is used instead.
 451  *
 452  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 453  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 454  */
 455 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 456 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 457
 458 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 459 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 460 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 461
 462 /*
 463  * MAMR settings for SDRAM
 464  */
 465
 466 /* 8 column SDRAM */
 467 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 468                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 469                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 470 /* 9 column SDRAM */
 471 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 472                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 473                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 474
 475
 476 /*
 477  * Internal Definitions
 478  *
 479  * Boot Flags
 480  */
 481 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 482 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 483
 484 #undef CONFIG_SCC1_ENET
 485 #define CONFIG_FEC_ENET
 486 /* #define CONFIG_ETHPRIME              "FEC ETHERNET" */
 487
 488 #endif  /* __CONFIG_H */