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1 /*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * P010 RDB board configuration file
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #ifdef CONFIG_36BIT
15 #define CONFIG_PHYS_64BIT
16 #endif
17 #define CONFIG_SYS_GENERIC_BOARD
18 #define CONFIG_DISPLAY_BOARDINFO
19
20 #define CONFIG_P1010
21 #define CONFIG_E500 /* BOOKE e500 family */
22 #include <asm/config_mpc85xx.h>
23 #define CONFIG_NAND_FSL_IFC
24
25 #ifdef CONFIG_SDCARD
26 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
27 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
28 #define CONFIG_SPL_ENV_SUPPORT
29 #define CONFIG_SPL_SERIAL_SUPPORT
30 #define CONFIG_SPL_MMC_SUPPORT
31 #define CONFIG_SPL_MMC_MINIMAL
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_LIBGENERIC_SUPPORT
35 #define CONFIG_SPL_LIBCOMMON_SUPPORT
36 #define CONFIG_SPL_I2C_SUPPORT
37 #define CONFIG_FSL_LAW /* Use common FSL init code */
38 #define CONFIG_SYS_TEXT_BASE 0x11001000
39 #define CONFIG_SPL_TEXT_BASE 0xD0001000
40 #define CONFIG_SPL_PAD_TO 0x18000
41 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
44 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
48 #define CONFIG_SPL_MMC_BOOT
49 #ifdef CONFIG_SPL_BUILD
50 #define CONFIG_SPL_COMMON_INIT_DDR
51 #endif
52 #endif
53
54 #ifdef CONFIG_SPIFLASH
55 #ifdef CONFIG_SECURE_BOOT
56 #define CONFIG_RAMBOOT_SPIFLASH
57 #define CONFIG_SYS_TEXT_BASE 0x11000000
58 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
59 #else
60 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
61 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
62 #define CONFIG_SPL_ENV_SUPPORT
63 #define CONFIG_SPL_SERIAL_SUPPORT
64 #define CONFIG_SPL_SPI_SUPPORT
65 #define CONFIG_SPL_SPI_FLASH_SUPPORT
66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
67 #define CONFIG_SPL_FLUSH_IMAGE
68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69 #define CONFIG_SPL_LIBGENERIC_SUPPORT
70 #define CONFIG_SPL_LIBCOMMON_SUPPORT
71 #define CONFIG_SPL_I2C_SUPPORT
72 #define CONFIG_FSL_LAW /* Use common FSL init code */
73 #define CONFIG_SYS_TEXT_BASE 0x11001000
74 #define CONFIG_SPL_TEXT_BASE 0xD0001000
75 #define CONFIG_SPL_PAD_TO 0x18000
76 #define CONFIG_SPL_MAX_SIZE (96 * 1024)
77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
83 #define CONFIG_SPL_SPI_BOOT
84 #ifdef CONFIG_SPL_BUILD
85 #define CONFIG_SPL_COMMON_INIT_DDR
86 #endif
87 #endif
88 #endif
89
90 #ifdef CONFIG_NAND
91 #ifdef CONFIG_SECURE_BOOT
92 #define CONFIG_SPL_INIT_MINIMAL
93 #define CONFIG_SPL_SERIAL_SUPPORT
94 #define CONFIG_SPL_NAND_SUPPORT
95 #define CONFIG_SPL_NAND_BOOT
96 #define CONFIG_SPL_FLUSH_IMAGE
97 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
98
99 #define CONFIG_SYS_TEXT_BASE 0x00201000
100 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
101 #define CONFIG_SPL_MAX_SIZE 8192
102 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
103 #define CONFIG_SPL_RELOC_STACK 0x00100000
104 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
105 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
106 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
107 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
109 #else
110 #ifdef CONFIG_TPL_BUILD
111 #define CONFIG_SPL_NAND_BOOT
112 #define CONFIG_SPL_FLUSH_IMAGE
113 #define CONFIG_SPL_ENV_SUPPORT
114 #define CONFIG_SPL_NAND_INIT
115 #define CONFIG_SPL_SERIAL_SUPPORT
116 #define CONFIG_SPL_LIBGENERIC_SUPPORT
117 #define CONFIG_SPL_LIBCOMMON_SUPPORT
118 #define CONFIG_SPL_I2C_SUPPORT
119 #define CONFIG_SPL_NAND_SUPPORT
120 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
121 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
122 #define CONFIG_SPL_COMMON_INIT_DDR
123 #define CONFIG_SPL_MAX_SIZE (128 << 10)
124 #define CONFIG_SPL_TEXT_BASE 0xD0001000
125 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
126 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
127 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
128 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
129 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
130 #elif defined(CONFIG_SPL_BUILD)
131 #define CONFIG_SPL_INIT_MINIMAL
132 #define CONFIG_SPL_SERIAL_SUPPORT
133 #define CONFIG_SPL_NAND_SUPPORT
134 #define CONFIG_SPL_NAND_MINIMAL
135 #define CONFIG_SPL_FLUSH_IMAGE
136 #define CONFIG_SPL_TEXT_BASE 0xff800000
137 #define CONFIG_SPL_MAX_SIZE 8192
138 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
139 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
140 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
141 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
142 #endif
143 #define CONFIG_SPL_PAD_TO 0x20000
144 #define CONFIG_TPL_PAD_TO 0x20000
145 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
146 #define CONFIG_SYS_TEXT_BASE 0x11001000
147 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
148 #endif
149 #endif
150
151 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
152 #define CONFIG_RAMBOOT_NAND
153 #define CONFIG_SYS_TEXT_BASE 0x11000000
154 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
155 #endif
156
157 #ifndef CONFIG_SYS_TEXT_BASE
158 #define CONFIG_SYS_TEXT_BASE 0xeff40000
159 #endif
160
161 #ifndef CONFIG_RESET_VECTOR_ADDRESS
162 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
163 #endif
164
165 #ifdef CONFIG_SPL_BUILD
166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
167 #else
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
169 #endif
170
171 /* High Level Configuration Options */
172 #define CONFIG_BOOKE /* BOOKE */
173 #define CONFIG_E500 /* BOOKE e500 family */
174 #define CONFIG_FSL_IFC /* Enable IFC Support */
175 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
176 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
177
178 #define CONFIG_PCI /* Enable PCI/PCIE */
179 #if defined(CONFIG_PCI)
180 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
181 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
182 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
183 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
184 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
185 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
186
187 #define CONFIG_CMD_NET
188 #define CONFIG_CMD_PCI
189
190 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
191
192 /*
193 * PCI Windows
194 * Memory space is mapped 1-1, but I/O space must start from 0.
195 */
196 /* controller 1, Slot 1, tgtid 1, Base address a000 */
197 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
198 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
199 #ifdef CONFIG_PHYS_64BIT
200 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
201 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
202 #else
203 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
204 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
205 #endif
206 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
207 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
208 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
209 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
212 #else
213 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
214 #endif
215
216 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
217 #if defined(CONFIG_P1010RDB_PA)
218 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
219 #elif defined(CONFIG_P1010RDB_PB)
220 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
221 #endif
222 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
223 #ifdef CONFIG_PHYS_64BIT
224 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
225 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
226 #else
227 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
228 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
229 #endif
230 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
231 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
232 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
233 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
234 #ifdef CONFIG_PHYS_64BIT
235 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
236 #else
237 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
238 #endif
239
240 #define CONFIG_PCI_PNP /* do pci plug-and-play */
241
242 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
243 #define CONFIG_DOS_PARTITION
244 #endif
245
246 #define CONFIG_FSL_LAW /* Use common FSL init code */
247 #define CONFIG_TSEC_ENET
248 #define CONFIG_ENV_OVERWRITE
249
250 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
251 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
252
253 #define CONFIG_MISC_INIT_R
254 #define CONFIG_HWCONFIG
255 /*
256 * These can be toggled for performance analysis, otherwise use default.
257 */
258 #define CONFIG_L2_CACHE /* toggle L2 cache */
259 #define CONFIG_BTB /* toggle branch predition */
260
261 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
262
263 #define CONFIG_ENABLE_36BIT_PHYS
264
265 #ifdef CONFIG_PHYS_64BIT
266 #define CONFIG_ADDR_MAP 1
267 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
268 #endif
269
270 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
271 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
272 #define CONFIG_PANIC_HANG /* do not reset board on panic */
273
274 /* DDR Setup */
275 #define CONFIG_SYS_FSL_DDR3
276 #define CONFIG_SYS_DDR_RAW_TIMING
277 #define CONFIG_DDR_SPD
278 #define CONFIG_SYS_SPD_BUS_NUM 1
279 #define SPD_EEPROM_ADDRESS 0x52
280
281 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
282
283 #ifndef __ASSEMBLY__
284 extern unsigned long get_sdram_size(void);
285 #endif
286 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
287 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
288 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
289
290 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
291 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
292
293 /* DDR3 Controller Settings */
294 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
295 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
296 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
297 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
298 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
299 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
300 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
301 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
302 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
303 #define CONFIG_SYS_DDR_RCW_1 0x00000000
304 #define CONFIG_SYS_DDR_RCW_2 0x00000000
305 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
306 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
307 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
308 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
309
310 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
311 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
312 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
313 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
314 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
315 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
316 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
317 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
318 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
319
320 /* settings for DDR3 at 667MT/s */
321 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
322 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
323 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
324 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
325 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
326 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
327 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
328 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
329 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
330
331 #define CONFIG_SYS_CCSRBAR 0xffe00000
332 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
333
334 /* Don't relocate CCSRBAR while in NAND_SPL */
335 #ifdef CONFIG_SPL_BUILD
336 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
337 #endif
338
339 /*
340 * Memory map
341 *
342 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
343 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
344 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
345 *
346 * Localbus non-cacheable
347 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
348 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
349 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
350 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
351 */
352
353 /*
354 * IFC Definitions
355 */
356 /* NOR Flash on IFC */
357 #ifdef CONFIG_SPL_BUILD
358 #define CONFIG_SYS_NO_FLASH
359 #endif
360
361 #define CONFIG_SYS_FLASH_BASE 0xee000000
362 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
363
364 #ifdef CONFIG_PHYS_64BIT
365 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
366 #else
367 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
368 #endif
369
370 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
371 CSPR_PORT_SIZE_16 | \
372 CSPR_MSEL_NOR | \
373 CSPR_V)
374 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
375 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
376 /* NOR Flash Timing Params */
377 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
378 FTIM0_NOR_TEADC(0x5) | \
379 FTIM0_NOR_TEAHC(0x5)
380 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
381 FTIM1_NOR_TRAD_NOR(0x0f)
382 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
383 FTIM2_NOR_TCH(0x4) | \
384 FTIM2_NOR_TWP(0x1c)
385 #define CONFIG_SYS_NOR_FTIM3 0x0
386
387 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
388 #define CONFIG_SYS_FLASH_QUIET_TEST
389 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
390 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
391
392 #undef CONFIG_SYS_FLASH_CHECKSUM
393 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
394 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
395
396 /* CFI for NOR Flash */
397 #define CONFIG_FLASH_CFI_DRIVER
398 #define CONFIG_SYS_FLASH_CFI
399 #define CONFIG_SYS_FLASH_EMPTY_INFO
400 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
401
402 /* NAND Flash on IFC */
403 #define CONFIG_SYS_NAND_BASE 0xff800000
404 #ifdef CONFIG_PHYS_64BIT
405 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
406 #else
407 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
408 #endif
409
410 #define CONFIG_MTD_DEVICE
411 #define CONFIG_MTD_PARTITION
412 #define CONFIG_CMD_MTDPARTS
413 #define MTDIDS_DEFAULT "nand0=ff800000.flash"
414 #define MTDPARTS_DEFAULT \
415 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
416
417 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
418 | CSPR_PORT_SIZE_8 \
419 | CSPR_MSEL_NAND \
420 | CSPR_V)
421 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
422
423 #if defined(CONFIG_P1010RDB_PA)
424 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
425 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
426 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
427 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
428 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
429 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
430 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
431 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
432
433 #elif defined(CONFIG_P1010RDB_PB)
434 #define CONFIG_SYS_NAND_ONFI_DETECTION
435 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
436 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
437 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
438 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
439 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
440 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
441 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
442 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
443 #endif
444
445 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
446 #define CONFIG_SYS_MAX_NAND_DEVICE 1
447 #define CONFIG_CMD_NAND
448
449 #if defined(CONFIG_P1010RDB_PA)
450 /* NAND Flash Timing Params */
451 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
452 FTIM0_NAND_TWP(0x0C) | \
453 FTIM0_NAND_TWCHT(0x04) | \
454 FTIM0_NAND_TWH(0x05)
455 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
456 FTIM1_NAND_TWBE(0x1d) | \
457 FTIM1_NAND_TRR(0x07) | \
458 FTIM1_NAND_TRP(0x0c)
459 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
460 FTIM2_NAND_TREH(0x05) | \
461 FTIM2_NAND_TWHRE(0x0f)
462 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
463
464 #elif defined(CONFIG_P1010RDB_PB)
465 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
466 /* ONFI NAND Flash mode0 Timing Params */
467 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
468 FTIM0_NAND_TWP(0x18) | \
469 FTIM0_NAND_TWCHT(0x07) | \
470 FTIM0_NAND_TWH(0x0a))
471 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
472 FTIM1_NAND_TWBE(0x39) | \
473 FTIM1_NAND_TRR(0x0e) | \
474 FTIM1_NAND_TRP(0x18))
475 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
476 FTIM2_NAND_TREH(0x0a) | \
477 FTIM2_NAND_TWHRE(0x1e))
478 #define CONFIG_SYS_NAND_FTIM3 0x0
479 #endif
480
481 #define CONFIG_SYS_NAND_DDR_LAW 11
482
483 /* Set up IFC registers for boot location NOR/NAND */
484 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
485 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
486 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
487 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
488 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
489 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
490 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
491 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
492 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
493 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
494 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
495 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
496 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
497 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
498 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
499 #else
500 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
501 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
502 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
503 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
504 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
505 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
506 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
507 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
508 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
509 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
510 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
511 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
512 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
513 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
514 #endif
515
516 /* CPLD on IFC */
517 #define CONFIG_SYS_CPLD_BASE 0xffb00000
518
519 #ifdef CONFIG_PHYS_64BIT
520 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
521 #else
522 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
523 #endif
524
525 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
526 | CSPR_PORT_SIZE_8 \
527 | CSPR_MSEL_GPCM \
528 | CSPR_V)
529 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
530 #define CONFIG_SYS_CSOR3 0x0
531 /* CPLD Timing parameters for IFC CS3 */
532 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
533 FTIM0_GPCM_TEADC(0x0e) | \
534 FTIM0_GPCM_TEAHC(0x0e))
535 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
536 FTIM1_GPCM_TRAD(0x1f))
537 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
538 FTIM2_GPCM_TCH(0x8) | \
539 FTIM2_GPCM_TWP(0x1f))
540 #define CONFIG_SYS_CS3_FTIM3 0x0
541
542 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
543 defined(CONFIG_RAMBOOT_NAND)
544 #define CONFIG_SYS_RAMBOOT
545 #define CONFIG_SYS_EXTRA_ENV_RELOC
546 #else
547 #undef CONFIG_SYS_RAMBOOT
548 #endif
549
550 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
551 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
552 #define CONFIG_A003399_NOR_WORKAROUND
553 #endif
554 #endif
555
556 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
557 #define CONFIG_BOARD_EARLY_INIT_R
558
559 #define CONFIG_SYS_INIT_RAM_LOCK
560 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
561 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
562
563 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
564 - GENERATED_GBL_DATA_SIZE)
565 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
566
567 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
568 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
569
570 /*
571 * Config the L2 Cache as L2 SRAM
572 */
573 #if defined(CONFIG_SPL_BUILD)
574 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
575 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
576 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
577 #define CONFIG_SYS_L2_SIZE (256 << 10)
578 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
579 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
580 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
581 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
582 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
583 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
584 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
585 #elif defined(CONFIG_NAND)
586 #ifdef CONFIG_TPL_BUILD
587 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
588 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
589 #define CONFIG_SYS_L2_SIZE (256 << 10)
590 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
591 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
592 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
593 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
594 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
595 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
596 #else
597 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
598 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
599 #define CONFIG_SYS_L2_SIZE (256 << 10)
600 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
601 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
602 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
603 #endif
604 #endif
605 #endif
606
607 /* Serial Port */
608 #define CONFIG_CONS_INDEX 1
609 #undef CONFIG_SERIAL_SOFTWARE_FIFO
610 #define CONFIG_SYS_NS16550
611 #define CONFIG_SYS_NS16550_SERIAL
612 #define CONFIG_SYS_NS16550_REG_SIZE 1
613 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
614 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
615 #define CONFIG_NS16550_MIN_FUNCTIONS
616 #endif
617
618 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
619
620 #define CONFIG_SYS_BAUDRATE_TABLE \
621 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
622
623 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
624 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
625
626 /* Use the HUSH parser */
627 #define CONFIG_SYS_HUSH_PARSER
628
629 /*
630 * Pass open firmware flat tree
631 */
632 #define CONFIG_OF_LIBFDT
633 #define CONFIG_OF_BOARD_SETUP
634 #define CONFIG_OF_STDOUT_VIA_ALIAS
635
636 /* new uImage format support */
637 #define CONFIG_FIT
638 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
639
640 /* I2C */
641 #define CONFIG_SYS_I2C
642 #define CONFIG_SYS_I2C_FSL
643 #define CONFIG_SYS_FSL_I2C_SPEED 400000
644 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
645 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
646 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
647 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
648 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
649 #define I2C_PCA9557_ADDR1 0x18
650 #define I2C_PCA9557_ADDR2 0x19
651 #define I2C_PCA9557_BUS_NUM 0
652
653 /* I2C EEPROM */
654 #if defined(CONFIG_P1010RDB_PB)
655 #define CONFIG_ID_EEPROM
656 #ifdef CONFIG_ID_EEPROM
657 #define CONFIG_SYS_I2C_EEPROM_NXID
658 #endif
659 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
660 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
661 #define CONFIG_SYS_EEPROM_BUS_NUM 0
662 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
663 #endif
664 /* enable read and write access to EEPROM */
665 #define CONFIG_CMD_EEPROM
666 #define CONFIG_SYS_I2C_MULTI_EEPROMS
667 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
668 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
669 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
670
671 /* RTC */
672 #define CONFIG_RTC_PT7C4338
673 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
674
675 #define CONFIG_CMD_I2C
676
677 /*
678 * SPI interface will not be available in case of NAND boot SPI CS0 will be
679 * used for SLIC
680 */
681 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
682 /* eSPI - Enhanced SPI */
683 #define CONFIG_FSL_ESPI
684 #define CONFIG_SPI_FLASH
685 #define CONFIG_SPI_FLASH_SPANSION
686 #define CONFIG_CMD_SF
687 #define CONFIG_SF_DEFAULT_SPEED 10000000
688 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
689 #endif
690
691 #if defined(CONFIG_TSEC_ENET)
692 #define CONFIG_MII /* MII PHY management */
693 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
694 #define CONFIG_TSEC1 1
695 #define CONFIG_TSEC1_NAME "eTSEC1"
696 #define CONFIG_TSEC2 1
697 #define CONFIG_TSEC2_NAME "eTSEC2"
698 #define CONFIG_TSEC3 1
699 #define CONFIG_TSEC3_NAME "eTSEC3"
700
701 #define TSEC1_PHY_ADDR 1
702 #define TSEC2_PHY_ADDR 0
703 #define TSEC3_PHY_ADDR 2
704
705 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
706 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
707 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
708
709 #define TSEC1_PHYIDX 0
710 #define TSEC2_PHYIDX 0
711 #define TSEC3_PHYIDX 0
712
713 #define CONFIG_ETHPRIME "eTSEC1"
714
715 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
716
717 /* TBI PHY configuration for SGMII mode */
718 #define CONFIG_TSEC_TBICR_SETTINGS ( \
719 TBICR_PHY_RESET \
720 | TBICR_ANEG_ENABLE \
721 | TBICR_FULL_DUPLEX \
722 | TBICR_SPEED1_SET \
723 )
724
725 #endif /* CONFIG_TSEC_ENET */
726
727
728 /* SATA */
729 #define CONFIG_FSL_SATA
730 #define CONFIG_FSL_SATA_V2
731 #define CONFIG_LIBATA
732
733 #ifdef CONFIG_FSL_SATA
734 #define CONFIG_SYS_SATA_MAX_DEVICE 2
735 #define CONFIG_SATA1
736 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
737 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
738 #define CONFIG_SATA2
739 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
740 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
741
742 #define CONFIG_CMD_SATA
743 #define CONFIG_LBA48
744 #endif /* #ifdef CONFIG_FSL_SATA */
745
746 #define CONFIG_MMC
747 #ifdef CONFIG_MMC
748 #define CONFIG_CMD_MMC
749 #define CONFIG_DOS_PARTITION
750 #define CONFIG_FSL_ESDHC
751 #define CONFIG_GENERIC_MMC
752 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
753 #endif
754
755 #define CONFIG_HAS_FSL_DR_USB
756
757 #if defined(CONFIG_HAS_FSL_DR_USB)
758 #define CONFIG_USB_EHCI
759
760 #ifdef CONFIG_USB_EHCI
761 #define CONFIG_CMD_USB
762 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
763 #define CONFIG_USB_EHCI_FSL
764 #define CONFIG_USB_STORAGE
765 #endif
766 #endif
767
768 /*
769 * Environment
770 */
771 #if defined(CONFIG_SDCARD)
772 #define CONFIG_ENV_IS_IN_MMC
773 #define CONFIG_FSL_FIXED_MMC_LOCATION
774 #define CONFIG_SYS_MMC_ENV_DEV 0
775 #define CONFIG_ENV_SIZE 0x2000
776 #elif defined(CONFIG_SPIFLASH)
777 #define CONFIG_ENV_IS_IN_SPI_FLASH
778 #define CONFIG_ENV_SPI_BUS 0
779 #define CONFIG_ENV_SPI_CS 0
780 #define CONFIG_ENV_SPI_MAX_HZ 10000000
781 #define CONFIG_ENV_SPI_MODE 0
782 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
783 #define CONFIG_ENV_SECT_SIZE 0x10000
784 #define CONFIG_ENV_SIZE 0x2000
785 #elif defined(CONFIG_NAND)
786 #define CONFIG_ENV_IS_IN_NAND
787 #ifdef CONFIG_TPL_BUILD
788 #define CONFIG_ENV_SIZE 0x2000
789 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
790 #else
791 #if defined(CONFIG_P1010RDB_PA)
792 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
793 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
794 #elif defined(CONFIG_P1010RDB_PB)
795 #define CONFIG_ENV_SIZE (16 * 1024)
796 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
797 #endif
798 #endif
799 #define CONFIG_ENV_OFFSET (1024 * 1024)
800 #elif defined(CONFIG_SYS_RAMBOOT)
801 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
802 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
803 #define CONFIG_ENV_SIZE 0x2000
804 #else
805 #define CONFIG_ENV_IS_IN_FLASH
806 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
807 #define CONFIG_ENV_SIZE 0x2000
808 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
809 #endif
810
811 #define CONFIG_LOADS_ECHO /* echo on for serial download */
812 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
813
814 /*
815 * Command line configuration.
816 */
817 #include <config_cmd_default.h>
818
819 #define CONFIG_CMD_DATE
820 #define CONFIG_CMD_ERRATA
821 #define CONFIG_CMD_ELF
822 #define CONFIG_CMD_IRQ
823 #define CONFIG_CMD_MII
824 #define CONFIG_CMD_PING
825 #define CONFIG_CMD_SETEXPR
826 #define CONFIG_CMD_REGINFO
827
828 #undef CONFIG_WATCHDOG /* watchdog disabled */
829
830 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
831 || defined(CONFIG_FSL_SATA)
832 #define CONFIG_CMD_EXT2
833 #define CONFIG_CMD_FAT
834 #define CONFIG_DOS_PARTITION
835 #endif
836
837 /* Hash command with SHA acceleration supported in hardware */
838 #ifdef CONFIG_FSL_CAAM
839 #define CONFIG_CMD_HASH
840 #define CONFIG_SHA_HW_ACCEL
841 #endif
842
843 /*
844 * Miscellaneous configurable options
845 */
846 #define CONFIG_SYS_LONGHELP /* undef to save memory */
847 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
848 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
849 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
850
851 #if defined(CONFIG_CMD_KGDB)
852 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
853 #else
854 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
855 #endif
856 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
857 /* Print Buffer Size */
858 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
859 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
860
861 /*
862 * Internal Definitions
863 *
864 * Boot Flags
865 */
866 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
867 #define BOOTFLAG_WARM 0x02 /* Software reboot */
868
869 /*
870 * For booting Linux, the board info and command line data
871 * have to be in the first 64 MB of memory, since this is
872 * the maximum mapped by the Linux kernel during initialization.
873 */
874 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
875 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
876
877 #if defined(CONFIG_CMD_KGDB)
878 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
879 #endif
880
881 /*
882 * Environment Configuration
883 */
884
885 #if defined(CONFIG_TSEC_ENET)
886 #define CONFIG_HAS_ETH0
887 #define CONFIG_HAS_ETH1
888 #define CONFIG_HAS_ETH2
889 #endif
890
891 #define CONFIG_ROOTPATH "/opt/nfsroot"
892 #define CONFIG_BOOTFILE "uImage"
893 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
894
895 /* default location for tftp and bootm */
896 #define CONFIG_LOADADDR 1000000
897
898 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
899 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
900
901 #define CONFIG_BAUDRATE 115200
902
903 #define CONFIG_EXTRA_ENV_SETTINGS \
904 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
905 "netdev=eth0\0" \
906 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
907 "loadaddr=1000000\0" \
908 "consoledev=ttyS0\0" \
909 "ramdiskaddr=2000000\0" \
910 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
911 "fdtaddr=c00000\0" \
912 "fdtfile=p1010rdb.dtb\0" \
913 "bdev=sda1\0" \
914 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
915 "othbootargs=ramdisk_size=600000\0" \
916 "usbfatboot=setenv bootargs root=/dev/ram rw " \
917 "console=$consoledev,$baudrate $othbootargs; " \
918 "usb start;" \
919 "fatload usb 0:2 $loadaddr $bootfile;" \
920 "fatload usb 0:2 $fdtaddr $fdtfile;" \
921 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
922 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
923 "usbext2boot=setenv bootargs root=/dev/ram rw " \
924 "console=$consoledev,$baudrate $othbootargs; " \
925 "usb start;" \
926 "ext2load usb 0:4 $loadaddr $bootfile;" \
927 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
928 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
929 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
930 CONFIG_BOOTMODE
931
932 #if defined(CONFIG_P1010RDB_PA)
933 #define CONFIG_BOOTMODE \
934 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
935 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
936 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
937 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
938 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
939 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
940
941 #elif defined(CONFIG_P1010RDB_PB)
942 #define CONFIG_BOOTMODE \
943 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
944 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
945 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
946 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
947 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
948 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
949 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
950 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
951 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
952 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
953 #endif
954
955 #define CONFIG_RAMBOOTCOMMAND \
956 "setenv bootargs root=/dev/ram rw " \
957 "console=$consoledev,$baudrate $othbootargs; " \
958 "tftp $ramdiskaddr $ramdiskfile;" \
959 "tftp $loadaddr $bootfile;" \
960 "tftp $fdtaddr $fdtfile;" \
961 "bootm $loadaddr $ramdiskaddr $fdtaddr"
962
963 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
964
965 #include <asm/fsl_secure_boot.h>
966
967 #ifdef CONFIG_SECURE_BOOT
968 #define CONFIG_CMD_BLOB
969 #endif
970
971 #endif /* __CONFIG_H */