include/configs/P1010RDB.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * P010 RDB board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_36BIT
  15 #define CONFIG_PHYS_64BIT
  16 #endif
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_P1010
  20 #define CONFIG_E500                     /* BOOKE e500 family */
  21 #include <asm/config_mpc85xx.h>
  22 #define CONFIG_NAND_FSL_IFC
  23
  24 #ifdef CONFIG_SDCARD
  25 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  26 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  27 #define CONFIG_SPL_ENV_SUPPORT
  28 #define CONFIG_SPL_SERIAL_SUPPORT
  29 #define CONFIG_SPL_MMC_SUPPORT
  30 #define CONFIG_SPL_MMC_MINIMAL
  31 #define CONFIG_SPL_FLUSH_IMAGE
  32 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  33 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  34 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  35 #define CONFIG_SPL_I2C_SUPPORT
  36 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  37 #define CONFIG_SYS_TEXT_BASE            0x11001000
  38 #define CONFIG_SPL_TEXT_BASE            0xD0001000
  39 #define CONFIG_SPL_PAD_TO               0x18000
  40 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  41 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  42 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  43 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  44 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  45 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  46 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  47 #define CONFIG_SPL_MMC_BOOT
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_COMMON_INIT_DDR
  50 #endif
  51 #endif
  52
  53 #ifdef CONFIG_SPIFLASH
  54 #ifdef CONFIG_SECURE_BOOT
  55 #define CONFIG_RAMBOOT_SPIFLASH
  56 #define CONFIG_SYS_TEXT_BASE            0x11000000
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  58 #else
  59 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  60 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  61 #define CONFIG_SPL_ENV_SUPPORT
  62 #define CONFIG_SPL_SERIAL_SUPPORT
  63 #define CONFIG_SPL_SPI_SUPPORT
  64 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  66 #define CONFIG_SPL_FLUSH_IMAGE
  67 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  68 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  69 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  70 #define CONFIG_SPL_I2C_SUPPORT
  71 #define CONFIG_FSL_LAW         /* Use common FSL init code */
  72 #define CONFIG_SYS_TEXT_BASE                    0x11001000
  73 #define CONFIG_SPL_TEXT_BASE                    0xD0001000
  74 #define CONFIG_SPL_PAD_TO                       0x18000
  75 #define CONFIG_SPL_MAX_SIZE                     (96 * 1024)
  76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  81 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  82 #define CONFIG_SPL_SPI_BOOT
  83 #ifdef CONFIG_SPL_BUILD
  84 #define CONFIG_SPL_COMMON_INIT_DDR
  85 #endif
  86 #endif
  87 #endif
  88
  89 #ifdef CONFIG_NAND
  90 #ifdef CONFIG_SECURE_BOOT
  91 #define CONFIG_SPL_INIT_MINIMAL
  92 #define CONFIG_SPL_SERIAL_SUPPORT
  93 #define CONFIG_SPL_NAND_SUPPORT
  94 #define CONFIG_SPL_NAND_BOOT
  95 #define CONFIG_SPL_FLUSH_IMAGE
  96 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  97
  98 #define CONFIG_SYS_TEXT_BASE            0x00201000
  99 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
 100 #define CONFIG_SPL_MAX_SIZE             8192
 101 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
 102 #define CONFIG_SPL_RELOC_STACK          0x00100000
 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
 104 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
 105 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
 107 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 108 #else
 109 #ifdef CONFIG_TPL_BUILD
 110 #define CONFIG_SPL_NAND_BOOT
 111 #define CONFIG_SPL_FLUSH_IMAGE
 112 #define CONFIG_SPL_ENV_SUPPORT
 113 #define CONFIG_SPL_NAND_INIT
 114 #define CONFIG_SPL_SERIAL_SUPPORT
 115 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 116 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 117 #define CONFIG_SPL_I2C_SUPPORT
 118 #define CONFIG_SPL_NAND_SUPPORT
 119 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 120 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 121 #define CONFIG_SPL_COMMON_INIT_DDR
 122 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 123 #define CONFIG_SPL_TEXT_BASE            0xD0001000
 124 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 125 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
 126 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 127 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 128 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 129 #elif defined(CONFIG_SPL_BUILD)
 130 #define CONFIG_SPL_INIT_MINIMAL
 131 #define CONFIG_SPL_SERIAL_SUPPORT
 132 #define CONFIG_SPL_NAND_SUPPORT
 133 #define CONFIG_SPL_NAND_MINIMAL
 134 #define CONFIG_SPL_FLUSH_IMAGE
 135 #define CONFIG_SPL_TEXT_BASE            0xff800000
 136 #define CONFIG_SPL_MAX_SIZE             8192
 137 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 138 #define CONFIG_SYS_NAND_U_BOOT_DST      0xD0000000
 139 #define CONFIG_SYS_NAND_U_BOOT_START    0xD0000000
 140 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 141 #endif
 142 #define CONFIG_SPL_PAD_TO       0x20000
 143 #define CONFIG_TPL_PAD_TO       0x20000
 144 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
 145 #define CONFIG_SYS_TEXT_BASE    0x11001000
 146 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 147 #endif
 148 #endif
 149
 150 #ifdef CONFIG_NAND_SECBOOT      /* NAND Boot */
 151 #define CONFIG_RAMBOOT_NAND
 152 #define CONFIG_SYS_TEXT_BASE            0x11000000
 153 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
 154 #endif
 155
 156 #ifndef CONFIG_SYS_TEXT_BASE
 157 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 158 #endif
 159
 160 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 161 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 162 #endif
 163
 164 #ifdef CONFIG_SPL_BUILD
 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 166 #else
 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 168 #endif
 169
 170 /* High Level Configuration Options */
 171 #define CONFIG_BOOKE                    /* BOOKE */
 172 #define CONFIG_E500                     /* BOOKE e500 family */
 173 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
 174 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 175 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
 176
 177 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 178 #if defined(CONFIG_PCI)
 179 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 180 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 181 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 182 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 183 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 184 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 185
 186 #define CONFIG_CMD_PCI
 187
 188 /*
 189  * PCI Windows
 190  * Memory space is mapped 1-1, but I/O space must start from 0.
 191  */
 192 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 193 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe Slot"
 194 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 195 #ifdef CONFIG_PHYS_64BIT
 196 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 197 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 198 #else
 199 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 200 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 201 #endif
 202 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 203 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 204 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 205 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 206 #ifdef CONFIG_PHYS_64BIT
 207 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 208 #else
 209 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 210 #endif
 211
 212 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 213 #if defined(CONFIG_P1010RDB_PA)
 214 #define CONFIG_SYS_PCIE2_NAME           "PCIe Slot"
 215 #elif defined(CONFIG_P1010RDB_PB)
 216 #define CONFIG_SYS_PCIE2_NAME           "mini PCIe Slot"
 217 #endif
 218 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 219 #ifdef CONFIG_PHYS_64BIT
 220 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 221 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 222 #else
 223 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 224 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 225 #endif
 226 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 227 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 228 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 229 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 230 #ifdef CONFIG_PHYS_64BIT
 231 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 232 #else
 233 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 234 #endif
 235
 236 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 237
 238 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 239 #define CONFIG_DOS_PARTITION
 240 #endif
 241
 242 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 243 #define CONFIG_TSEC_ENET
 244 #define CONFIG_ENV_OVERWRITE
 245
 246 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1010 RDB */
 247 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for P1010 RDB */
 248
 249 #define CONFIG_MISC_INIT_R
 250 #define CONFIG_HWCONFIG
 251 /*
 252  * These can be toggled for performance analysis, otherwise use default.
 253  */
 254 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 255 #define CONFIG_BTB                      /* toggle branch predition */
 256
 257 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 258
 259 #define CONFIG_ENABLE_36BIT_PHYS
 260
 261 #ifdef CONFIG_PHYS_64BIT
 262 #define CONFIG_ADDR_MAP                 1
 263 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 264 #endif
 265
 266 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 267 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 268 #define CONFIG_PANIC_HANG               /* do not reset board on panic */
 269
 270 /* DDR Setup */
 271 #define CONFIG_SYS_FSL_DDR3
 272 #define CONFIG_SYS_DDR_RAW_TIMING
 273 #define CONFIG_DDR_SPD
 274 #define CONFIG_SYS_SPD_BUS_NUM          1
 275 #define SPD_EEPROM_ADDRESS              0x52
 276
 277 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 278
 279 #ifndef __ASSEMBLY__
 280 extern unsigned long get_sdram_size(void);
 281 #endif
 282 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 283 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 284 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 285
 286 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 287 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 288
 289 /* DDR3 Controller Settings */
 290 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 291 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 292 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 293 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 294 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 295 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 296 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 297 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 298 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 299 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 300 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 301 #define CONFIG_SYS_DDR_CONTROL          0xc70c0008      /* Type = DDR3  */
 302 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 303 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 304 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 305
 306 #define CONFIG_SYS_DDR_TIMING_3_800     0x00030000
 307 #define CONFIG_SYS_DDR_TIMING_0_800     0x00110104
 308 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b8644
 309 #define CONFIG_SYS_DDR_TIMING_2_800     0x0FA888CF
 310 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x03000000
 311 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
 312 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
 313 #define CONFIG_SYS_DDR_INTERVAL_800     0x0C300100
 314 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
 315
 316 /* settings for DDR3 at 667MT/s */
 317 #define CONFIG_SYS_DDR_TIMING_3_667             0x00010000
 318 #define CONFIG_SYS_DDR_TIMING_0_667             0x00110004
 319 #define CONFIG_SYS_DDR_TIMING_1_667             0x5d59e544
 320 #define CONFIG_SYS_DDR_TIMING_2_667             0x0FA890CD
 321 #define CONFIG_SYS_DDR_CLK_CTRL_667             0x03000000
 322 #define CONFIG_SYS_DDR_MODE_1_667               0x00441210
 323 #define CONFIG_SYS_DDR_MODE_2_667               0x00000000
 324 #define CONFIG_SYS_DDR_INTERVAL_667             0x0a280000
 325 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667        0x8675F608
 326
 327 #define CONFIG_SYS_CCSRBAR                      0xffe00000
 328 #define CONFIG_SYS_CCSRBAR_PHYS_LOW             CONFIG_SYS_CCSRBAR
 329
 330 /* Don't relocate CCSRBAR while in NAND_SPL */
 331 #ifdef CONFIG_SPL_BUILD
 332 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 333 #endif
 334
 335 /*
 336  * Memory map
 337  *
 338  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheable
 339  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1.5G non-cacheable
 340  * 0xffc0_0000  0xffc3_ffff     PCI IO range            256k non-cacheable
 341  *
 342  * Localbus non-cacheable
 343  * 0xff80_0000  0xff8f_ffff     NAND Flash              1M non-cacheable
 344  * 0xffb0_0000  0xffbf_ffff     Board CPLD              1M non-cacheable
 345  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 346  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 347  */
 348
 349 /*
 350  * IFC Definitions
 351  */
 352 /* NOR Flash on IFC */
 353 #ifdef CONFIG_SPL_BUILD
 354 #define CONFIG_SYS_NO_FLASH
 355 #endif
 356
 357 #define CONFIG_SYS_FLASH_BASE           0xee000000
 358 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 359
 360 #ifdef CONFIG_PHYS_64BIT
 361 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 362 #else
 363 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 364 #endif
 365
 366 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 367                                 CSPR_PORT_SIZE_16 | \
 368                                 CSPR_MSEL_NOR | \
 369                                 CSPR_V)
 370 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(32*1024*1024)
 371 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(7)
 372 /* NOR Flash Timing Params */
 373 #define CONFIG_SYS_NOR_FTIM0    FTIM0_NOR_TACSE(0x4) | \
 374                                 FTIM0_NOR_TEADC(0x5) | \
 375                                 FTIM0_NOR_TEAHC(0x5)
 376 #define CONFIG_SYS_NOR_FTIM1    FTIM1_NOR_TACO(0x1e) | \
 377                                 FTIM1_NOR_TRAD_NOR(0x0f)
 378 #define CONFIG_SYS_NOR_FTIM2    FTIM2_NOR_TCS(0x4) | \
 379                                 FTIM2_NOR_TCH(0x4) | \
 380                                 FTIM2_NOR_TWP(0x1c)
 381 #define CONFIG_SYS_NOR_FTIM3    0x0
 382
 383 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 384 #define CONFIG_SYS_FLASH_QUIET_TEST
 385 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 386 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 387
 388 #undef CONFIG_SYS_FLASH_CHECKSUM
 389 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 390 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 391
 392 /* CFI for NOR Flash */
 393 #define CONFIG_FLASH_CFI_DRIVER
 394 #define CONFIG_SYS_FLASH_CFI
 395 #define CONFIG_SYS_FLASH_EMPTY_INFO
 396 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 397
 398 /* NAND Flash on IFC */
 399 #define CONFIG_SYS_NAND_BASE            0xff800000
 400 #ifdef CONFIG_PHYS_64BIT
 401 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 402 #else
 403 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 404 #endif
 405
 406 #define CONFIG_MTD_DEVICE
 407 #define CONFIG_MTD_PARTITION
 408 #define CONFIG_CMD_MTDPARTS
 409 #define MTDIDS_DEFAULT                  "nand0=ff800000.flash"
 410 #define MTDPARTS_DEFAULT                \
 411         "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
 412
 413 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 414                                 | CSPR_PORT_SIZE_8      \
 415                                 | CSPR_MSEL_NAND        \
 416                                 | CSPR_V)
 417 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 418
 419 #if defined(CONFIG_P1010RDB_PA)
 420 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 421                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 422                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 423                                 | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
 424                                 | CSOR_NAND_PGS_512     /* Page Size = 512b */ \
 425                                 | CSOR_NAND_SPRZ_16     /* Spare size = 16 */ \
 426                                 | CSOR_NAND_PB(32))     /* 32 Pages Per Block */
 427 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 428
 429 #elif defined(CONFIG_P1010RDB_PB)
 430 #define CONFIG_SYS_NAND_ONFI_DETECTION
 431 #define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 432                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 433                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 434                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 435                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 436                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 437                                 | CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 438 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 439 #endif
 440
 441 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 442 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 443 #define CONFIG_CMD_NAND
 444
 445 #if defined(CONFIG_P1010RDB_PA)
 446 /* NAND Flash Timing Params */
 447 #define CONFIG_SYS_NAND_FTIM0           FTIM0_NAND_TCCST(0x01) | \
 448                                         FTIM0_NAND_TWP(0x0C)   | \
 449                                         FTIM0_NAND_TWCHT(0x04) | \
 450                                         FTIM0_NAND_TWH(0x05)
 451 #define CONFIG_SYS_NAND_FTIM1           FTIM1_NAND_TADLE(0x1d) | \
 452                                         FTIM1_NAND_TWBE(0x1d)  | \
 453                                         FTIM1_NAND_TRR(0x07)   | \
 454                                         FTIM1_NAND_TRP(0x0c)
 455 #define CONFIG_SYS_NAND_FTIM2           FTIM2_NAND_TRAD(0x0c) | \
 456                                         FTIM2_NAND_TREH(0x05) | \
 457                                         FTIM2_NAND_TWHRE(0x0f)
 458 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 459
 460 #elif defined(CONFIG_P1010RDB_PB)
 461 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 462 /* ONFI NAND Flash mode0 Timing Params */
 463 #define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 464                                         FTIM0_NAND_TWP(0x18)   | \
 465                                         FTIM0_NAND_TWCHT(0x07) | \
 466                                         FTIM0_NAND_TWH(0x0a))
 467 #define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 468                                         FTIM1_NAND_TWBE(0x39)  | \
 469                                         FTIM1_NAND_TRR(0x0e)   | \
 470                                         FTIM1_NAND_TRP(0x18))
 471 #define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 472                                         FTIM2_NAND_TREH(0x0a)  | \
 473                                         FTIM2_NAND_TWHRE(0x1e))
 474 #define CONFIG_SYS_NAND_FTIM3   0x0
 475 #endif
 476
 477 #define CONFIG_SYS_NAND_DDR_LAW         11
 478
 479 /* Set up IFC registers for boot location NOR/NAND */
 480 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 481 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 482 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 483 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 484 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 485 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 486 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 487 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 488 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 489 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 490 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 491 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 492 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 493 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 494 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 495 #else
 496 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 497 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 498 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 499 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 500 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 501 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 502 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 503 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 504 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 505 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 506 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 507 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 508 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 509 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 510 #endif
 511
 512 /* CPLD on IFC */
 513 #define CONFIG_SYS_CPLD_BASE            0xffb00000
 514
 515 #ifdef CONFIG_PHYS_64BIT
 516 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffb00000ull
 517 #else
 518 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 519 #endif
 520
 521 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 522                                 | CSPR_PORT_SIZE_8 \
 523                                 | CSPR_MSEL_GPCM \
 524                                 | CSPR_V)
 525 #define CONFIG_SYS_AMASK3               IFC_AMASK(64*1024)
 526 #define CONFIG_SYS_CSOR3                0x0
 527 /* CPLD Timing parameters for IFC CS3 */
 528 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 529                                         FTIM0_GPCM_TEADC(0x0e) | \
 530                                         FTIM0_GPCM_TEAHC(0x0e))
 531 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 532                                         FTIM1_GPCM_TRAD(0x1f))
 533 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 534                                         FTIM2_GPCM_TCH(0x8) | \
 535                                         FTIM2_GPCM_TWP(0x1f))
 536 #define CONFIG_SYS_CS3_FTIM3            0x0
 537
 538 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
 539         defined(CONFIG_RAMBOOT_NAND)
 540 #define CONFIG_SYS_RAMBOOT
 541 #define CONFIG_SYS_EXTRA_ENV_RELOC
 542 #else
 543 #undef CONFIG_SYS_RAMBOOT
 544 #endif
 545
 546 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 547 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
 548 #define CONFIG_A003399_NOR_WORKAROUND
 549 #endif
 550 #endif
 551
 552 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 553 #define CONFIG_BOARD_EARLY_INIT_R
 554
 555 #define CONFIG_SYS_INIT_RAM_LOCK
 556 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 557 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 558
 559 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 560                                                 - GENERATED_GBL_DATA_SIZE)
 561 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 562
 563 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 564 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 565
 566 /*
 567  * Config the L2 Cache as L2 SRAM
 568  */
 569 #if defined(CONFIG_SPL_BUILD)
 570 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 571 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 572 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 573 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 574 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 575 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 576 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 577 #define CONFIG_SPL_RELOC_STACK_SIZE     (16 << 10)
 578 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 579 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (128 << 10)
 580 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
 581 #elif defined(CONFIG_NAND)
 582 #ifdef CONFIG_TPL_BUILD
 583 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 584 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 585 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 586 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 587 #define CONFIG_SPL_RELOC_TEXT_BASE      0xD0001000
 588 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 589 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 590 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 591 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 592 #else
 593 #define CONFIG_SYS_INIT_L2_ADDR         0xD0000000
 594 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 595 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 596 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 597 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 598 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 599 #endif
 600 #endif
 601 #endif
 602
 603 /* Serial Port */
 604 #define CONFIG_CONS_INDEX       1
 605 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 606 #define CONFIG_SYS_NS16550_SERIAL
 607 #define CONFIG_SYS_NS16550_REG_SIZE     1
 608 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 609 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 610 #define CONFIG_NS16550_MIN_FUNCTIONS
 611 #endif
 612
 613 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 614
 615 #define CONFIG_SYS_BAUDRATE_TABLE       \
 616         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 617
 618 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 619 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 620
 621 /* I2C */
 622 #define CONFIG_SYS_I2C
 623 #define CONFIG_SYS_I2C_FSL
 624 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 625 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 626 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 627 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 628 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 629 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 630 #define I2C_PCA9557_ADDR1               0x18
 631 #define I2C_PCA9557_ADDR2               0x19
 632 #define I2C_PCA9557_BUS_NUM             0
 633
 634 /* I2C EEPROM */
 635 #if defined(CONFIG_P1010RDB_PB)
 636 #define CONFIG_ID_EEPROM
 637 #ifdef CONFIG_ID_EEPROM
 638 #define CONFIG_SYS_I2C_EEPROM_NXID
 639 #endif
 640 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 641 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 642 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 643 #define MAX_NUM_PORTS                   9 /* for 128Bytes EEPROM */
 644 #endif
 645 /* enable read and write access to EEPROM */
 646 #define CONFIG_CMD_EEPROM
 647 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 648 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 649 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 650
 651 /* RTC */
 652 #define CONFIG_RTC_PT7C4338
 653 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 654
 655 /*
 656  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 657  * used for SLIC
 658  */
 659 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 660 /* eSPI - Enhanced SPI */
 661 #define CONFIG_SF_DEFAULT_SPEED         10000000
 662 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 663 #endif
 664
 665 #if defined(CONFIG_TSEC_ENET)
 666 #define CONFIG_MII                      /* MII PHY management */
 667 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 668 #define CONFIG_TSEC1    1
 669 #define CONFIG_TSEC1_NAME       "eTSEC1"
 670 #define CONFIG_TSEC2    1
 671 #define CONFIG_TSEC2_NAME       "eTSEC2"
 672 #define CONFIG_TSEC3    1
 673 #define CONFIG_TSEC3_NAME       "eTSEC3"
 674
 675 #define TSEC1_PHY_ADDR          1
 676 #define TSEC2_PHY_ADDR          0
 677 #define TSEC3_PHY_ADDR          2
 678
 679 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 680 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 681 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 682
 683 #define TSEC1_PHYIDX            0
 684 #define TSEC2_PHYIDX            0
 685 #define TSEC3_PHYIDX            0
 686
 687 #define CONFIG_ETHPRIME         "eTSEC1"
 688
 689 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 690
 691 /* TBI PHY configuration for SGMII mode */
 692 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 693                 TBICR_PHY_RESET \
 694                 | TBICR_ANEG_ENABLE \
 695                 | TBICR_FULL_DUPLEX \
 696                 | TBICR_SPEED1_SET \
 697                 )
 698
 699 #endif  /* CONFIG_TSEC_ENET */
 700
 701 /* SATA */
 702 #define CONFIG_FSL_SATA
 703 #define CONFIG_FSL_SATA_V2
 704 #define CONFIG_LIBATA
 705
 706 #ifdef CONFIG_FSL_SATA
 707 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 708 #define CONFIG_SATA1
 709 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 710 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 711 #define CONFIG_SATA2
 712 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 713 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 714
 715 #define CONFIG_CMD_SATA
 716 #define CONFIG_LBA48
 717 #endif /* #ifdef CONFIG_FSL_SATA  */
 718
 719 #define CONFIG_MMC
 720 #ifdef CONFIG_MMC
 721 #define CONFIG_DOS_PARTITION
 722 #define CONFIG_FSL_ESDHC
 723 #define CONFIG_GENERIC_MMC
 724 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 725 #endif
 726
 727 #define CONFIG_HAS_FSL_DR_USB
 728
 729 #if defined(CONFIG_HAS_FSL_DR_USB)
 730 #define CONFIG_USB_EHCI
 731
 732 #ifdef CONFIG_USB_EHCI
 733 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 734 #define CONFIG_USB_EHCI_FSL
 735 #define CONFIG_USB_STORAGE
 736 #endif
 737 #endif
 738
 739 /*
 740  * Environment
 741  */
 742 #if defined(CONFIG_SDCARD)
 743 #define CONFIG_ENV_IS_IN_MMC
 744 #define CONFIG_FSL_FIXED_MMC_LOCATION
 745 #define CONFIG_SYS_MMC_ENV_DEV          0
 746 #define CONFIG_ENV_SIZE                 0x2000
 747 #elif defined(CONFIG_SPIFLASH)
 748 #define CONFIG_ENV_IS_IN_SPI_FLASH
 749 #define CONFIG_ENV_SPI_BUS      0
 750 #define CONFIG_ENV_SPI_CS       0
 751 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 752 #define CONFIG_ENV_SPI_MODE     0
 753 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 754 #define CONFIG_ENV_SECT_SIZE    0x10000
 755 #define CONFIG_ENV_SIZE         0x2000
 756 #elif defined(CONFIG_NAND)
 757 #define CONFIG_ENV_IS_IN_NAND
 758 #ifdef CONFIG_TPL_BUILD
 759 #define CONFIG_ENV_SIZE         0x2000
 760 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 761 #else
 762 #if defined(CONFIG_P1010RDB_PA)
 763 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 764 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 765 #elif defined(CONFIG_P1010RDB_PB)
 766 #define CONFIG_ENV_SIZE         (16 * 1024)
 767 #define CONFIG_ENV_RANGE        (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 768 #endif
 769 #endif
 770 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 771 #elif defined(CONFIG_SYS_RAMBOOT)
 772 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 773 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 774 #define CONFIG_ENV_SIZE                 0x2000
 775 #else
 776 #define CONFIG_ENV_IS_IN_FLASH
 777 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 778 #define CONFIG_ENV_SIZE         0x2000
 779 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 780 #endif
 781
 782 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 783 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 784
 785 /*
 786  * Command line configuration.
 787  */
 788 #define CONFIG_CMD_DATE
 789 #define CONFIG_CMD_ERRATA
 790 #define CONFIG_CMD_IRQ
 791 #define CONFIG_CMD_REGINFO
 792
 793 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 794
 795 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 796                  || defined(CONFIG_FSL_SATA)
 797 #define CONFIG_DOS_PARTITION
 798 #endif
 799
 800 /* Hash command with SHA acceleration supported in hardware */
 801 #ifdef CONFIG_FSL_CAAM
 802 #define CONFIG_CMD_HASH
 803 #define CONFIG_SHA_HW_ACCEL
 804 #endif
 805
 806 /*
 807  * Miscellaneous configurable options
 808  */
 809 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 810 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 811 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 812 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 813
 814 #if defined(CONFIG_CMD_KGDB)
 815 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 816 #else
 817 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 818 #endif
 819 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 820                                                 /* Print Buffer Size */
 821 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 822 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 823
 824 /*
 825  * For booting Linux, the board info and command line data
 826  * have to be in the first 64 MB of memory, since this is
 827  * the maximum mapped by the Linux kernel during initialization.
 828  */
 829 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 830 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 831
 832 #if defined(CONFIG_CMD_KGDB)
 833 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 834 #endif
 835
 836 /*
 837  * Environment Configuration
 838  */
 839
 840 #if defined(CONFIG_TSEC_ENET)
 841 #define CONFIG_HAS_ETH0
 842 #define CONFIG_HAS_ETH1
 843 #define CONFIG_HAS_ETH2
 844 #endif
 845
 846 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 847 #define CONFIG_BOOTFILE         "uImage"
 848 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 849
 850 /* default location for tftp and bootm */
 851 #define CONFIG_LOADADDR         1000000
 852
 853 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 854
 855 #define CONFIG_BAUDRATE         115200
 856
 857 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 858         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 859         "netdev=eth0\0"                                         \
 860         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 861         "loadaddr=1000000\0"                    \
 862         "consoledev=ttyS0\0"                            \
 863         "ramdiskaddr=2000000\0"                 \
 864         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 865         "fdtaddr=1e00000\0"                             \
 866         "fdtfile=p1010rdb.dtb\0"                \
 867         "bdev=sda1\0"   \
 868         "hwconfig=usb1:dr_mode=host,phy_type=utmi\0"    \
 869         "othbootargs=ramdisk_size=600000\0" \
 870         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 871         "console=$consoledev,$baudrate $othbootargs; "  \
 872         "usb start;"                    \
 873         "fatload usb 0:2 $loadaddr $bootfile;"          \
 874         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 875         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 876         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 877         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 878         "console=$consoledev,$baudrate $othbootargs; "  \
 879         "usb start;"                    \
 880         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 881         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 882         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 883         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 884         CONFIG_BOOTMODE
 885
 886 #if defined(CONFIG_P1010RDB_PA)
 887 #define CONFIG_BOOTMODE \
 888         "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 889         "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
 890         "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
 891         "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
 892         "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
 893         "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
 894
 895 #elif defined(CONFIG_P1010RDB_PB)
 896 #define CONFIG_BOOTMODE \
 897         "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 898         "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
 899         "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
 900         "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
 901         "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
 902         "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
 903         "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
 904         "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
 905         "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
 906         "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
 907 #endif
 908
 909 #define CONFIG_RAMBOOTCOMMAND           \
 910         "setenv bootargs root=/dev/ram rw "     \
 911         "console=$consoledev,$baudrate $othbootargs; "  \
 912         "tftp $ramdiskaddr $ramdiskfile;"       \
 913         "tftp $loadaddr $bootfile;"             \
 914         "tftp $fdtaddr $fdtfile;"               \
 915         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 916
 917 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 918
 919 #include <asm/fsl_secure_boot.h>
 920
 921 #endif  /* __CONFIG_H */