include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  18 #define CONFIG_SPL_SERIAL_SUPPORT
  19 #define CONFIG_SPL_MMC_SUPPORT
  20 #define CONFIG_SPL_MMC_MINIMAL
  21 #define CONFIG_SPL_FLUSH_IMAGE
  22 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  23 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  24 #define CONFIG_SYS_TEXT_BASE            0x11001000
  25 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  26 #define CONFIG_SPL_PAD_TO               0x20000
  27 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  28 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  29 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  30 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  31 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
  32 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  33 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  34 #define CONFIG_SPL_MMC_BOOT
  35 #ifdef CONFIG_SPL_BUILD
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #endif
  38 #endif
  39
  40 #ifdef CONFIG_SPIFLASH
  41 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  42 #define CONFIG_SPL_SERIAL_SUPPORT
  43 #define CONFIG_SPL_SPI_SUPPORT
  44 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  45 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  46 #define CONFIG_SPL_FLUSH_IMAGE
  47 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  48 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  49 #define CONFIG_SYS_TEXT_BASE            0x11001000
  50 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  51 #define CONFIG_SPL_PAD_TO               0x20000
  52 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
  57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  58 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  59 #define CONFIG_SPL_SPI_BOOT
  60 #ifdef CONFIG_SPL_BUILD
  61 #define CONFIG_SPL_COMMON_INIT_DDR
  62 #endif
  63 #endif
  64
  65 #define CONFIG_NAND_FSL_ELBC
  66 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  67 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  68
  69 #ifdef CONFIG_NAND
  70 #ifdef CONFIG_TPL_BUILD
  71 #define CONFIG_SPL_NAND_BOOT
  72 #define CONFIG_SPL_FLUSH_IMAGE
  73 #define CONFIG_TPL_NAND_INIT
  74 #define CONFIG_TPL_SERIAL_SUPPORT
  75 #define CONFIG_TPL_NAND_SUPPORT
  76 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  77 #define CONFIG_SPL_COMMON_INIT_DDR
  78 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  79 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  81 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  82 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  83 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  84 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  85 #elif defined(CONFIG_SPL_BUILD)
  86 #define CONFIG_SPL_INIT_MINIMAL
  87 #define CONFIG_SPL_SERIAL_SUPPORT
  88 #define CONFIG_SPL_NAND_SUPPORT
  89 #define CONFIG_SPL_FLUSH_IMAGE
  90 #define CONFIG_SPL_TEXT_BASE            0xff800000
  91 #define CONFIG_SPL_MAX_SIZE             4096
  92 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  93 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  94 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  95 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  96 #endif
  97 #define CONFIG_SPL_PAD_TO               0x20000
  98 #define CONFIG_TPL_PAD_TO               0x20000
  99 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 100 #define CONFIG_SYS_TEXT_BASE            0x11001000
 101 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 102 #endif
 103
 104 /* High Level Configuration Options */
 105 #define CONFIG_BOOKE                    /* BOOKE */
 106 #define CONFIG_E500                     /* BOOKE e500 family */
 107 #define CONFIG_P1022
 108 #define CONFIG_P1022DS
 109 #define CONFIG_MP                       /* support multiple processors */
 110
 111 #ifndef CONFIG_SYS_TEXT_BASE
 112 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 113 #endif
 114
 115 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 116 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 117 #endif
 118
 119 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 120 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 121 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 122 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 123 #define CONFIG_PCIE3                    /* PCIE controller 3 (ULI bridge) */
 124 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 125 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 126 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 127
 128 #define CONFIG_ENABLE_36BIT_PHYS
 129
 130 #ifdef CONFIG_PHYS_64BIT
 131 #define CONFIG_ADDR_MAP
 132 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 133 #endif
 134
 135 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 136
 137 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 138 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 139 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 140
 141 /*
 142  * These can be toggled for performance analysis, otherwise use default.
 143  */
 144 #define CONFIG_L2_CACHE
 145 #define CONFIG_BTB
 146
 147 #define CONFIG_SYS_MEMTEST_START        0x00000000
 148 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 149
 150 #define CONFIG_SYS_CCSRBAR              0xffe00000
 151 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 152
 153 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 154        SPL code*/
 155 #ifdef CONFIG_SPL_BUILD
 156 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 157 #endif
 158
 159 /* DDR Setup */
 160 #define CONFIG_DDR_SPD
 161 #define CONFIG_VERY_BIG_RAM
 162 #define CONFIG_SYS_FSL_DDR3
 163
 164 #ifdef CONFIG_DDR_ECC
 165 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 166 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 167 #endif
 168
 169 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 170 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 171
 172 #define CONFIG_NUM_DDR_CONTROLLERS      1
 173 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 174 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 175
 176 /* I2C addresses of SPD EEPROMs */
 177 #define CONFIG_SYS_SPD_BUS_NUM          1
 178 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 179
 180 /* These are used when DDR doesn't use SPD.  */
 181 #define CONFIG_SYS_SDRAM_SIZE           2048
 182 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 183 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 184 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 185 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 186 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 187 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 188 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 189 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 190 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 191 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 192 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 193 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 194 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 195 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 196 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 197 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 198 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 199 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 200 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 201 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 202
 203 /*
 204  * Memory map
 205  *
 206  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 207  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 208  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 209  *
 210  * Localbus cacheable (TBD)
 211  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 212  *
 213  * Localbus non-cacheable
 214  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 215  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 216  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 217  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 218  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 219  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 220  */
 221
 222 /*
 223  * Local Bus Definitions
 224  */
 225 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 226 #ifdef CONFIG_PHYS_64BIT
 227 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 228 #else
 229 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 230 #endif
 231
 232 #define CONFIG_FLASH_BR_PRELIM  \
 233         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 234 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 235
 236 #ifdef CONFIG_NAND
 237 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 238 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 239 #else
 240 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 241 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 242 #endif
 243
 244 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 245 #define CONFIG_SYS_FLASH_QUIET_TEST
 246 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 247
 248 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 249 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 250
 251 #ifndef CONFIG_SYS_MONITOR_BASE
 252 #ifdef CONFIG_SPL_BUILD
 253 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 254 #else
 255 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 256 #endif
 257 #endif
 258
 259 #define CONFIG_FLASH_CFI_DRIVER
 260 #define CONFIG_SYS_FLASH_CFI
 261 #define CONFIG_SYS_FLASH_EMPTY_INFO
 262
 263 /* Nand Flash */
 264 #if defined(CONFIG_NAND_FSL_ELBC)
 265 #define CONFIG_SYS_NAND_BASE            0xff800000
 266 #ifdef CONFIG_PHYS_64BIT
 267 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 268 #else
 269 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 270 #endif
 271
 272 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 273 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 274 #define CONFIG_CMD_NAND                 1
 275 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 276 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 277
 278 /* NAND flash config */
 279 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 280                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 281                                | BR_PS_8               /* Port Size = 8 bit */ \
 282                                | BR_MS_FCM             /* MSEL = FCM */ \
 283                                | BR_V)                 /* valid */
 284 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 285                                | OR_FCM_PGS            /* Large Page*/ \
 286                                | OR_FCM_CSCT \
 287                                | OR_FCM_CST \
 288                                | OR_FCM_CHT \
 289                                | OR_FCM_SCY_1 \
 290                                | OR_FCM_TRLX \
 291                                | OR_FCM_EHTR)
 292 #ifdef CONFIG_NAND
 293 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 294 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 295 #else
 296 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 297 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 298 #endif
 299
 300 #endif /* CONFIG_NAND_FSL_ELBC */
 301
 302 #define CONFIG_BOARD_EARLY_INIT_F
 303 #define CONFIG_BOARD_EARLY_INIT_R
 304 #define CONFIG_MISC_INIT_R
 305 #define CONFIG_HWCONFIG
 306
 307 #define CONFIG_FSL_NGPIXIS
 308 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 309 #ifdef CONFIG_PHYS_64BIT
 310 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 311 #else
 312 #define PIXIS_BASE_PHYS         PIXIS_BASE
 313 #endif
 314
 315 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 316 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 317
 318 #define PIXIS_LBMAP_SWITCH      7
 319 #define PIXIS_LBMAP_MASK        0xF0
 320 #define PIXIS_LBMAP_ALTBANK     0x20
 321 #define PIXIS_SPD               0x07
 322 #define PIXIS_SPD_SYSCLK_MASK   0x07
 323 #define PIXIS_ELBC_SPI_MASK     0xc0
 324 #define PIXIS_SPI               0x80
 325
 326 #define CONFIG_SYS_INIT_RAM_LOCK
 327 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 328 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 329
 330 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 331         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 332 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 333
 334 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 335 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 336
 337 /*
 338  * Config the L2 Cache as L2 SRAM
 339 */
 340 #if defined(CONFIG_SPL_BUILD)
 341 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 342 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 343 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 344 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 345 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 346 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 347 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 348 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 349 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 350 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 351 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 352 #elif defined(CONFIG_NAND)
 353 #ifdef CONFIG_TPL_BUILD
 354 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 355 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 356 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 357 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 358 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 359 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 360 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 361 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 362 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 363 #else
 364 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 365 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 366 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 367 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 368 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 369 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 370 #endif
 371 #endif
 372 #endif
 373
 374 /*
 375  * Serial Port
 376  */
 377 #define CONFIG_CONS_INDEX               1
 378 #define CONFIG_SYS_NS16550_SERIAL
 379 #define CONFIG_SYS_NS16550_REG_SIZE     1
 380 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 381 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 382 #define CONFIG_NS16550_MIN_FUNCTIONS
 383 #endif
 384
 385 #define CONFIG_SYS_BAUDRATE_TABLE       \
 386         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 387
 388 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 389 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 390
 391 /* Video */
 392
 393 #ifdef CONFIG_FSL_DIU_FB
 394 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 395 #define CONFIG_VIDEO
 396 #define CONFIG_CMD_BMP
 397 #define CONFIG_CFB_CONSOLE
 398 #define CONFIG_VIDEO_SW_CURSOR
 399 #define CONFIG_VGA_AS_SINGLE_DEVICE
 400 #define CONFIG_VIDEO_LOGO
 401 #define CONFIG_VIDEO_BMP_LOGO
 402 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 403 /*
 404  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 405  * disable empty flash sector detection, which is I/O-intensive.
 406  */
 407 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 408 #endif
 409
 410 #ifndef CONFIG_FSL_DIU_FB
 411 #endif
 412
 413 #ifdef CONFIG_ATI
 414 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 415 #define CONFIG_VIDEO
 416 #define CONFIG_BIOSEMU
 417 #define CONFIG_VIDEO_SW_CURSOR
 418 #define CONFIG_ATI_RADEON_FB
 419 #define CONFIG_VIDEO_LOGO
 420 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 421 #define CONFIG_CFB_CONSOLE
 422 #define CONFIG_VGA_AS_SINGLE_DEVICE
 423 #endif
 424
 425 /* I2C */
 426 #define CONFIG_SYS_I2C
 427 #define CONFIG_SYS_I2C_FSL
 428 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 429 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 430 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 431 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 432 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 433 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 434 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 435
 436 /*
 437  * I2C2 EEPROM
 438  */
 439 #define CONFIG_ID_EEPROM
 440 #define CONFIG_SYS_I2C_EEPROM_NXID
 441 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 442 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 443 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 444
 445 /*
 446  * eSPI - Enhanced SPI
 447  */
 448
 449 #define CONFIG_HARD_SPI
 450
 451 #define CONFIG_SF_DEFAULT_SPEED         10000000
 452 #define CONFIG_SF_DEFAULT_MODE          0
 453
 454 /*
 455  * General PCI
 456  * Memory space is mapped 1-1, but I/O space must start from 0.
 457  */
 458
 459 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 460 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 461 #ifdef CONFIG_PHYS_64BIT
 462 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 463 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 464 #else
 465 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 466 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 467 #endif
 468 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 469 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 470 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 471 #ifdef CONFIG_PHYS_64BIT
 472 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 473 #else
 474 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 475 #endif
 476 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 477
 478 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 479 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 480 #ifdef CONFIG_PHYS_64BIT
 481 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 482 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 483 #else
 484 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 485 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 486 #endif
 487 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 488 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 489 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 490 #ifdef CONFIG_PHYS_64BIT
 491 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 492 #else
 493 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 494 #endif
 495 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 496
 497 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 498 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 499 #ifdef CONFIG_PHYS_64BIT
 500 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 501 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 502 #else
 503 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 504 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 505 #endif
 506 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 507 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 508 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 509 #ifdef CONFIG_PHYS_64BIT
 510 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 511 #else
 512 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 513 #endif
 514 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 515
 516 #ifdef CONFIG_PCI
 517 #define CONFIG_PCI_INDIRECT_BRIDGE
 518 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 519 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 520 #endif
 521
 522 /* SATA */
 523 #define CONFIG_LIBATA
 524 #define CONFIG_FSL_SATA
 525 #define CONFIG_FSL_SATA_V2
 526
 527 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 528 #define CONFIG_SATA1
 529 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 530 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 531 #define CONFIG_SATA2
 532 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 533 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 534
 535 #ifdef CONFIG_FSL_SATA
 536 #define CONFIG_LBA48
 537 #define CONFIG_CMD_SATA
 538 #define CONFIG_DOS_PARTITION
 539 #endif
 540
 541 #define CONFIG_MMC
 542 #ifdef CONFIG_MMC
 543 #define CONFIG_FSL_ESDHC
 544 #define CONFIG_GENERIC_MMC
 545 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 546 #endif
 547
 548 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 549 #define CONFIG_DOS_PARTITION
 550 #endif
 551
 552 #define CONFIG_TSEC_ENET
 553 #ifdef CONFIG_TSEC_ENET
 554
 555 #define CONFIG_TSECV2
 556
 557 #define CONFIG_MII                      /* MII PHY management */
 558 #define CONFIG_TSEC1            1
 559 #define CONFIG_TSEC1_NAME       "eTSEC1"
 560 #define CONFIG_TSEC2            1
 561 #define CONFIG_TSEC2_NAME       "eTSEC2"
 562
 563 #define TSEC1_PHY_ADDR          1
 564 #define TSEC2_PHY_ADDR          2
 565
 566 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 567 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 568
 569 #define TSEC1_PHYIDX            0
 570 #define TSEC2_PHYIDX            0
 571
 572 #define CONFIG_ETHPRIME         "eTSEC1"
 573
 574 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 575 #endif
 576
 577 /*
 578  * Dynamic MTD Partition support with mtdparts
 579  */
 580 #define CONFIG_MTD_DEVICE
 581 #define CONFIG_MTD_PARTITIONS
 582 #define CONFIG_CMD_MTDPARTS
 583 #define CONFIG_FLASH_CFI_MTD
 584 #ifdef CONFIG_PHYS_64BIT
 585 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
 586 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
 587                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 588                         "512k(dtb),768k(u-boot)"
 589 #else
 590 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
 591 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
 592                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 593                         "512k(dtb),768k(u-boot)"
 594 #endif
 595
 596 /*
 597  * Environment
 598  */
 599 #ifdef CONFIG_SPIFLASH
 600 #define CONFIG_ENV_IS_IN_SPI_FLASH
 601 #define CONFIG_ENV_SPI_BUS      0
 602 #define CONFIG_ENV_SPI_CS       0
 603 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 604 #define CONFIG_ENV_SPI_MODE     0
 605 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 606 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 607 #define CONFIG_ENV_SECT_SIZE    0x10000
 608 #elif defined(CONFIG_SDCARD)
 609 #define CONFIG_ENV_IS_IN_MMC
 610 #define CONFIG_FSL_FIXED_MMC_LOCATION
 611 #define CONFIG_ENV_SIZE         0x2000
 612 #define CONFIG_SYS_MMC_ENV_DEV  0
 613 #elif defined(CONFIG_NAND)
 614 #ifdef CONFIG_TPL_BUILD
 615 #define CONFIG_ENV_SIZE         0x2000
 616 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 617 #else
 618 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 619 #endif
 620 #define CONFIG_ENV_IS_IN_NAND
 621 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 622 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 623 #elif defined(CONFIG_SYS_RAMBOOT)
 624 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 625 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 626 #define CONFIG_ENV_SIZE         0x2000
 627 #else
 628 #define CONFIG_ENV_IS_IN_FLASH
 629 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 630 #define CONFIG_ENV_SIZE         0x2000
 631 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 632 #endif
 633
 634 #define CONFIG_LOADS_ECHO
 635 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 636
 637 /*
 638  * Command line configuration.
 639  */
 640 #define CONFIG_CMD_ERRATA
 641 #define CONFIG_CMD_IRQ
 642 #define CONFIG_CMD_REGINFO
 643
 644 #ifdef CONFIG_PCI
 645 #define CONFIG_CMD_PCI
 646 #endif
 647
 648 /*
 649  * USB
 650  */
 651 #define CONFIG_HAS_FSL_DR_USB
 652 #ifdef CONFIG_HAS_FSL_DR_USB
 653 #define CONFIG_USB_EHCI
 654
 655 #ifdef CONFIG_USB_EHCI
 656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 657 #define CONFIG_USB_EHCI_FSL
 658 #endif
 659 #endif
 660
 661 /*
 662  * Miscellaneous configurable options
 663  */
 664 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 665 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 666 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 667 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 668 #ifdef CONFIG_CMD_KGDB
 669 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 670 #else
 671 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 672 #endif
 673 /* Print Buffer Size */
 674 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 675 #define CONFIG_SYS_MAXARGS      16
 676 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 677
 678 /*
 679  * For booting Linux, the board info and command line data
 680  * have to be in the first 64 MB of memory, since this is
 681  * the maximum mapped by the Linux kernel during initialization.
 682  */
 683 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 684 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 685
 686 #ifdef CONFIG_CMD_KGDB
 687 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 688 #endif
 689
 690 /*
 691  * Environment Configuration
 692  */
 693
 694 #define CONFIG_HOSTNAME         p1022ds
 695 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 696 #define CONFIG_BOOTFILE         "uImage"
 697 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 698
 699 #define CONFIG_LOADADDR         1000000
 700
 701
 702 #define CONFIG_BAUDRATE 115200
 703
 704 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 705         "netdev=eth0\0"                                         \
 706         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 707         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 708         "tftpflash=tftpboot $loadaddr $uboot && "               \
 709                 "protect off $ubootaddr +$filesize && "         \
 710                 "erase $ubootaddr +$filesize && "               \
 711                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 712                 "protect on $ubootaddr +$filesize && "          \
 713                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 714         "consoledev=ttyS0\0"                                    \
 715         "ramdiskaddr=2000000\0"                                 \
 716         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 717         "fdtaddr=1e00000\0"                                     \
 718         "fdtfile=p1022ds.dtb\0"                                 \
 719         "bdev=sda3\0"                                           \
 720         "hwconfig=esdhc;audclk:12\0"
 721
 722 #define CONFIG_HDBOOT                                   \
 723         "setenv bootargs root=/dev/$bdev rw "           \
 724         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 725         "tftp $loadaddr $bootfile;"                     \
 726         "tftp $fdtaddr $fdtfile;"                       \
 727         "bootm $loadaddr - $fdtaddr"
 728
 729 #define CONFIG_NFSBOOTCOMMAND                                           \
 730         "setenv bootargs root=/dev/nfs rw "                             \
 731         "nfsroot=$serverip:$rootpath "                                  \
 732         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 733         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 734         "tftp $loadaddr $bootfile;"                                     \
 735         "tftp $fdtaddr $fdtfile;"                                       \
 736         "bootm $loadaddr - $fdtaddr"
 737
 738 #define CONFIG_RAMBOOTCOMMAND                                           \
 739         "setenv bootargs root=/dev/ram rw "                             \
 740         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 741         "tftp $ramdiskaddr $ramdiskfile;"                               \
 742         "tftp $loadaddr $bootfile;"                                     \
 743         "tftp $fdtaddr $fdtfile;"                                       \
 744         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 745
 746 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 747
 748 #endif