include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  18 #define CONFIG_SPL_ENV_SUPPORT
  19 #define CONFIG_SPL_SERIAL_SUPPORT
  20 #define CONFIG_SPL_MMC_SUPPORT
  21 #define CONFIG_SPL_MMC_MINIMAL
  22 #define CONFIG_SPL_FLUSH_IMAGE
  23 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  24 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  25 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  26 #define CONFIG_SPL_I2C_SUPPORT
  27 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  28 #define CONFIG_SYS_TEXT_BASE            0x11001000
  29 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  30 #define CONFIG_SPL_PAD_TO               0x20000
  31 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  32 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  33 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  34 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  35 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  38 #define CONFIG_SPL_MMC_BOOT
  39 #ifdef CONFIG_SPL_BUILD
  40 #define CONFIG_SPL_COMMON_INIT_DDR
  41 #endif
  42 #endif
  43
  44 #ifdef CONFIG_SPIFLASH
  45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  46 #define CONFIG_SPL_ENV_SUPPORT
  47 #define CONFIG_SPL_SERIAL_SUPPORT
  48 #define CONFIG_SPL_SPI_SUPPORT
  49 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  51 #define CONFIG_SPL_FLUSH_IMAGE
  52 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  53 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  54 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  55 #define CONFIG_SPL_I2C_SUPPORT
  56 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  57 #define CONFIG_SYS_TEXT_BASE            0x11001000
  58 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  59 #define CONFIG_SPL_PAD_TO               0x20000
  60 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
  65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  67 #define CONFIG_SPL_SPI_BOOT
  68 #ifdef CONFIG_SPL_BUILD
  69 #define CONFIG_SPL_COMMON_INIT_DDR
  70 #endif
  71 #endif
  72
  73 #define CONFIG_NAND_FSL_ELBC
  74 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  75 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  76
  77 #ifdef CONFIG_NAND
  78 #ifdef CONFIG_TPL_BUILD
  79 #define CONFIG_SPL_NAND_BOOT
  80 #define CONFIG_SPL_FLUSH_IMAGE
  81 #define CONFIG_SPL_ENV_SUPPORT
  82 #define CONFIG_SPL_NAND_INIT
  83 #define CONFIG_SPL_SERIAL_SUPPORT
  84 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  85 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  86 #define CONFIG_SPL_I2C_SUPPORT
  87 #define CONFIG_SPL_NAND_SUPPORT
  88 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  89 #define CONFIG_SPL_COMMON_INIT_DDR
  90 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  91 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  93 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  94 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  95 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  96 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  97 #elif defined(CONFIG_SPL_BUILD)
  98 #define CONFIG_SPL_INIT_MINIMAL
  99 #define CONFIG_SPL_SERIAL_SUPPORT
 100 #define CONFIG_SPL_NAND_SUPPORT
 101 #define CONFIG_SPL_FLUSH_IMAGE
 102 #define CONFIG_SPL_TEXT_BASE            0xff800000
 103 #define CONFIG_SPL_MAX_SIZE             4096
 104 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 105 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 106 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 107 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 108 #endif
 109 #define CONFIG_SPL_PAD_TO               0x20000
 110 #define CONFIG_TPL_PAD_TO               0x20000
 111 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 112 #define CONFIG_SYS_TEXT_BASE            0x11001000
 113 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 114 #endif
 115
 116 /* High Level Configuration Options */
 117 #define CONFIG_BOOKE                    /* BOOKE */
 118 #define CONFIG_E500                     /* BOOKE e500 family */
 119 #define CONFIG_P1022
 120 #define CONFIG_P1022DS
 121 #define CONFIG_MP                       /* support multiple processors */
 122
 123 #ifndef CONFIG_SYS_TEXT_BASE
 124 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 125 #endif
 126
 127 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 128 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 129 #endif
 130
 131 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 132 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 133 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 134 #define CONFIG_PCIE2                    /* PCIE controller 2 (slot 2) */
 135 #define CONFIG_PCIE3                    /* PCIE controller 3 (ULI bridge) */
 136 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 137 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 138 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 139
 140 #define CONFIG_ENABLE_36BIT_PHYS
 141
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_ADDR_MAP
 144 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 145 #endif
 146
 147 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 148
 149 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 150 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 151 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 152
 153 /*
 154  * These can be toggled for performance analysis, otherwise use default.
 155  */
 156 #define CONFIG_L2_CACHE
 157 #define CONFIG_BTB
 158
 159 #define CONFIG_SYS_MEMTEST_START        0x00000000
 160 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 161
 162 #define CONFIG_SYS_CCSRBAR              0xffe00000
 163 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 164
 165 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 166        SPL code*/
 167 #ifdef CONFIG_SPL_BUILD
 168 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 169 #endif
 170
 171 /* DDR Setup */
 172 #define CONFIG_DDR_SPD
 173 #define CONFIG_VERY_BIG_RAM
 174 #define CONFIG_SYS_FSL_DDR3
 175
 176 #ifdef CONFIG_DDR_ECC
 177 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 178 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 179 #endif
 180
 181 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 182 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 183
 184 #define CONFIG_NUM_DDR_CONTROLLERS      1
 185 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 186 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 187
 188 /* I2C addresses of SPD EEPROMs */
 189 #define CONFIG_SYS_SPD_BUS_NUM          1
 190 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 191
 192 /* These are used when DDR doesn't use SPD.  */
 193 #define CONFIG_SYS_SDRAM_SIZE           2048
 194 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 195 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 196 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 197 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 198 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 199 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 200 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 201 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 202 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 203 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 204 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 205 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 206 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 207 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 208 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 209 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 210 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 211 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 212 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 213 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 214
 215 /*
 216  * Memory map
 217  *
 218  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 219  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 220  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 221  *
 222  * Localbus cacheable (TBD)
 223  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 224  *
 225  * Localbus non-cacheable
 226  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 227  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 228  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 229  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 230  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 231  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 232  */
 233
 234 /*
 235  * Local Bus Definitions
 236  */
 237 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 238 #ifdef CONFIG_PHYS_64BIT
 239 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 240 #else
 241 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 242 #endif
 243
 244 #define CONFIG_FLASH_BR_PRELIM  \
 245         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 246 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 247
 248 #ifdef CONFIG_NAND
 249 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 250 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 251 #else
 252 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 253 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 254 #endif
 255
 256 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 257 #define CONFIG_SYS_FLASH_QUIET_TEST
 258 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 259
 260 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 261 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 262
 263 #ifndef CONFIG_SYS_MONITOR_BASE
 264 #ifdef CONFIG_SPL_BUILD
 265 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 266 #else
 267 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 268 #endif
 269 #endif
 270
 271 #define CONFIG_FLASH_CFI_DRIVER
 272 #define CONFIG_SYS_FLASH_CFI
 273 #define CONFIG_SYS_FLASH_EMPTY_INFO
 274
 275 /* Nand Flash */
 276 #if defined(CONFIG_NAND_FSL_ELBC)
 277 #define CONFIG_SYS_NAND_BASE            0xff800000
 278 #ifdef CONFIG_PHYS_64BIT
 279 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 280 #else
 281 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 282 #endif
 283
 284 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 285 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 286 #define CONFIG_CMD_NAND                 1
 287 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 288 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 289
 290 /* NAND flash config */
 291 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 292                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 293                                | BR_PS_8               /* Port Size = 8 bit */ \
 294                                | BR_MS_FCM             /* MSEL = FCM */ \
 295                                | BR_V)                 /* valid */
 296 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 297                                | OR_FCM_PGS            /* Large Page*/ \
 298                                | OR_FCM_CSCT \
 299                                | OR_FCM_CST \
 300                                | OR_FCM_CHT \
 301                                | OR_FCM_SCY_1 \
 302                                | OR_FCM_TRLX \
 303                                | OR_FCM_EHTR)
 304 #ifdef CONFIG_NAND
 305 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 306 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 307 #else
 308 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 309 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 310 #endif
 311
 312 #endif /* CONFIG_NAND_FSL_ELBC */
 313
 314 #define CONFIG_BOARD_EARLY_INIT_F
 315 #define CONFIG_BOARD_EARLY_INIT_R
 316 #define CONFIG_MISC_INIT_R
 317 #define CONFIG_HWCONFIG
 318
 319 #define CONFIG_FSL_NGPIXIS
 320 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 321 #ifdef CONFIG_PHYS_64BIT
 322 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 323 #else
 324 #define PIXIS_BASE_PHYS         PIXIS_BASE
 325 #endif
 326
 327 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 328 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 329
 330 #define PIXIS_LBMAP_SWITCH      7
 331 #define PIXIS_LBMAP_MASK        0xF0
 332 #define PIXIS_LBMAP_ALTBANK     0x20
 333 #define PIXIS_SPD               0x07
 334 #define PIXIS_SPD_SYSCLK_MASK   0x07
 335 #define PIXIS_ELBC_SPI_MASK     0xc0
 336 #define PIXIS_SPI               0x80
 337
 338 #define CONFIG_SYS_INIT_RAM_LOCK
 339 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 340 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 341
 342 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 343         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 344 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 345
 346 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 347 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 348
 349 /*
 350  * Config the L2 Cache as L2 SRAM
 351 */
 352 #if defined(CONFIG_SPL_BUILD)
 353 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 354 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 355 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 356 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 357 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 358 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 359 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 360 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 361 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 362 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 363 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 364 #elif defined(CONFIG_NAND)
 365 #ifdef CONFIG_TPL_BUILD
 366 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 367 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 368 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 369 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 370 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 371 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 372 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 373 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 374 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 375 #else
 376 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 377 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 378 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 379 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 380 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 381 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 382 #endif
 383 #endif
 384 #endif
 385
 386 /*
 387  * Serial Port
 388  */
 389 #define CONFIG_CONS_INDEX               1
 390 #define CONFIG_SYS_NS16550_SERIAL
 391 #define CONFIG_SYS_NS16550_REG_SIZE     1
 392 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 393 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 394 #define CONFIG_NS16550_MIN_FUNCTIONS
 395 #endif
 396
 397 #define CONFIG_SYS_BAUDRATE_TABLE       \
 398         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 399
 400 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 401 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 402
 403 /* Video */
 404
 405 #ifdef CONFIG_FSL_DIU_FB
 406 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 407 #define CONFIG_VIDEO
 408 #define CONFIG_CMD_BMP
 409 #define CONFIG_CFB_CONSOLE
 410 #define CONFIG_VIDEO_SW_CURSOR
 411 #define CONFIG_VGA_AS_SINGLE_DEVICE
 412 #define CONFIG_VIDEO_LOGO
 413 #define CONFIG_VIDEO_BMP_LOGO
 414 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 415 /*
 416  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 417  * disable empty flash sector detection, which is I/O-intensive.
 418  */
 419 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 420 #endif
 421
 422 #ifndef CONFIG_FSL_DIU_FB
 423 #endif
 424
 425 #ifdef CONFIG_ATI
 426 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 427 #define CONFIG_VIDEO
 428 #define CONFIG_BIOSEMU
 429 #define CONFIG_VIDEO_SW_CURSOR
 430 #define CONFIG_ATI_RADEON_FB
 431 #define CONFIG_VIDEO_LOGO
 432 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 433 #define CONFIG_CFB_CONSOLE
 434 #define CONFIG_VGA_AS_SINGLE_DEVICE
 435 #endif
 436
 437 /* I2C */
 438 #define CONFIG_SYS_I2C
 439 #define CONFIG_SYS_I2C_FSL
 440 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 441 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 442 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 443 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 444 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 445 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 446 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 447
 448 /*
 449  * I2C2 EEPROM
 450  */
 451 #define CONFIG_ID_EEPROM
 452 #define CONFIG_SYS_I2C_EEPROM_NXID
 453 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 454 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 455 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 456
 457 /*
 458  * eSPI - Enhanced SPI
 459  */
 460
 461 #define CONFIG_HARD_SPI
 462
 463 #define CONFIG_SF_DEFAULT_SPEED         10000000
 464 #define CONFIG_SF_DEFAULT_MODE          0
 465
 466 /*
 467  * General PCI
 468  * Memory space is mapped 1-1, but I/O space must start from 0.
 469  */
 470
 471 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 472 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 473 #ifdef CONFIG_PHYS_64BIT
 474 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 475 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 476 #else
 477 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 478 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 479 #endif
 480 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 481 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 482 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 483 #ifdef CONFIG_PHYS_64BIT
 484 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 485 #else
 486 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 487 #endif
 488 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 489
 490 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 491 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 492 #ifdef CONFIG_PHYS_64BIT
 493 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 494 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 495 #else
 496 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 497 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 498 #endif
 499 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 500 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 501 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 502 #ifdef CONFIG_PHYS_64BIT
 503 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 504 #else
 505 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 506 #endif
 507 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 508
 509 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 510 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 511 #ifdef CONFIG_PHYS_64BIT
 512 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 513 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 514 #else
 515 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 516 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 517 #endif
 518 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 519 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 520 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 521 #ifdef CONFIG_PHYS_64BIT
 522 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 523 #else
 524 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 525 #endif
 526 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 527
 528 #ifdef CONFIG_PCI
 529 #define CONFIG_PCI_INDIRECT_BRIDGE
 530 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 531 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 532 #endif
 533
 534 /* SATA */
 535 #define CONFIG_LIBATA
 536 #define CONFIG_FSL_SATA
 537 #define CONFIG_FSL_SATA_V2
 538
 539 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 540 #define CONFIG_SATA1
 541 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 542 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 543 #define CONFIG_SATA2
 544 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 545 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 546
 547 #ifdef CONFIG_FSL_SATA
 548 #define CONFIG_LBA48
 549 #define CONFIG_CMD_SATA
 550 #define CONFIG_DOS_PARTITION
 551 #endif
 552
 553 #define CONFIG_MMC
 554 #ifdef CONFIG_MMC
 555 #define CONFIG_FSL_ESDHC
 556 #define CONFIG_GENERIC_MMC
 557 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 558 #endif
 559
 560 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 561 #define CONFIG_DOS_PARTITION
 562 #endif
 563
 564 #define CONFIG_TSEC_ENET
 565 #ifdef CONFIG_TSEC_ENET
 566
 567 #define CONFIG_TSECV2
 568
 569 #define CONFIG_MII                      /* MII PHY management */
 570 #define CONFIG_TSEC1            1
 571 #define CONFIG_TSEC1_NAME       "eTSEC1"
 572 #define CONFIG_TSEC2            1
 573 #define CONFIG_TSEC2_NAME       "eTSEC2"
 574
 575 #define TSEC1_PHY_ADDR          1
 576 #define TSEC2_PHY_ADDR          2
 577
 578 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 579 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 580
 581 #define TSEC1_PHYIDX            0
 582 #define TSEC2_PHYIDX            0
 583
 584 #define CONFIG_ETHPRIME         "eTSEC1"
 585
 586 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 587 #endif
 588
 589 /*
 590  * Dynamic MTD Partition support with mtdparts
 591  */
 592 #define CONFIG_MTD_DEVICE
 593 #define CONFIG_MTD_PARTITIONS
 594 #define CONFIG_CMD_MTDPARTS
 595 #define CONFIG_FLASH_CFI_MTD
 596 #ifdef CONFIG_PHYS_64BIT
 597 #define MTDIDS_DEFAULT "nor0=fe8000000.nor"
 598 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
 599                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 600                         "512k(dtb),768k(u-boot)"
 601 #else
 602 #define MTDIDS_DEFAULT "nor0=e8000000.nor"
 603 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
 604                         "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
 605                         "512k(dtb),768k(u-boot)"
 606 #endif
 607
 608 /*
 609  * Environment
 610  */
 611 #ifdef CONFIG_SPIFLASH
 612 #define CONFIG_ENV_IS_IN_SPI_FLASH
 613 #define CONFIG_ENV_SPI_BUS      0
 614 #define CONFIG_ENV_SPI_CS       0
 615 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 616 #define CONFIG_ENV_SPI_MODE     0
 617 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 618 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 619 #define CONFIG_ENV_SECT_SIZE    0x10000
 620 #elif defined(CONFIG_SDCARD)
 621 #define CONFIG_ENV_IS_IN_MMC
 622 #define CONFIG_FSL_FIXED_MMC_LOCATION
 623 #define CONFIG_ENV_SIZE         0x2000
 624 #define CONFIG_SYS_MMC_ENV_DEV  0
 625 #elif defined(CONFIG_NAND)
 626 #ifdef CONFIG_TPL_BUILD
 627 #define CONFIG_ENV_SIZE         0x2000
 628 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 629 #else
 630 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 631 #endif
 632 #define CONFIG_ENV_IS_IN_NAND
 633 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 634 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 635 #elif defined(CONFIG_SYS_RAMBOOT)
 636 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 637 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 638 #define CONFIG_ENV_SIZE         0x2000
 639 #else
 640 #define CONFIG_ENV_IS_IN_FLASH
 641 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 642 #define CONFIG_ENV_SIZE         0x2000
 643 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 644 #endif
 645
 646 #define CONFIG_LOADS_ECHO
 647 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 648
 649 /*
 650  * Command line configuration.
 651  */
 652 #define CONFIG_CMD_ERRATA
 653 #define CONFIG_CMD_IRQ
 654 #define CONFIG_CMD_REGINFO
 655
 656 #ifdef CONFIG_PCI
 657 #define CONFIG_CMD_PCI
 658 #endif
 659
 660 /*
 661  * USB
 662  */
 663 #define CONFIG_HAS_FSL_DR_USB
 664 #ifdef CONFIG_HAS_FSL_DR_USB
 665 #define CONFIG_USB_EHCI
 666
 667 #ifdef CONFIG_USB_EHCI
 668 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 669 #define CONFIG_USB_EHCI_FSL
 670 #define CONFIG_USB_STORAGE
 671 #endif
 672 #endif
 673
 674 /*
 675  * Miscellaneous configurable options
 676  */
 677 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 678 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 679 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 680 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 681 #ifdef CONFIG_CMD_KGDB
 682 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 683 #else
 684 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 685 #endif
 686 /* Print Buffer Size */
 687 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 688 #define CONFIG_SYS_MAXARGS      16
 689 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 690
 691 /*
 692  * For booting Linux, the board info and command line data
 693  * have to be in the first 64 MB of memory, since this is
 694  * the maximum mapped by the Linux kernel during initialization.
 695  */
 696 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 697 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 698
 699 #ifdef CONFIG_CMD_KGDB
 700 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 701 #endif
 702
 703 /*
 704  * Environment Configuration
 705  */
 706
 707 #define CONFIG_HOSTNAME         p1022ds
 708 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 709 #define CONFIG_BOOTFILE         "uImage"
 710 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 711
 712 #define CONFIG_LOADADDR         1000000
 713
 714
 715 #define CONFIG_BAUDRATE 115200
 716
 717 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 718         "netdev=eth0\0"                                         \
 719         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 720         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 721         "tftpflash=tftpboot $loadaddr $uboot && "               \
 722                 "protect off $ubootaddr +$filesize && "         \
 723                 "erase $ubootaddr +$filesize && "               \
 724                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 725                 "protect on $ubootaddr +$filesize && "          \
 726                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 727         "consoledev=ttyS0\0"                                    \
 728         "ramdiskaddr=2000000\0"                                 \
 729         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 730         "fdtaddr=1e00000\0"                                     \
 731         "fdtfile=p1022ds.dtb\0"                                 \
 732         "bdev=sda3\0"                                           \
 733         "hwconfig=esdhc;audclk:12\0"
 734
 735 #define CONFIG_HDBOOT                                   \
 736         "setenv bootargs root=/dev/$bdev rw "           \
 737         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 738         "tftp $loadaddr $bootfile;"                     \
 739         "tftp $fdtaddr $fdtfile;"                       \
 740         "bootm $loadaddr - $fdtaddr"
 741
 742 #define CONFIG_NFSBOOTCOMMAND                                           \
 743         "setenv bootargs root=/dev/nfs rw "                             \
 744         "nfsroot=$serverip:$rootpath "                                  \
 745         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 746         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 747         "tftp $loadaddr $bootfile;"                                     \
 748         "tftp $fdtaddr $fdtfile;"                                       \
 749         "bootm $loadaddr - $fdtaddr"
 750
 751 #define CONFIG_RAMBOOTCOMMAND                                           \
 752         "setenv bootargs root=/dev/ram rw "                             \
 753         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 754         "tftp $ramdiskaddr $ramdiskfile;"                               \
 755         "tftp $loadaddr $bootfile;"                                     \
 756         "tftp $fdtaddr $fdtfile;"                                       \
 757         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 758
 759 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 760
 761 #endif