include/configs/P1022DS.h

   1 /*
   2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include "../board/freescale/common/ics307_clk.h"
  13
  14 #ifdef CONFIG_36BIT
  15 #define CONFIG_PHYS_64BIT
  16 #endif
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_SPL
  20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  21 #define CONFIG_SPL_ENV_SUPPORT
  22 #define CONFIG_SPL_SERIAL_SUPPORT
  23 #define CONFIG_SPL_MMC_SUPPORT
  24 #define CONFIG_SPL_MMC_MINIMAL
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  27 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  28 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  29 #define CONFIG_SPL_I2C_SUPPORT
  30 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  31 #define CONFIG_SYS_TEXT_BASE            0x11001000
  32 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  33 #define CONFIG_SPL_PAD_TO               0x18000
  34 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  35 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
  36 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
  37 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
  38 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  41 #define CONFIG_SPL_MMC_BOOT
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #endif
  45 #endif
  46
  47 #ifdef CONFIG_SPIFLASH
  48 #define CONFIG_SPL
  49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  50 #define CONFIG_SPL_ENV_SUPPORT
  51 #define CONFIG_SPL_SERIAL_SUPPORT
  52 #define CONFIG_SPL_SPI_SUPPORT
  53 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SPL_FLUSH_IMAGE
  56 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  57 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  58 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  59 #define CONFIG_SPL_I2C_SUPPORT
  60 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  61 #define CONFIG_SYS_TEXT_BASE            0x11001000
  62 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  63 #define CONFIG_SPL_PAD_TO               0x18000
  64 #define CONFIG_SPL_MAX_SIZE             (96 * 1024)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (512 << 10)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (96 << 10)
  69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  70 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  71 #define CONFIG_SPL_SPI_BOOT
  72 #ifdef CONFIG_SPL_BUILD
  73 #define CONFIG_SPL_COMMON_INIT_DDR
  74 #endif
  75 #endif
  76
  77 #define CONFIG_NAND_FSL_ELBC
  78 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  79 #define CONFIG_SYS_NAND_MAX_OOBFREE     5
  80
  81 #ifdef CONFIG_NAND
  82 #define CONFIG_SPL
  83 #define CONFIG_TPL
  84 #ifdef CONFIG_TPL_BUILD
  85 #define CONFIG_SPL_NAND_BOOT
  86 #define CONFIG_SPL_FLUSH_IMAGE
  87 #define CONFIG_SPL_ENV_SUPPORT
  88 #define CONFIG_SPL_NAND_INIT
  89 #define CONFIG_SPL_SERIAL_SUPPORT
  90 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  91 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  92 #define CONFIG_SPL_I2C_SUPPORT
  93 #define CONFIG_SPL_NAND_SUPPORT
  94 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  95 #define CONFIG_SPL_COMMON_INIT_DDR
  96 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  97 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  99 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (576 << 10)
 100 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 101 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 103 #elif defined(CONFIG_SPL_BUILD)
 104 #define CONFIG_SPL_INIT_MINIMAL
 105 #define CONFIG_SPL_SERIAL_SUPPORT
 106 #define CONFIG_SPL_NAND_SUPPORT
 107 #define CONFIG_SPL_FLUSH_IMAGE
 108 #define CONFIG_SPL_TEXT_BASE            0xff800000
 109 #define CONFIG_SPL_MAX_SIZE             4096
 110 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 111 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 112 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 113 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 114 #endif
 115 #define CONFIG_SPL_PAD_TO               0x20000
 116 #define CONFIG_TPL_PAD_TO               0x20000
 117 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 118 #define CONFIG_SYS_TEXT_BASE            0x11001000
 119 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 120 #endif
 121
 122 /* High Level Configuration Options */
 123 #define CONFIG_BOOKE                    /* BOOKE */
 124 #define CONFIG_E500                     /* BOOKE e500 family */
 125 #define CONFIG_MPC85xx                  /* MPC8540/60/55/41/48 */
 126 #define CONFIG_P1022
 127 #define CONFIG_P1022DS
 128 #define CONFIG_MP                       /* support multiple processors */
 129
 130 #ifndef CONFIG_SYS_TEXT_BASE
 131 #define CONFIG_SYS_TEXT_BASE    0xeff80000
 132 #endif
 133
 134 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 135 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 136 #endif
 137
 138 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 139 #define CONFIG_PCI                      /* Enable PCI/PCIE */
 140 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
 141 #define CONFIG_PCIE2                    /* PCIE controler 2 (slot 2) */
 142 #define CONFIG_PCIE3                    /* PCIE controler 3 (ULI bridge) */
 143 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 144 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 145 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 146
 147 #define CONFIG_ENABLE_36BIT_PHYS
 148
 149 #ifdef CONFIG_PHYS_64BIT
 150 #define CONFIG_ADDR_MAP
 151 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 152 #endif
 153
 154 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 155
 156 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 157 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 158 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
 159
 160 /*
 161  * These can be toggled for performance analysis, otherwise use default.
 162  */
 163 #define CONFIG_L2_CACHE
 164 #define CONFIG_BTB
 165
 166 #define CONFIG_SYS_MEMTEST_START        0x00000000
 167 #define CONFIG_SYS_MEMTEST_END          0x7fffffff
 168
 169 #define CONFIG_SYS_CCSRBAR              0xffe00000
 170 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 171
 172 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 173        SPL code*/
 174 #ifdef CONFIG_SPL_BUILD
 175 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 176 #endif
 177
 178
 179 /* DDR Setup */
 180 #define CONFIG_DDR_SPD
 181 #define CONFIG_VERY_BIG_RAM
 182 #define CONFIG_SYS_FSL_DDR3
 183
 184 #ifdef CONFIG_DDR_ECC
 185 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 186 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 187 #endif
 188
 189 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 190 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 191
 192 #define CONFIG_NUM_DDR_CONTROLLERS      1
 193 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 194 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 195
 196 /* I2C addresses of SPD EEPROMs */
 197 #define CONFIG_SYS_SPD_BUS_NUM          1
 198 #define SPD_EEPROM_ADDRESS              0x51    /* CTLR 0 DIMM 0 */
 199
 200 /* These are used when DDR doesn't use SPD.  */
 201 #define CONFIG_SYS_SDRAM_SIZE           2048
 202 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 203 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 204 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 205 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 206 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014202
 207 #define CONFIG_SYS_DDR_TIMING_3         0x00010000
 208 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 209 #define CONFIG_SYS_DDR_TIMING_1         0x5c5bd746
 210 #define CONFIG_SYS_DDR_TIMING_2         0x0fa8d4ca
 211 #define CONFIG_SYS_DDR_MODE_1           0x00441221
 212 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 213 #define CONFIG_SYS_DDR_INTERVAL         0x0a280100
 214 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 215 #define CONFIG_SYS_DDR_CLK_CTRL         0x02800000
 216 #define CONFIG_SYS_DDR_CONTROL          0xc7000008
 217 #define CONFIG_SYS_DDR_CONTROL_2        0x24401041
 218 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 219 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 220 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 221 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8675f608
 222
 223
 224 /*
 225  * Memory map
 226  *
 227  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 228  * 0x8000_0000  0xdfff_ffff     PCI Express Mem         1.5G non-cacheable
 229  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
 230  *
 231  * Localbus cacheable (TBD)
 232  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 233  *
 234  * Localbus non-cacheable
 235  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
 236  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 237  * 0xff80_0000  0xff80_7fff     NAND                    32K non-cacheable
 238  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 239  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 240  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 241  */
 242
 243 /*
 244  * Local Bus Definitions
 245  */
 246 #define CONFIG_SYS_FLASH_BASE           0xe8000000 /* start of FLASH 128M */
 247 #ifdef CONFIG_PHYS_64BIT
 248 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 249 #else
 250 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 251 #endif
 252
 253 #define CONFIG_FLASH_BR_PRELIM  \
 254         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 255 #define CONFIG_FLASH_OR_PRELIM  (OR_AM_128MB | 0xff7)
 256
 257 #ifdef CONFIG_NAND
 258 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 259 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 260 #else
 261 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 262 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 263 #endif
 264
 265 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 266 #define CONFIG_SYS_FLASH_QUIET_TEST
 267 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 268
 269 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 270 #define CONFIG_SYS_MAX_FLASH_SECT       1024
 271
 272 #ifndef CONFIG_SYS_MONITOR_BASE
 273 #ifdef CONFIG_SPL_BUILD
 274 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 275 #else
 276 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 277 #endif
 278 #endif
 279
 280 #define CONFIG_FLASH_CFI_DRIVER
 281 #define CONFIG_SYS_FLASH_CFI
 282 #define CONFIG_SYS_FLASH_EMPTY_INFO
 283
 284 /* Nand Flash */
 285 #if defined(CONFIG_NAND_FSL_ELBC)
 286 #define CONFIG_SYS_NAND_BASE            0xff800000
 287 #ifdef CONFIG_PHYS_64BIT
 288 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 289 #else
 290 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 291 #endif
 292
 293 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 294 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 295 #define CONFIG_MTD_NAND_VERIFY_WRITE
 296 #define CONFIG_CMD_NAND                 1
 297 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 298 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
 299
 300 /* NAND flash config */
 301 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 302                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 303                                | BR_PS_8               /* Port Size = 8 bit */ \
 304                                | BR_MS_FCM             /* MSEL = FCM */ \
 305                                | BR_V)                 /* valid */
 306 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB         /* length 256K */ \
 307                                | OR_FCM_PGS            /* Large Page*/ \
 308                                | OR_FCM_CSCT \
 309                                | OR_FCM_CST \
 310                                | OR_FCM_CHT \
 311                                | OR_FCM_SCY_1 \
 312                                | OR_FCM_TRLX \
 313                                | OR_FCM_EHTR)
 314 #ifdef CONFIG_NAND
 315 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 316 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 317 #else
 318 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 319 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 320 #endif
 321
 322 #endif /* CONFIG_NAND_FSL_ELBC */
 323
 324 #define CONFIG_BOARD_EARLY_INIT_F
 325 #define CONFIG_BOARD_EARLY_INIT_R
 326 #define CONFIG_MISC_INIT_R
 327 #define CONFIG_HWCONFIG
 328
 329 #define CONFIG_FSL_NGPIXIS
 330 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 331 #ifdef CONFIG_PHYS_64BIT
 332 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 333 #else
 334 #define PIXIS_BASE_PHYS         PIXIS_BASE
 335 #endif
 336
 337 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 338 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB | 0x6ff7)
 339
 340 #define PIXIS_LBMAP_SWITCH      7
 341 #define PIXIS_LBMAP_MASK        0xF0
 342 #define PIXIS_LBMAP_ALTBANK     0x20
 343 #define PIXIS_SPD               0x07
 344 #define PIXIS_SPD_SYSCLK_MASK   0x07
 345 #define PIXIS_ELBC_SPI_MASK     0xc0
 346 #define PIXIS_SPI               0x80
 347
 348 #define CONFIG_SYS_INIT_RAM_LOCK
 349 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 350 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000 /* Size of used area in RAM */
 351
 352 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 353         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 354 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 355
 356 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 357 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 358
 359 /*
 360  * Config the L2 Cache as L2 SRAM
 361 */
 362 #if defined(CONFIG_SPL_BUILD)
 363 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 364 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
 365 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 366 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 367 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 368 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 369 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 370 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 371 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 372 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
 373 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 374 #elif defined(CONFIG_NAND)
 375 #ifdef CONFIG_TPL_BUILD
 376 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 377 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 378 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 379 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 380 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 381 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 382 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 383 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 384 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 385 #else
 386 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 387 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 388 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 389 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 390 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 391 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 392 #endif
 393 #endif
 394 #endif
 395
 396 /*
 397  * Serial Port
 398  */
 399 #define CONFIG_CONS_INDEX               1
 400 #define CONFIG_SYS_NS16550
 401 #define CONFIG_SYS_NS16550_SERIAL
 402 #define CONFIG_SYS_NS16550_REG_SIZE     1
 403 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 404 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 405 #define CONFIG_NS16550_MIN_FUNCTIONS
 406 #endif
 407
 408 #define CONFIG_SYS_BAUDRATE_TABLE       \
 409         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 410
 411 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 412 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 413
 414 /* Use the HUSH parser */
 415 #define CONFIG_SYS_HUSH_PARSER
 416
 417 /* Video */
 418
 419 #ifdef CONFIG_FSL_DIU_FB
 420 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 421 #define CONFIG_VIDEO
 422 #define CONFIG_CMD_BMP
 423 #define CONFIG_CFB_CONSOLE
 424 #define CONFIG_VIDEO_SW_CURSOR
 425 #define CONFIG_VGA_AS_SINGLE_DEVICE
 426 #define CONFIG_VIDEO_LOGO
 427 #define CONFIG_VIDEO_BMP_LOGO
 428 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 429 /*
 430  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 431  * disable empty flash sector detection, which is I/O-intensive.
 432  */
 433 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 434 #endif
 435
 436 #ifndef CONFIG_FSL_DIU_FB
 437 #endif
 438
 439 #ifdef CONFIG_ATI
 440 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
 441 #define CONFIG_VIDEO
 442 #define CONFIG_BIOSEMU
 443 #define CONFIG_VIDEO_SW_CURSOR
 444 #define CONFIG_ATI_RADEON_FB
 445 #define CONFIG_VIDEO_LOGO
 446 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 447 #define CONFIG_CFB_CONSOLE
 448 #define CONFIG_VGA_AS_SINGLE_DEVICE
 449 #endif
 450
 451 /*
 452  * Pass open firmware flat tree
 453  */
 454 #define CONFIG_OF_LIBFDT
 455 #define CONFIG_OF_BOARD_SETUP
 456 #define CONFIG_OF_STDOUT_VIA_ALIAS
 457
 458 /* new uImage format support */
 459 #define CONFIG_FIT
 460 #define CONFIG_FIT_VERBOSE
 461
 462 /* I2C */
 463 #define CONFIG_SYS_I2C
 464 #define CONFIG_SYS_I2C_FSL
 465 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 466 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 467 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 468 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 469 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 470 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 471 #define CONFIG_SYS_I2C_NOPROBES         {{0, 0x29}}
 472
 473 /*
 474  * I2C2 EEPROM
 475  */
 476 #define CONFIG_ID_EEPROM
 477 #define CONFIG_SYS_I2C_EEPROM_NXID
 478 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 479 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 480 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 481
 482 /*
 483  * eSPI - Enhanced SPI
 484  */
 485 #define CONFIG_SPI_FLASH
 486 #define CONFIG_SPI_FLASH_SPANSION
 487
 488 #define CONFIG_HARD_SPI
 489 #define CONFIG_FSL_ESPI
 490
 491 #define CONFIG_CMD_SF
 492 #define CONFIG_SF_DEFAULT_SPEED         10000000
 493 #define CONFIG_SF_DEFAULT_MODE          0
 494
 495 /*
 496  * General PCI
 497  * Memory space is mapped 1-1, but I/O space must start from 0.
 498  */
 499
 500 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 501 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 502 #ifdef CONFIG_PHYS_64BIT
 503 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 504 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 505 #else
 506 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 507 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 508 #endif
 509 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 510 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 511 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 512 #ifdef CONFIG_PHYS_64BIT
 513 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 514 #else
 515 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 516 #endif
 517 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 518
 519 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 520 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 521 #ifdef CONFIG_PHYS_64BIT
 522 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 523 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 524 #else
 525 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 526 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 527 #endif
 528 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 529 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 530 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 533 #else
 534 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 535 #endif
 536 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 537
 538 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 539 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 540 #ifdef CONFIG_PHYS_64BIT
 541 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 542 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
 543 #else
 544 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 545 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 546 #endif
 547 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 548 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 549 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 550 #ifdef CONFIG_PHYS_64BIT
 551 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
 552 #else
 553 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 554 #endif
 555 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 556
 557 #ifdef CONFIG_PCI
 558 #define CONFIG_PCI_INDIRECT_BRIDGE
 559 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 560 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 561 #define CONFIG_E1000                    /* Define e1000 pci Ethernet card */
 562 #endif
 563
 564 /* SATA */
 565 #define CONFIG_LIBATA
 566 #define CONFIG_FSL_SATA
 567 #define CONFIG_FSL_SATA_V2
 568
 569 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 570 #define CONFIG_SATA1
 571 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 572 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 573 #define CONFIG_SATA2
 574 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 575 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 576
 577 #ifdef CONFIG_FSL_SATA
 578 #define CONFIG_LBA48
 579 #define CONFIG_CMD_SATA
 580 #define CONFIG_DOS_PARTITION
 581 #define CONFIG_CMD_EXT2
 582 #endif
 583
 584 #define CONFIG_MMC
 585 #ifdef CONFIG_MMC
 586 #define CONFIG_CMD_MMC
 587 #define CONFIG_FSL_ESDHC
 588 #define CONFIG_GENERIC_MMC
 589 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 590 #endif
 591
 592 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 593 #define CONFIG_CMD_EXT2
 594 #define CONFIG_CMD_FAT
 595 #define CONFIG_DOS_PARTITION
 596 #endif
 597
 598 #define CONFIG_TSEC_ENET
 599 #ifdef CONFIG_TSEC_ENET
 600
 601 #define CONFIG_TSECV2
 602
 603 #define CONFIG_MII                      /* MII PHY management */
 604 #define CONFIG_TSEC1            1
 605 #define CONFIG_TSEC1_NAME       "eTSEC1"
 606 #define CONFIG_TSEC2            1
 607 #define CONFIG_TSEC2_NAME       "eTSEC2"
 608
 609 #define TSEC1_PHY_ADDR          1
 610 #define TSEC2_PHY_ADDR          2
 611
 612 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 613 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 614
 615 #define TSEC1_PHYIDX            0
 616 #define TSEC2_PHYIDX            0
 617
 618 #define CONFIG_ETHPRIME         "eTSEC1"
 619
 620 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 621 #endif
 622
 623 /*
 624  * Environment
 625  */
 626 #ifdef CONFIG_SPIFLASH
 627 #define CONFIG_ENV_IS_IN_SPI_FLASH
 628 #define CONFIG_ENV_SPI_BUS      0
 629 #define CONFIG_ENV_SPI_CS       0
 630 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 631 #define CONFIG_ENV_SPI_MODE     0
 632 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 633 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 634 #define CONFIG_ENV_SECT_SIZE    0x10000
 635 #elif defined(CONFIG_SDCARD)
 636 #define CONFIG_ENV_IS_IN_MMC
 637 #define CONFIG_FSL_FIXED_MMC_LOCATION
 638 #define CONFIG_ENV_SIZE         0x2000
 639 #define CONFIG_SYS_MMC_ENV_DEV  0
 640 #elif defined(CONFIG_NAND)
 641 #ifdef CONFIG_TPL_BUILD
 642 #define CONFIG_ENV_SIZE         0x2000
 643 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 644 #else
 645 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 646 #endif
 647 #define CONFIG_ENV_IS_IN_NAND
 648 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 649 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 650 #elif defined(CONFIG_SYS_RAMBOOT)
 651 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 652 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 653 #define CONFIG_ENV_SIZE         0x2000
 654 #else
 655 #define CONFIG_ENV_IS_IN_FLASH
 656 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 657 #define CONFIG_ENV_ADDR 0xfff80000
 658 #else
 659 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 660 #endif
 661 #define CONFIG_ENV_SIZE         0x2000
 662 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 663 #endif
 664
 665 #define CONFIG_LOADS_ECHO
 666 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 667
 668 /*
 669  * Command line configuration.
 670  */
 671 #include <config_cmd_default.h>
 672
 673 #define CONFIG_CMD_ELF
 674 #define CONFIG_CMD_ERRATA
 675 #define CONFIG_CMD_IRQ
 676 #define CONFIG_CMD_I2C
 677 #define CONFIG_CMD_MII
 678 #define CONFIG_CMD_PING
 679 #define CONFIG_CMD_SETEXPR
 680 #define CONFIG_CMD_REGINFO
 681
 682 #ifdef CONFIG_PCI
 683 #define CONFIG_CMD_PCI
 684 #define CONFIG_CMD_NET
 685 #endif
 686
 687 /*
 688  * USB
 689  */
 690 #define CONFIG_HAS_FSL_DR_USB
 691 #ifdef CONFIG_HAS_FSL_DR_USB
 692 #define CONFIG_USB_EHCI
 693
 694 #ifdef CONFIG_USB_EHCI
 695 #define CONFIG_CMD_USB
 696 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 697 #define CONFIG_USB_EHCI_FSL
 698 #define CONFIG_USB_STORAGE
 699 #define CONFIG_CMD_FAT
 700 #endif
 701 #endif
 702
 703 /*
 704  * Miscellaneous configurable options
 705  */
 706 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 707 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 708 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 709 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 710 #ifdef CONFIG_CMD_KGDB
 711 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 712 #else
 713 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 714 #endif
 715 /* Print Buffer Size */
 716 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 717 #define CONFIG_SYS_MAXARGS      16
 718 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 719
 720 /*
 721  * For booting Linux, the board info and command line data
 722  * have to be in the first 64 MB of memory, since this is
 723  * the maximum mapped by the Linux kernel during initialization.
 724  */
 725 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 726 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 727
 728 #ifdef CONFIG_CMD_KGDB
 729 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 730 #endif
 731
 732 /*
 733  * Environment Configuration
 734  */
 735
 736 #define CONFIG_HOSTNAME         p1022ds
 737 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 738 #define CONFIG_BOOTFILE         "uImage"
 739 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 740
 741 #define CONFIG_LOADADDR         1000000
 742
 743 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 744
 745 #define CONFIG_BAUDRATE 115200
 746
 747 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 748         "netdev=eth0\0"                                         \
 749         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 750         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 751         "tftpflash=tftpboot $loadaddr $uboot && "               \
 752                 "protect off $ubootaddr +$filesize && "         \
 753                 "erase $ubootaddr +$filesize && "               \
 754                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 755                 "protect on $ubootaddr +$filesize && "          \
 756                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 757         "consoledev=ttyS0\0"                                    \
 758         "ramdiskaddr=2000000\0"                                 \
 759         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 760         "fdtaddr=c00000\0"                                      \
 761         "fdtfile=p1022ds.dtb\0"                                 \
 762         "bdev=sda3\0"                                           \
 763         "hwconfig=esdhc;audclk:12\0"
 764
 765 #define CONFIG_HDBOOT                                   \
 766         "setenv bootargs root=/dev/$bdev rw "           \
 767         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 768         "tftp $loadaddr $bootfile;"                     \
 769         "tftp $fdtaddr $fdtfile;"                       \
 770         "bootm $loadaddr - $fdtaddr"
 771
 772 #define CONFIG_NFSBOOTCOMMAND                                           \
 773         "setenv bootargs root=/dev/nfs rw "                             \
 774         "nfsroot=$serverip:$rootpath "                                  \
 775         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 776         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 777         "tftp $loadaddr $bootfile;"                                     \
 778         "tftp $fdtaddr $fdtfile;"                                       \
 779         "bootm $loadaddr - $fdtaddr"
 780
 781 #define CONFIG_RAMBOOTCOMMAND                                           \
 782         "setenv bootargs root=/dev/ram rw "                             \
 783         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 784         "tftp $ramdiskaddr $ramdiskfile;"                               \
 785         "tftp $loadaddr $bootfile;"                                     \
 786         "tftp $fdtaddr $fdtfile;"                                       \
 787         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 788
 789 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 790
 791 #endif