include/configs/P1023RDS.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <b25806@freescale.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * p1023rds board configuration file
  28  *
  29  */
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #ifdef CONFIG_NAND
  34 #define CONFIG_NAND_U_BOOT
  35 #define CONFIG_RAMBOOT_NAND
  36 #endif
  37
  38 #ifdef CONFIG_NAND_U_BOOT
  39 #define CONFIG_SYS_TEXT_BASE_SPL        0xfff00000
  40 #define CONFIG_SYS_TEXT_BASE            0x11001000
  41
  42 #ifdef CONFIG_NAND_SPL
  43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  44 #else
  45 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  46 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  47 #endif /* CONFIG_NAND_SPL */
  48 #endif
  49
  50 #ifndef CONFIG_SYS_TEXT_BASE
  51 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  52 #endif
  53
  54 #ifndef CONFIG_SYS_MONITOR_BASE
  55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 /* High Level Configuration Options */
  63 #define CONFIG_BOOKE            /* BOOKE */
  64 #define CONFIG_E500             /* BOOKE e500 family */
  65 #define CONFIG_MPC85xx
  66 #define CONFIG_P1023
  67 #define CONFIG_P1023RDS
  68 #define CONFIG_MP               /* support multiple processors */
  69
  70 #define CONFIG_FSL_ELBC         /* Has Enhanced localbus controller */
  71 #define CONFIG_PCI              /* Enable PCI/PCIE */
  72 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  73 #define CONFIG_PCIE2            /* PCIE controler 2 (slot 2) */
  74 #define CONFIG_PCIE3            /* PCIE controler 3 (slot 3) */
  75 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  76 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  77 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  78 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  79
  80 #ifndef __ASSEMBLY__
  81 extern unsigned long get_clock_freq(void);
  82 #endif
  83
  84 #define CONFIG_SYS_CLK_FREQ     66666666
  85 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  86
  87 /*
  88  * These can be toggled for performance analysis, otherwise use default.
  89  */
  90 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  91 #define CONFIG_BTB                      /* toggle branch predition */
  92 #define CONFIG_HWCONFIG
  93
  94 #define CONFIG_ENABLE_36BIT_PHYS
  95
  96 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  97 #define CONFIG_SYS_MEMTEST_END          0x1fffffff      /* fix me, only 1G */
  98 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  99
 100 #define CONFIG_SYS_LBC_LBCR     0x00000000      /* Implement conversion of
 101                                                 addresses in the LBC */
 102 /*
 103  * Base addresses -- Note these are effective addresses where the
 104  * actual resources get mapped (not physical addresses)
 105  */
 106 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff600000      /* CCSRBAR Default */
 107 #define CONFIG_SYS_CCSRBAR              0xff600000      /* relocated CCSRBAR */
 108 /* physical addr of CCSRBAR */
 109 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
 110 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 111
 112 /* DDR Setup */
 113 #define CONFIG_VERY_BIG_RAM
 114
 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 116 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 117
 118 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 119 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 120
 121 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 122 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 123
 124 /* These are used when DDR doesn't use SPD.  */
 125 #define CONFIG_SYS_SDRAM_SIZE           2048u   /* DDR is 2GB */
 126
 127 /* Default settings for "stable" mode */
 128 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 129 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007F
 130 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 131 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 132 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 133 #define CONFIG_SYS_DDR_TIMING_0         0x40110104
 134 #define CONFIG_SYS_DDR_TIMING_1         0x5C59E544
 135 #define CONFIG_SYS_DDR_TIMING_2         0x0fA888CA
 136 #define CONFIG_SYS_DDR_MODE_1           0x00441210
 137 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 138 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
 139 #define CONFIG_SYS_DDR_INTERVAL         0x0A280100
 140 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 141 #define CONFIG_SYS_DDR_CLK_CTRL         0x01800000
 142 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 143 #define CONFIG_SYS_DDR_TIMING_5         0x01401400
 144 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
 145 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8675F605
 146 #define CONFIG_SYS_DDR_CONTROL  0xC70C0008 /* Type = DDR3: No Interleaving */
 147 #define CONFIG_SYS_DDR_CONTROL2         0x24401010
 148 #define CONFIG_SYS_DDR_CDR1             0x00000000
 149 #define CONFIG_SYS_DDR_CDR2             0x00000000
 150
 151 #define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 152 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 153 #define CONFIG_SYS_DDR_SBE              0x00000000
 154
 155 /* Settings that differ for "performance" mode */
 156 #define CONFIG_SYS_DDR_CS0_BNDS_PERF    0x0000007F /* Interleaving Enabled */
 157 #define CONFIG_SYS_DDR_CS1_BNDS_PERF    0x00000000 /* Interleaving Enabled */
 158 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014302
 159 #define CONFIG_SYS_DDR_TIMING_1_PERF    0x5C58E544
 160 #define CONFIG_SYS_DDR_TIMING_2_PERF    0x0FA888CA
 161 /* Type = DDR3: cs0-cs1 interleaving */
 162 #define CONFIG_SYS_DDR_CONTROL_PERF     0xC70C4008
 163 #define CONFIG_SYS_DDR_CDR_1            0x00000000
 164 #define CONFIG_SYS_DDR_CDR_2            0x00000000
 165
 166
 167 /*
 168  * Memory map
 169  *
 170  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 171  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 172  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 173  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 174  *
 175  * Localbus non-cacheable
 176  * 0xe000_0000  0xe003_ffff     BCSR                    256K BCSR
 177  * 0xee00_0000  0xefff_ffff     NOR flash               32M NOR flash
 178  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M
 179  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
 180  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 181  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 182  */
 183
 184 /*
 185  * Local Bus Definitions
 186  */
 187 #define CONFIG_SYS_BCSR_BASE            0xe0000000 /* start of on board FPGA */
 188 #define CONFIG_SYS_BCSR_BASE_PHYS       CONFIG_SYS_BCSR_BASE
 189
 190 #ifndef CONFIG_NAND
 191 #define CONFIG_SYS_FLASH_BASE           0xee000000 /* start of FLASH 32M */
 192
 193 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 194
 195 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 196                 | BR_PS_16 | BR_V)
 197 #define CONFIG_FLASH_OR_PRELIM  0xfe000ff7
 198
 199 #define CONFIG_FLASH_CFI_DRIVER
 200 #define CONFIG_SYS_FLASH_CFI
 201 #define CONFIG_SYS_FLASH_EMPTY_INFO
 202
 203 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 204 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 205 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 206 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 207 #else
 208 #define CONFIG_SYS_NO_FLASH
 209 #endif
 210
 211 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
 212 #define CONFIG_SYS_RAMBOOT
 213 #endif
 214
 215 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f function */
 216 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 217
 218 #define CONFIG_SYS_INIT_RAM_LOCK
 219 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 220 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 221
 222 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 223 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 224         (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 225 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 226
 227 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 228 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 229
 230 #ifndef CONFIG_NAND_SPL
 231 #define CONFIG_SYS_NAND_BASE            0xffa00000
 232 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 233 #else
 234 #define CONFIG_SYS_NAND_BASE            0xfff00000
 235 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 236 #endif
 237
 238 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 239 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 240 #define CONFIG_MTD_NAND_VERIFY_WRITE
 241 #define CONFIG_CMD_NAND
 242 #define CONFIG_NAND_FSL_ELBC
 243 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 244
 245 /* NAND boot: 4K NAND loader config */
 246 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 247 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
 248 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
 249 #define CONFIG_SYS_NAND_U_BOOT_START    0x11000000
 250 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 251 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
 252 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 253
 254 /* NAND flash config */
 255 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 256                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 257                                 | BR_PS_8               /* Port Size = 8bit */ \
 258                                 | BR_MS_FCM             /* MSEL = FCM */ \
 259                                 | BR_V)                 /* valid */
 260 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFF80000          /* length 32K */ \
 261                                 | OR_FCM_CSCT \
 262                                 | OR_FCM_CST \
 263                                 | OR_FCM_CHT \
 264                                 | OR_FCM_SCY_1 \
 265                                 | OR_FCM_TRLX \
 266                                 | OR_FCM_EHTR)
 267
 268 #ifdef CONFIG_RAMBOOT_NAND
 269 /* NAND Base Address */
 270 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 271 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 272 /* chip select 1 - BCSR */
 273 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
 274                                 | BR_MS_GPCM | BR_PS_8 | BR_V)
 275 #define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
 276                                 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
 277                                 | OR_GPCM_EAD)
 278 #else
 279 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 280 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 281 /* chip select 1 - BCSR */
 282 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
 283                                 | BR_MS_GPCM | BR_PS_8 | BR_V)
 284 #define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
 285                                 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
 286                                 | OR_GPCM_EAD)
 287 #endif
 288
 289 /* Serial Port
 290  * open - index 2
 291  * shorted - index 1
 292  */
 293 #define CONFIG_CONS_INDEX               1
 294 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 295 #define CONFIG_SYS_NS16550
 296 #define CONFIG_SYS_NS16550_SERIAL
 297 #define CONFIG_SYS_NS16550_REG_SIZE     1
 298 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 299 #ifdef CONFIG_NAND_SPL
 300 #define CONFIG_NS16550_MIN_FUNCTIONS
 301 #endif
 302
 303 #define CONFIG_SYS_BAUDRATE_TABLE       \
 304         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 305
 306 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 307 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 308
 309 /* Use the HUSH parser */
 310 #define CONFIG_SYS_HUSH_PARSER
 311 #ifdef  CONFIG_SYS_HUSH_PARSER
 312 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 313 #endif
 314
 315 /*
 316  * Pass open firmware flat tree
 317  */
 318 #define CONFIG_OF_LIBFDT
 319 #define CONFIG_OF_BOARD_SETUP
 320 #define CONFIG_OF_STDOUT_VIA_ALIAS
 321
 322 #define CONFIG_SYS_64BIT_VSPRINTF
 323 #define CONFIG_SYS_64BIT_STRTOUL
 324
 325 /* new uImage format support */
 326 #define CONFIG_FIT
 327 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 328
 329 /* I2C */
 330 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 331 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 332 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 333 #define CONFIG_I2C_MULTI_BUS
 334 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 335 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x51
 336 #define CONFIG_SYS_I2C_SLAVE            0x7F
 337 #define CONFIG_SYS_I2C_OFFSET           0x3000
 338 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 339
 340 /*
 341  * I2C2 EEPROM
 342  */
 343 #define CONFIG_ID_EEPROM
 344 #ifdef CONFIG_ID_EEPROM
 345 #define CONFIG_SYS_I2C_EEPROM_NXID
 346 #endif
 347 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x51
 348 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 349 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 350
 351 #define CONFIG_CMD_I2C
 352
 353 /*
 354  * eSPI - Enhanced SPI
 355  */
 356 #define CONFIG_SPI_FLASH
 357 #define CONFIG_SPI_FLASH_ATMEL
 358
 359 #define CONFIG_HARD_SPI
 360 #define CONFIG_FSL_ESPI
 361
 362 #define CONFIG_CMD_SF
 363 #define CONFIG_SF_DEFAULT_SPEED         10000000
 364 #define CONFIG_SF_DEFAULT_MODE          0
 365
 366 /*
 367  * General PCI
 368  * Memory space is mapped 1-1, but I/O space must start from 0.
 369  */
 370
 371 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 372 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 373 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 374 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 375 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 376 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 377 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 378 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 379 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 380 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 381
 382 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 383 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 384 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 385 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 386 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 387 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 388 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 389 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 390 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 391 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 392
 393 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 394 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 395 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 396 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 397 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 398 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 399 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 400 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 401 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 402 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 403
 404 #if defined(CONFIG_PCI)
 405 #define CONFIG_E1000            /* Defind e1000 pci Ethernet card */
 406 #define CONFIG_NET_MULTI
 407 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 408 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 409 #endif  /* CONFIG_PCI */
 410
 411 #ifndef CONFIG_NET_MULTI
 412 #define CONFIG_NET_MULTI
 413 #endif
 414
 415 /*
 416  * Environment
 417  */
 418 #define CONFIG_ENV_OVERWRITE
 419
 420 #if defined(CONFIG_SYS_RAMBOOT)
 421 #if defined(CONFIG_RAMBOOT_NAND)
 422 #define CONFIG_ENV_IS_IN_NAND
 423 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 424 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 425 #else
 426 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 427 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x4000)
 428 #define CONFIG_ENV_SIZE         0x2000
 429 #endif
 430 #else
 431 #define CONFIG_ENV_IS_IN_FLASH
 432 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 433 #define CONFIG_ENV_ADDR         0xfff80000
 434 #else
 435 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 436 #endif
 437 #define CONFIG_ENV_SIZE         0x2000
 438 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 439 #endif
 440
 441 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 442 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 443
 444 /*
 445  * Command line configuration.
 446  */
 447 #include <config_cmd_default.h>
 448
 449 #define CONFIG_CMD_IRQ
 450 #define CONFIG_CMD_PING
 451 #define CONFIG_CMD_MII
 452 #define CONFIG_CMD_ELF
 453 #define CONFIG_CMD_SETEXPR
 454 #define CONFIG_CMD_REGINFO
 455
 456 #if defined(CONFIG_PCI)
 457 #define CONFIG_CMD_PCI
 458 #define CONFIG_CMD_NET
 459 #endif
 460
 461 /*
 462  * USB
 463  */
 464 #define CONFIG_USB_EHCI
 465
 466 #ifdef CONFIG_USB_EHCI
 467 #define CONFIG_CMD_USB
 468 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 469 #define CONFIG_USB_EHCI_FSL
 470 #define CONFIG_USB_STORAGE
 471 #define CONFIG_CMD_FAT
 472 #define CONFIG_CMD_EXT2
 473 #define CONFIG_CMD_FAT
 474 #define CONFIG_DOS_PARTITION
 475 #endif
 476
 477 /*
 478  * Miscellaneous configurable options
 479  */
 480 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 481 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 482 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 483 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 484 #if defined(CONFIG_CMD_KGDB)
 485 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 486 #else
 487 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 488 #endif
 489 /* Print Buffer Size */
 490 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 491 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 492 /* Boot Argument Buffer Size */
 493 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 494 #define CONFIG_SYS_HZ   1000            /* decrementer freq: 1ms ticks */
 495
 496 /*
 497  * For booting Linux, the board info and command line data
 498  * have to be in the first 16 MB of memory, since this is
 499  * the maximum mapped by the Linux kernel during initialization.
 500  */
 501 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20) /* Initial Memory map for Linux*/
 502 #define CONFIG_SYS_BOOTM_LEN    (16 << 20) /* Increase max gunzip size */
 503
 504 #if defined(CONFIG_CMD_KGDB)
 505 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 506 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 507 #endif
 508
 509 /*
 510  * Environment Configuration
 511  */
 512 #define CONFIG_BOOTFILE         uImage
 513 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 514
 515 /* default location for tftp and bootm */
 516 #define CONFIG_LOADADDR         1000000
 517
 518 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 519
 520 #define CONFIG_BAUDRATE 115200
 521
 522 /* Qman/Bman */
 523 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
 524 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 525 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 526 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 527 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 528 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 529 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 530
 531 /* For FM */
 532 #define CONFIG_SYS_DPAA_FMAN
 533 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 534
 535 #ifdef CONFIG_SYS_DPAA_FMAN
 536 #define CONFIG_FMAN_ENET
 537 #endif
 538
 539 #define CONFIG_SYS_FMAN_FW
 540 #ifndef CONFIG_NAND
 541 /* Default address of microcode for the Linux Fman driver */
 542 /* QE microcode/firmware address */
 543 #define CONFIG_SYS_FMAN_FW_ADDR         0xEF000000
 544 #else
 545 #define CONFIG_SYS_QE_FW_IN_NAND        0x1f00000
 546 #endif
 547 #define CONFIG_SYS_FMAN_FW_LENGTH       0x10000
 548 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
 549
 550 #ifdef CONFIG_FMAN_ENET
 551 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 552 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x7
 553
 554 #define CONFIG_SYS_TBIPA_VALUE  8
 555 #define CONFIG_MII              /* MII PHY management */
 556 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 557 #endif
 558
 559 #define CONFIG_EXTRA_ENV_SETTINGS       \
 560         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 561
 562 #endif  /* __CONFIG_H */