include/configs/P1_P2_RDB.h

   1 /*
   2  * Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P1 P2 RDB board configuration file
  25  * This file is intended to address a set of Low End and Ultra Low End
  26  * Freescale SOCs of QorIQ series(RDB platforms).
  27  * Currently only P2020RDB
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #ifdef CONFIG_MK_P1011RDB
  34 #define CONFIG_P1011
  35 #endif
  36 #ifdef CONFIG_MK_P1020RDB
  37 #define CONFIG_P1020
  38 #endif
  39 #ifdef CONFIG_MK_P2010RDB
  40 #define CONFIG_P2010
  41 #endif
  42 #ifdef CONFIG_MK_P2020RDB
  43 #define CONFIG_P2020
  44 #endif
  45
  46 /* High Level Configuration Options */
  47 #define CONFIG_BOOKE            1       /* BOOKE */
  48 #define CONFIG_E500             1       /* BOOKE e500 family */
  49 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  50 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  51 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  52 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  53 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  54 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  55 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  56 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  57 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  58 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  59 #define CONFIG_ENV_OVERWRITE
  60
  61 #ifndef __ASSEMBLY__
  62 extern unsigned long get_board_sys_clk(unsigned long dummy);
  63 #endif
  64 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on P1_P2 RDB */
  65 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
  66
  67 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
  68 #define CONFIG_MP
  69 #endif
  70
  71 /*
  72  * These can be toggled for performance analysis, otherwise use default.
  73  */
  74 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  75 #define CONFIG_BTB                      /* toggle branch predition */
  76
  77 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  78
  79 #define CONFIG_ENABLE_36BIT_PHYS        1
  80
  81 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
  82 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
  83 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  84
  85 /*
  86  * Base addresses -- Note these are effective addresses where the
  87  * actual resources get mapped (not physical addresses)
  88  */
  89 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  90 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  91 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of */
  92                                                         /* CCSRBAR */
  93 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
  94                                                         /* CONFIG_SYS_IMMR */
  95 #define CONFIG_SYS_PCIE2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
  96 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR+0xa000)
  97
  98 /* DDR Setup */
  99 #define CONFIG_FSL_DDR2
 100 #undef CONFIG_FSL_DDR_INTERACTIVE
 101 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 102 #undef CONFIG_DDR_DLL
 103
 104 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 105
 106 #define CONFIG_SYS_SDRAM_SIZE   1024    /* DDR size on P1_P2 RDBs */
 107 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 109
 110 #define CONFIG_NUM_DDR_CONTROLLERS      1
 111 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 112 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 113
 114 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 115 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 116 #define CONFIG_SYS_DDR_SBE              0x00FF0000
 117
 118 #define CONFIG_SYS_DDR_TLB_START 9
 119
 120 /*
 121  * Memory map
 122  *
 123  * 0x0000_0000  0x3fff_ffff     DDR                     1G cacheablen
 124  * 0xa000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 125  * 0xffc2_0000  0xffc5_ffff     PCI IO range            256K non-cacheable
 126  *
 127  * Localbus cacheable (TBD)
 128  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 129  *
 130  * Localbus non-cacheable
 131  * 0xef00_0000  0xefff_ffff     FLASH                   16M non-cacheable
 132  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 133  * 0xffb0_0000  0xffbf_ffff     VSC7385 switch          1M non-cacheable
 134  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 135  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 136  */
 137
 138 /*
 139  * Local Bus Definitions
 140  */
 141 #define CONFIG_SYS_FLASH_BASE           0xef000000      /* start of FLASH 16M */
 142
 143 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 144
 145 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 146                                         BR_PS_16 | BR_V)
 147 #define CONFIG_FLASH_OR_PRELIM          0xff000ff7
 148
 149 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 150 #define CONFIG_SYS_FLASH_QUIET_TEST
 151 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 155 #undef  CONFIG_SYS_FLASH_CHECKSUM
 156 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 157 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 158
 159 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 160
 161 #define CONFIG_FLASH_CFI_DRIVER
 162 #define CONFIG_SYS_FLASH_CFI
 163 #define CONFIG_SYS_FLASH_EMPTY_INFO
 164 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 165
 166 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 167
 168 #define CONFIG_SYS_INIT_RAM_LOCK        1
 169 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000        /* stack in RAM */
 170 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 171
 172 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 173 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END \
 174                                                 - CONFIG_SYS_GBL_DATA_SIZE)
 175 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 176
 177 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 178 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 179
 180 #define CONFIG_SYS_NAND_BASE            0xffa00000
 181 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 182 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE}
 183 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 184 #define NAND_MAX_CHIPS                  1
 185 #define CONFIG_MTD_NAND_VERIFY_WRITE
 186 #define CONFIG_CMD_NAND                 1
 187 #define CONFIG_NAND_FSL_ELBC            1
 188 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 189
 190 /* NAND flash config */
 191 #define CONFIG_NAND_BR_PRELIM   (CONFIG_SYS_NAND_BASE_PHYS \
 192                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 193                                 | BR_PS_8       /* Port Size = 8 bit */ \
 194                                 | BR_MS_FCM             /* MSEL = FCM */ \
 195                                 | BR_V)                 /* valid */
 196
 197 #define CONFIG_NAND_OR_PRELIM   (0xFFF80000             /* length 32K */ \
 198                                 | OR_FCM_CSCT \
 199                                 | OR_FCM_CST \
 200                                 | OR_FCM_CHT \
 201                                 | OR_FCM_SCY_1 \
 202                                 | OR_FCM_TRLX \
 203                                 | OR_FCM_EHTR)
 204
 205 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 206 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 207 #define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 208 #define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 209
 210 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 211
 212 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 213
 214 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
 215 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 216                                 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 217                                 OR_GPCM_EHTR | OR_GPCM_EAD)
 218
 219 /* Serial Port - controlled on board with jumper J8
 220  * open - index 2
 221  * shorted - index 1
 222  */
 223 #define CONFIG_CONS_INDEX       1
 224 //#define CONFIG_CONS_INDEX     2
 225 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 226 #define CONFIG_SYS_NS16550
 227 #define CONFIG_SYS_NS16550_SERIAL
 228 #define CONFIG_SYS_NS16550_REG_SIZE     1
 229 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 230
 231 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 232 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 233
 234 #define CONFIG_SYS_BAUDRATE_TABLE       \
 235         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 236
 237 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 238 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 239
 240 /* Use the HUSH parser */
 241 #define CONFIG_SYS_HUSH_PARSER
 242 #ifdef  CONFIG_SYS_HUSH_PARSER
 243 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 244 #endif
 245
 246 /*
 247  * Pass open firmware flat tree
 248  */
 249 #define CONFIG_OF_LIBFDT                1
 250 #define CONFIG_OF_BOARD_SETUP           1
 251 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 252
 253 #define CONFIG_SYS_64BIT_VSPRINTF       1
 254 #define CONFIG_SYS_64BIT_STRTOUL        1
 255
 256 /* new uImage format support */
 257 #define CONFIG_FIT              1
 258 #define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
 259
 260 /* I2C */
 261 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 262 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 263 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 264 #define CONFIG_I2C_MULTI_BUS
 265 #define CONFIG_I2C_CMD_TREE
 266 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address*/
 267 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 268 #define CONFIG_SYS_I2C_SLAVE            0x7F
 269 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}      /* Don't probe these addrs */
 270 #define CONFIG_SYS_I2C_OFFSET           0x3000
 271 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 272
 273 /*
 274  * I2C2 EEPROM
 275  */
 276 #define CONFIG_ID_EEPROM
 277 #ifdef CONFIG_ID_EEPROM
 278 #define CONFIG_SYS_I2C_EEPROM_NXID
 279 #endif
 280 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 281 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 282 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 283
 284 #define CONFIG_RTC_DS1337
 285 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 286 /*
 287  * General PCI
 288  * Memory space is mapped 1-1, but I/O space must start from 0.
 289  */
 290
 291 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 292 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 293 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 294 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 295 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 296 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 297 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 298 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 299 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 300
 301 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 302 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 303 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 304 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 305 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 306 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc30000
 307 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 308 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc30000
 309 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 310
 311 #if defined(CONFIG_PCI)
 312 #define CONFIG_NET_MULTI
 313 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 314
 315 #undef CONFIG_EEPRO100
 316 #undef CONFIG_TULIP
 317 #undef CONFIG_RTL8139
 318
 319 #ifdef CONFIG_RTL8139
 320 /* This macro is used by RTL8139 but not defined in PPC architecture */
 321 #define KSEG1ADDR(x)            (x)
 322 #define _IO_BASE        0x00000000
 323 #endif
 324
 325
 326 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 327 #define CONFIG_DOS_PARTITION
 328
 329 #endif  /* CONFIG_PCI */
 330
 331 #if defined(CONFIG_TSEC_ENET)
 332 #ifndef CONFIG_NET_MULTI
 333 #define CONFIG_NET_MULTI        1
 334 #endif
 335
 336 #define CONFIG_MII              1       /* MII PHY management */
 337 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 338 #define CONFIG_TSEC1    1
 339 #define CONFIG_TSEC1_NAME       "eTSEC1"
 340 #define CONFIG_TSEC2    1
 341 #define CONFIG_TSEC2_NAME       "eTSEC2"
 342 #define CONFIG_TSEC3    1
 343 #define CONFIG_TSEC3_NAME       "eTSEC3"
 344
 345 #define TSEC1_PHY_ADDR          2
 346 #define TSEC2_PHY_ADDR          0
 347 #define TSEC3_PHY_ADDR          1
 348
 349 #define CONFIG_VSC7385_ENET
 350
 351 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 352 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 353 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 354
 355 #define TSEC1_PHYIDX            0
 356 #define TSEC2_PHYIDX            0
 357 #define TSEC3_PHYIDX            0
 358
 359 /* Vitesse 7385 */
 360
 361 #ifdef CONFIG_VSC7385_ENET
 362 /* The size of the VSC7385 firmware image */
 363 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 364 #endif
 365
 366 #define CONFIG_ETHPRIME         "eTSEC1"
 367
 368 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 369 #endif  /* CONFIG_TSEC_ENET */
 370
 371 /*
 372  * Environment
 373  */
 374 #define CONFIG_ENV_IS_IN_FLASH  1
 375 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 376 #define CONFIG_ENV_ADDR         0xfff80000
 377 #else
 378 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 379 #endif
 380 #define CONFIG_ENV_SIZE         0x2000
 381 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 382
 383 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 385
 386 /*
 387  * Command line configuration.
 388  */
 389 #include <config_cmd_default.h>
 390
 391 #define CONFIG_CMD_DATE
 392 #define CONFIG_CMD_ELF
 393 #define CONFIG_CMD_I2C
 394 #define CONFIG_CMD_IRQ
 395 #define CONFIG_CMD_MII
 396 #define CONFIG_CMD_PING
 397 #define CONFIG_CMD_SETEXPR
 398
 399 #if defined(CONFIG_PCI)
 400 #define CONFIG_CMD_NET
 401 #define CONFIG_CMD_PCI
 402 #endif
 403
 404 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 405
 406 #define CONFIG_MMC      1
 407
 408 #ifdef CONFIG_MMC
 409 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 410 #define CONFIG_CMD_MMC
 411 #define CONFIG_DOS_PARTITION
 412 #define CONFIG_FSL_ESDHC
 413 #define CONFIG_GENERIC_MMC
 414 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 415 #ifdef CONFIG_P2020
 416 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
 417 #endif
 418 #endif
 419
 420 #define CONFIG_USB_EHCI
 421
 422 #ifdef CONFIG_USB_EHCI
 423 #define CONFIG_CMD_USB
 424 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 425 #define CONFIG_USB_EHCI_FSL
 426 #define CONFIG_USB_STORAGE
 427 #endif
 428
 429 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 430 #define CONFIG_CMD_EXT2
 431 #define CONFIG_CMD_FAT
 432 #define CONFIG_DOS_PARTITION
 433 #endif
 434
 435 /*
 436  * Miscellaneous configurable options
 437  */
 438 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 439 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 440 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 441 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 442 #if defined(CONFIG_CMD_KGDB)
 443 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 444 #else
 445 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 446 #endif
 447 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 448                                                 /* Print Buffer Size */
 449 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 450 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 451 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 452
 453 /*
 454  * For booting Linux, the board info and command line data
 455  * have to be in the first 16 MB of memory, since this is
 456  * the maximum mapped by the Linux kernel during initialization.
 457  */
 458 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)/* Initial Memory map for Linux*/
 459
 460 /*
 461  * Internal Definitions
 462  *
 463  * Boot Flags
 464  */
 465 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 466 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 467
 468 #if defined(CONFIG_CMD_KGDB)
 469 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 470 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 471 #endif
 472
 473 /*
 474  * Environment Configuration
 475  */
 476
 477 #if defined(CONFIG_TSEC_ENET)
 478 #define CONFIG_HAS_ETH0
 479 #define CONFIG_HAS_ETH1
 480 #define CONFIG_HAS_ETH2
 481 #endif
 482
 483 #define CONFIG_HOSTNAME         P2020RDB
 484 #define CONFIG_ROOTPATH         /opt/nfsroot
 485 #define CONFIG_BOOTFILE         uImage
 486 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 487
 488 /* default location for tftp and bootm */
 489 #define CONFIG_LOADADDR         1000000
 490
 491 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 492 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 493
 494 #define CONFIG_BAUDRATE 115200
 495
 496 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 497         "netdev=eth0\0"                                         \
 498         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 499         "loadaddr=1000000\0"                    \
 500         "bootfile=uImage\0"     \
 501         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 502                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 503                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 504                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 505                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 506                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 507         "consoledev=ttyS0\0"                            \
 508         "ramdiskaddr=2000000\0"                 \
 509         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 510         "fdtaddr=c00000\0"                              \
 511         "fdtfile=p2020rdb.dtb\0"                \
 512         "bdev=sda1\0"   \
 513         "jffs2nor=mtdblock3\0"  \
 514         "norbootaddr=ef080000\0"        \
 515         "norfdtaddr=ef040000\0" \
 516         "jffs2nand=mtdblock9\0" \
 517         "nandbootaddr=100000\0" \
 518         "nandfdtaddr=80000\0"           \
 519         "nandimgsize=400000\0"          \
 520         "nandfdtsize=80000\0"           \
 521         "usb_phy_type=ulpi\0"           \
 522         "vscfw_addr=ef000000\0" \
 523         "othbootargs=ramdisk_size=600000\0" \
 524         "usbfatboot=setenv bootargs root=/dev/ram rw "  \
 525         "console=$consoledev,$baudrate $othbootargs; "  \
 526         "usb start;"                    \
 527         "fatload usb 0:2 $loadaddr $bootfile;"          \
 528         "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 529         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 530         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 531         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 532         "console=$consoledev,$baudrate $othbootargs; "  \
 533         "usb start;"                    \
 534         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 535         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 536         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 537         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 538         "norboot=setenv bootargs root=/dev/$jffs2nor rw "       \
 539         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 540         "bootm $norbootaddr - $norfdtaddr\0"            \
 541         "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
 542         "console=$consoledev,$baudrate $othbootargs;"   \
 543         "nand read 2000000 $nandbootaddr $nandimgsize;" \
 544         "nand read 3000000 $nandfdtaddr $nandfdtsize;"  \
 545         "bootm 2000000 - 3000000;\0"
 546
 547 #define CONFIG_NFSBOOTCOMMAND           \
 548         "setenv bootargs root=/dev/nfs rw "     \
 549         "nfsroot=$serverip:$rootpath "          \
 550         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 551         "console=$consoledev,$baudrate $othbootargs;"   \
 552         "tftp $loadaddr $bootfile;"             \
 553         "tftp $fdtaddr $fdtfile;"               \
 554         "bootm $loadaddr - $fdtaddr"
 555
 556 #define CONFIG_HDBOOT                   \
 557         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 558         "console=$consoledev,$baudrate $othbootargs;"   \
 559         "usb start;"                    \
 560         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"           \
 561         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 562         "bootm $loadaddr - $fdtaddr"
 563
 564 #define CONFIG_RAMBOOTCOMMAND           \
 565         "setenv bootargs root=/dev/ram rw "     \
 566         "console=$consoledev,$baudrate $othbootargs; "  \
 567         "tftp $ramdiskaddr $ramdiskfile;"       \
 568         "tftp $loadaddr $bootfile;"             \
 569         "tftp $fdtaddr $fdtfile;"               \
 570         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 571
 572 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 573
 574 #endif  /* __CONFIG_H */