include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P2041 RDB board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_P2041RDB
  31 #define CONFIG_PHYS_64BIT
  32 #define CONFIG_PPC_P2041
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE
  41 #define CONFIG_E500                     /* BOOKE e500 family */
  42 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  43 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  44 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  45 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  46 #define CONFIG_MP                       /* support multiple processors */
  47
  48 #ifndef CONFIG_SYS_TEXT_BASE
  49 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  50 #endif
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  57 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  58 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  59 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  60 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  61 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  62 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  63 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  64 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  65
  66 #define CONFIG_SYS_SRIO
  67 #define CONFIG_SRIO1                    /* SRIO port 1 */
  68 #define CONFIG_SRIO2                    /* SRIO port 2 */
  69
  70 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  71
  72 #define CONFIG_ENV_OVERWRITE
  73
  74 #ifdef CONFIG_SYS_NO_FLASH
  75 #define CONFIG_ENV_IS_NOWHERE
  76 #else
  77 #define CONFIG_FLASH_CFI_DRIVER
  78 #define CONFIG_SYS_FLASH_CFI
  79 #endif
  80
  81 #if defined(CONFIG_SPIFLASH)
  82         #define CONFIG_SYS_EXTRA_ENV_RELOC
  83         #define CONFIG_ENV_IS_IN_SPI_FLASH
  84         #define CONFIG_ENV_SPI_BUS              0
  85         #define CONFIG_ENV_SPI_CS               0
  86         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  87         #define CONFIG_ENV_SPI_MODE             0
  88         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  89         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  90         #define CONFIG_ENV_SECT_SIZE            0x10000
  91 #elif defined(CONFIG_SDCARD)
  92         #define CONFIG_SYS_EXTRA_ENV_RELOC
  93         #define CONFIG_ENV_IS_IN_MMC
  94         #define CONFIG_SYS_MMC_ENV_DEV          0
  95         #define CONFIG_ENV_SIZE                 0x2000
  96         #define CONFIG_ENV_OFFSET               (512 * 1097)
  97 #else
  98         #define CONFIG_ENV_IS_IN_FLASH
  99         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 100                         - CONFIG_ENV_SECT_SIZE)
 101         #define CONFIG_ENV_SIZE         0x2000
 102         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 103 #endif
 104
 105 #define CONFIG_SYS_CLK_FREQ     66666666
 106
 107 /*
 108  * These can be toggled for performance analysis, otherwise use default.
 109  */
 110 #define CONFIG_SYS_CACHE_STASHING
 111 #define CONFIG_BACKSIDE_L2_CACHE
 112 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 113 #define CONFIG_BTB                      /* toggle branch predition */
 114
 115 #define CONFIG_ENABLE_36BIT_PHYS
 116
 117 #ifdef CONFIG_PHYS_64BIT
 118 #define CONFIG_ADDR_MAP
 119 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 120 #endif
 121
 122 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 123 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 124 #define CONFIG_SYS_MEMTEST_END          0x00400000
 125 #define CONFIG_SYS_ALT_MEMTEST
 126 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 127
 128 /*
 129  *  Config the L3 Cache as L3 SRAM
 130  */
 131 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 134                 CONFIG_RAMBOOT_TEXT_BASE)
 135 #else
 136 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 137 #endif
 138 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 139 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 140
 141 /*
 142  * Base addresses -- Note these are effective addresses where the
 143  * actual resources get mapped (not physical addresses)
 144  */
 145 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xfe000000      /* CCSRBAR Default */
 146 #define CONFIG_SYS_CCSRBAR              0xfe000000      /* relocated CCSRBAR */
 147 #ifdef CONFIG_PHYS_64BIT
 148 #define CONFIG_SYS_CCSRBAR_PHYS         0xffe000000ull
 149 #else
 150 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
 151 #endif
 152 /* PQII uses CONFIG_SYS_IMMR */
 153 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
 154
 155 #ifdef CONFIG_PHYS_64BIT
 156 #define CONFIG_SYS_DCSRBAR              0xf0000000
 157 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 158 #endif
 159
 160 /* EEPROM */
 161 #define CONFIG_ID_EEPROM
 162 #define CONFIG_SYS_I2C_EEPROM_NXID
 163 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 164 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 166
 167 /*
 168  * DDR Setup
 169  */
 170 #define CONFIG_VERY_BIG_RAM
 171 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 172 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 173
 174 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 175 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 176
 177 #define CONFIG_DDR_SPD
 178 #define CONFIG_FSL_DDR3
 179
 180 #define CONFIG_SYS_SPD_BUS_NUM  0
 181 #define SPD_EEPROM_ADDRESS      0x52
 182 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 183
 184 /*
 185  * Local Bus Definitions
 186  */
 187
 188 /* Set the local bus clock 1/8 of platform clock */
 189 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 190
 191 #define CONFIG_SYS_FLASH_BASE           0xe8000000      /* Start of PromJet */
 192 #ifdef CONFIG_PHYS_64BIT
 193 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe8000000ull
 194 #else
 195 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 196 #endif
 197
 198 #define CONFIG_SYS_BR0_PRELIM \
 199                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 200 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 201                                 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 202
 203 #define CONFIG_FSL_CPLD
 204 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 205 #ifdef CONFIG_PHYS_64BIT
 206 #define CPLD_BASE_PHYS          0xfffdf0000ull
 207 #else
 208 #define CPLD_BASE_PHYS          CPLD_BASE
 209 #endif
 210
 211 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 212 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 213
 214 #define PIXIS_LBMAP_SWITCH      7
 215 #define PIXIS_LBMAP_MASK        0xf0
 216 #define PIXIS_LBMAP_SHIFT       4
 217 #define PIXIS_LBMAP_ALTBANK     0x40
 218
 219 #define CONFIG_SYS_FLASH_QUIET_TEST
 220 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 221
 222 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 223 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 224 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 225 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 226
 227 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 228
 229 #if defined(CONFIG_RAMBOOT_PBL)
 230 #define CONFIG_SYS_RAMBOOT
 231 #endif
 232
 233 #define CONFIG_SYS_FLASH_EMPTY_INFO
 234 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 235 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 236
 237 #define CONFIG_BOARD_EARLY_INIT_F
 238 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 239 #define CONFIG_MISC_INIT_R
 240
 241 #define CONFIG_HWCONFIG
 242
 243 /* define to use L1 as initial stack */
 244 #define CONFIG_L1_INIT_RAM
 245 #define CONFIG_SYS_INIT_RAM_LOCK
 246 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 247 #ifdef CONFIG_PHYS_64BIT
 248 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 249 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 250 /* The assembler doesn't like typecast */
 251 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 252         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 253           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 254 #else
 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 257 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 258 #endif
 259 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 260
 261 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 262                                         GENERATED_GBL_DATA_SIZE)
 263 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 264
 265 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 266 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 267
 268 /* Serial Port - controlled on board with jumper J8
 269  * open - index 2
 270  * shorted - index 1
 271  */
 272 #define CONFIG_CONS_INDEX       1
 273 #define CONFIG_SYS_NS16550
 274 #define CONFIG_SYS_NS16550_SERIAL
 275 #define CONFIG_SYS_NS16550_REG_SIZE     1
 276 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 277
 278 #define CONFIG_SYS_BAUDRATE_TABLE       \
 279         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 280
 281 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 282 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 283 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 284 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 285
 286 /* Use the HUSH parser */
 287 #define CONFIG_SYS_HUSH_PARSER
 288 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 289
 290 /* pass open firmware flat tree */
 291 #define CONFIG_OF_LIBFDT
 292 #define CONFIG_OF_BOARD_SETUP
 293 #define CONFIG_OF_STDOUT_VIA_ALIAS
 294
 295 /* new uImage format support */
 296 #define CONFIG_FIT
 297 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 298
 299 /* I2C */
 300 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 301 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 302 #define CONFIG_I2C_MULTI_BUS
 303 #define CONFIG_I2C_CMD_TREE
 304 #define CONFIG_SYS_I2C_SPEED            400000
 305 #define CONFIG_SYS_I2C_SLAVE            0x7F
 306 #define CONFIG_SYS_I2C_OFFSET           0x118000
 307 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 308
 309 /*
 310  * RapidIO
 311  */
 312 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 315 #else
 316 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 317 #endif
 318 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 319
 320 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 321 #ifdef CONFIG_PHYS_64BIT
 322 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 323 #else
 324 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 325 #endif
 326 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 327
 328 /*
 329  * eSPI - Enhanced SPI
 330  */
 331 #define CONFIG_FSL_ESPI
 332 #define CONFIG_SPI_FLASH
 333 #define CONFIG_SPI_FLASH_SPANSION
 334 #define CONFIG_CMD_SF
 335 #define CONFIG_SF_DEFAULT_SPEED         10000000
 336 #define CONFIG_SF_DEFAULT_MODE          0
 337
 338 /*
 339  * General PCI
 340  * Memory space is mapped 1-1, but I/O space must start from 0.
 341  */
 342
 343 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 344 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 345 #ifdef CONFIG_PHYS_64BIT
 346 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 347 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 348 #else
 349 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 350 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 351 #endif
 352 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 353 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 354 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 355 #ifdef CONFIG_PHYS_64BIT
 356 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 357 #else
 358 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 359 #endif
 360 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 361
 362 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 363 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 364 #ifdef CONFIG_PHYS_64BIT
 365 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 366 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 367 #else
 368 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 369 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 370 #endif
 371 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 372 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 373 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 374 #ifdef CONFIG_PHYS_64BIT
 375 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 376 #else
 377 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 378 #endif
 379 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 380
 381 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 382 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 383 #ifdef CONFIG_PHYS_64BIT
 384 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 385 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 386 #else
 387 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 388 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 389 #endif
 390 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 391 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 392 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 393 #ifdef CONFIG_PHYS_64BIT
 394 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 395 #else
 396 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 397 #endif
 398 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 399
 400 /* Qman/Bman */
 401 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 402 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 403 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 406 #else
 407 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 408 #endif
 409 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 410 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 411 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 412 #ifdef CONFIG_PHYS_64BIT
 413 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 414 #else
 415 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 416 #endif
 417 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 418
 419 #define CONFIG_SYS_DPAA_FMAN
 420 #define CONFIG_SYS_DPAA_PME
 421 /* Default address of microcode for the Linux Fman driver */
 422 #define CONFIG_SYS_FMAN_FW
 423 #if defined(CONFIG_SPIFLASH)
 424 /*
 425  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 426  * env, so we got 0x110000.
 427  */
 428 #define CONFIG_SYS_QE_FW_IN_SPIFLASH    0x110000
 429 #elif defined(CONFIG_SDCARD)
 430 /*
 431  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 432  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 433  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 434  */
 435 #define CONFIG_SYS_QE_FW_IN_MMC         (512 * 1130)
 436 #elif defined(CONFIG_NAND)
 437 #define CONFIG_SYS_QE_FW_IN_NAND        (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 438 #else
 439 #define CONFIG_SYS_FMAN_FW_ADDR         0xEF000000
 440 #endif
 441 #define CONFIG_SYS_FMAN_FW_LENGTH       0x10000
 442 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
 443
 444 #ifdef CONFIG_SYS_DPAA_FMAN
 445 #define CONFIG_FMAN_ENET
 446 #endif
 447
 448 #ifdef CONFIG_PCI
 449 #define CONFIG_NET_MULTI
 450 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 451 #define CONFIG_E1000
 452
 453 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 454 #define CONFIG_DOS_PARTITION
 455 #endif  /* CONFIG_PCI */
 456
 457 /* SATA */
 458 #define CONFIG_FSL_SATA_V2
 459 #ifdef CONFIG_FSL_SATA_V2
 460 #define CONFIG_LIBATA
 461 #define CONFIG_FSL_SATA
 462
 463 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 464 #define CONFIG_SATA1
 465 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 466 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 467 #define CONFIG_SATA2
 468 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 469 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 470
 471 #define CONFIG_LBA48
 472 #define CONFIG_CMD_SATA
 473 #define CONFIG_DOS_PARTITION
 474 #define CONFIG_CMD_EXT2
 475 #endif
 476
 477 #ifdef CONFIG_FMAN_ENET
 478 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 479 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 480 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 481 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 482 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 483
 484 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 485 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 486 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 487 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 488
 489 #define CONFIG_SYS_TBIPA_VALUE  8
 490 #define CONFIG_MII              /* MII PHY management */
 491 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 492 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 493 #endif
 494
 495 /*
 496  * Environment
 497  */
 498 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 499 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 500
 501 /*
 502  * Command line configuration.
 503  */
 504 #include <config_cmd_default.h>
 505
 506 #define CONFIG_CMD_DHCP
 507 #define CONFIG_CMD_ELF
 508 #define CONFIG_CMD_ERRATA
 509 #define CONFIG_CMD_GREPENV
 510 #define CONFIG_CMD_IRQ
 511 #define CONFIG_CMD_I2C
 512 #define CONFIG_CMD_MII
 513 #define CONFIG_CMD_PING
 514 #define CONFIG_CMD_SETEXPR
 515
 516 #ifdef CONFIG_PCI
 517 #define CONFIG_CMD_PCI
 518 #define CONFIG_CMD_NET
 519 #endif
 520
 521 /*
 522 * USB
 523 */
 524 #define CONFIG_CMD_USB
 525 #define CONFIG_USB_STORAGE
 526 #define CONFIG_USB_EHCI
 527 #define CONFIG_USB_EHCI_FSL
 528 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 529 #define CONFIG_CMD_EXT2
 530
 531 #define CONFIG_MMC
 532
 533 #ifdef CONFIG_MMC
 534 #define CONFIG_FSL_ESDHC
 535 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 536 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 537 #define CONFIG_CMD_MMC
 538 #define CONFIG_GENERIC_MMC
 539 #define CONFIG_CMD_EXT2
 540 #define CONFIG_CMD_FAT
 541 #define CONFIG_DOS_PARTITION
 542 #endif
 543
 544 /*
 545  * Miscellaneous configurable options
 546  */
 547 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 548 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 549 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 550 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 551 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 552 #ifdef CONFIG_CMD_KGDB
 553 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 554 #else
 555 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 556 #endif
 557 /* Print Buffer Size */
 558 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 559                                 sizeof(CONFIG_SYS_PROMPT)+16)
 560 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 561 /* Boot Argument Buffer Size */
 562 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 563 #define CONFIG_SYS_HZ           1000            /* decrementer freq 1ms ticks */
 564
 565 /*
 566  * For booting Linux, the board info and command line data
 567  * have to be in the first 64 MB of memory, since this is
 568  * the maximum mapped by the Linux kernel during initialization.
 569  */
 570 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 571 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 572
 573 #ifdef CONFIG_CMD_KGDB
 574 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 575 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 576 #endif
 577
 578 /*
 579  * Environment Configuration
 580  */
 581 #define CONFIG_ROOTPATH         /opt/nfsroot
 582 #define CONFIG_BOOTFILE         uImage
 583 #define CONFIG_UBOOTPATH        u-boot.bin
 584
 585 /* default location for tftp and bootm */
 586 #define CONFIG_LOADADDR         1000000
 587
 588 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 589
 590 #define CONFIG_BAUDRATE 115200
 591
 592 #define __USB_PHY_TYPE  utmi
 593
 594 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 595         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 596         "bank_intlv=cs0_cs1\0"                                  \
 597         "netdev=eth0\0"                                         \
 598         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
 599         "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"          \
 600         "tftpflash=tftpboot $loadaddr $uboot && "               \
 601         "protect off $ubootaddr +$filesize && "                 \
 602         "erase $ubootaddr +$filesize && "                       \
 603         "cp.b $loadaddr $ubootaddr $filesize && "               \
 604         "protect on $ubootaddr +$filesize && "                  \
 605         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 606         "consoledev=ttyS0\0"                                    \
 607         "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0"             \
 608         "usb_dr_mode=host\0"                                    \
 609         "ramdiskaddr=2000000\0"                                 \
 610         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 611         "fdtaddr=c00000\0"                                      \
 612         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 613         "bdev=sda3\0"                                           \
 614         "c=ffe\0"
 615
 616 #define CONFIG_HDBOOT                                   \
 617         "setenv bootargs root=/dev/$bdev rw "           \
 618         "console=$consoledev,$baudrate $othbootargs;"   \
 619         "tftp $loadaddr $bootfile;"                     \
 620         "tftp $fdtaddr $fdtfile;"                       \
 621         "bootm $loadaddr - $fdtaddr"
 622
 623 #define CONFIG_NFSBOOTCOMMAND                   \
 624         "setenv bootargs root=/dev/nfs rw "     \
 625         "nfsroot=$serverip:$rootpath "          \
 626         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 627         "console=$consoledev,$baudrate $othbootargs;"   \
 628         "tftp $loadaddr $bootfile;"             \
 629         "tftp $fdtaddr $fdtfile;"               \
 630         "bootm $loadaddr - $fdtaddr"
 631
 632 #define CONFIG_RAMBOOTCOMMAND                           \
 633         "setenv bootargs root=/dev/ram rw "             \
 634         "console=$consoledev,$baudrate $othbootargs;"   \
 635         "tftp $ramdiskaddr $ramdiskfile;"               \
 636         "tftp $loadaddr $bootfile;"                     \
 637         "tftp $fdtaddr $fdtfile;"                       \
 638         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 639
 640 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 641
 642 #ifdef CONFIG_SECURE_BOOT
 643 #include <asm/fsl_secure_boot.h>
 644 #endif
 645
 646 #endif  /* __CONFIG_H */