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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/P2041RDB.h
d3b655fda93d27f0dc09e89c170d9b6f5a5cd4b2
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #ifdef CONFIG_RAMBOOT_PBL
15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 /* High Level Configuration Options */
30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
31 #define CONFIG_MP /* support multiple processors */
33 #ifndef CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_TEXT_BASE 0xeff40000
37 #ifndef CONFIG_RESET_VECTOR_ADDRESS
38 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
42 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
43 #define CONFIG_PCIE1 /* PCIE controller 1 */
44 #define CONFIG_PCIE2 /* PCIE controller 2 */
45 #define CONFIG_PCIE3 /* PCIE controller 3 */
46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
49 #define CONFIG_SYS_SRIO
50 #define CONFIG_SRIO1 /* SRIO port 1 */
51 #define CONFIG_SRIO2 /* SRIO port 2 */
52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
53 #define CONFIG_SYS_DPAA_RMAN /* RMan */
55 #define CONFIG_ENV_OVERWRITE
57 #ifndef CONFIG_MTD_NOR_FLASH
59 #define CONFIG_FLASH_CFI_DRIVER
60 #define CONFIG_SYS_FLASH_CFI
61 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
64 #if defined(CONFIG_SPIFLASH)
65 #define CONFIG_SYS_EXTRA_ENV_RELOC
66 #define CONFIG_ENV_IS_IN_SPI_FLASH
67 #define CONFIG_ENV_SPI_BUS 0
68 #define CONFIG_ENV_SPI_CS 0
69 #define CONFIG_ENV_SPI_MAX_HZ 10000000
70 #define CONFIG_ENV_SPI_MODE 0
71 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
72 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
73 #define CONFIG_ENV_SECT_SIZE 0x10000
74 #elif defined(CONFIG_SDCARD)
75 #define CONFIG_SYS_EXTRA_ENV_RELOC
76 #define CONFIG_FSL_FIXED_MMC_LOCATION
77 #define CONFIG_SYS_MMC_ENV_DEV 0
78 #define CONFIG_ENV_SIZE 0x2000
79 #define CONFIG_ENV_OFFSET (512 * 1658)
80 #elif defined(CONFIG_NAND)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
83 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
84 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
85 #define CONFIG_ENV_IS_IN_REMOTE
86 #define CONFIG_ENV_ADDR 0xffe20000
87 #define CONFIG_ENV_SIZE 0x2000
88 #elif defined(CONFIG_ENV_IS_NOWHERE)
89 #define CONFIG_ENV_SIZE 0x2000
91 #define CONFIG_ENV_IS_IN_FLASH
92 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
93 - CONFIG_ENV_SECT_SIZE)
94 #define CONFIG_ENV_SIZE 0x2000
95 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
99 unsigned long get_board_sys_clk(unsigned long dummy
);
101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
104 * These can be toggled for performance analysis, otherwise use default.
106 #define CONFIG_SYS_CACHE_STASHING
107 #define CONFIG_BACKSIDE_L2_CACHE
108 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
109 #define CONFIG_BTB /* toggle branch predition */
111 #define CONFIG_ENABLE_36BIT_PHYS
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_ADDR_MAP
115 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
118 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
119 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_END 0x00400000
121 #define CONFIG_SYS_ALT_MEMTEST
122 #define CONFIG_PANIC_HANG /* do not reset board on panic */
125 * Config the L3 Cache as L3 SRAM
127 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
130 CONFIG_RAMBOOT_TEXT_BASE)
132 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
134 #define CONFIG_SYS_L3_SIZE (1024 << 10)
135 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SYS_DCSRBAR 0xf0000000
139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
143 #define CONFIG_ID_EEPROM
144 #define CONFIG_SYS_I2C_EEPROM_NXID
145 #define CONFIG_SYS_EEPROM_BUS_NUM 0
146 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
152 #define CONFIG_VERY_BIG_RAM
153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
156 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
157 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
159 #define CONFIG_DDR_SPD
161 #define CONFIG_SYS_SPD_BUS_NUM 0
162 #define SPD_EEPROM_ADDRESS 0x52
163 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
166 * Local Bus Definitions
169 /* Set the local bus clock 1/8 of platform clock */
170 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
173 * This board doesn't have a promjet connector.
174 * However, it uses commone corenet board LAW and TLB.
175 * It is necessary to use the same start address with proper offset.
177 #define CONFIG_SYS_FLASH_BASE 0xe0000000
178 #ifdef CONFIG_PHYS_64BIT
179 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
184 #define CONFIG_SYS_FLASH_BR_PRELIM \
185 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
187 #define CONFIG_SYS_FLASH_OR_PRELIM \
188 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
189 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
191 #define CONFIG_FSL_CPLD
192 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
193 #ifdef CONFIG_PHYS_64BIT
194 #define CPLD_BASE_PHYS 0xfffdf0000ull
196 #define CPLD_BASE_PHYS CPLD_BASE
199 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
200 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
202 #define PIXIS_LBMAP_SWITCH 7
203 #define PIXIS_LBMAP_MASK 0xf0
204 #define PIXIS_LBMAP_SHIFT 4
205 #define PIXIS_LBMAP_ALTBANK 0x40
207 #define CONFIG_SYS_FLASH_QUIET_TEST
208 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
211 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
215 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
217 #if defined(CONFIG_RAMBOOT_PBL)
218 #define CONFIG_SYS_RAMBOOT
221 #define CONFIG_NAND_FSL_ELBC
223 #ifdef CONFIG_NAND_FSL_ELBC
224 #define CONFIG_SYS_NAND_BASE 0xffa00000
225 #ifdef CONFIG_PHYS_64BIT
226 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
228 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
231 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
232 #define CONFIG_SYS_MAX_NAND_DEVICE 1
233 #define CONFIG_CMD_NAND
234 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
236 /* NAND flash config */
237 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
238 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
239 | BR_PS_8 /* Port Size = 8 bit */ \
240 | BR_MS_FCM /* MSEL = FCM */ \
242 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
243 | OR_FCM_PGS /* Large Page*/ \
252 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
253 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
254 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
255 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
259 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
260 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
263 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
264 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
265 #endif /* CONFIG_NAND_FSL_ELBC */
267 #define CONFIG_SYS_FLASH_EMPTY_INFO
268 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
271 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
272 #define CONFIG_MISC_INIT_R
274 #define CONFIG_HWCONFIG
276 /* define to use L1 as initial stack */
277 #define CONFIG_L1_INIT_RAM
278 #define CONFIG_SYS_INIT_RAM_LOCK
279 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
283 /* The assembler doesn't like typecast */
284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
285 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
286 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
292 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
294 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
295 GENERATED_GBL_DATA_SIZE)
296 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
298 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
299 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
301 /* Serial Port - controlled on board with jumper J8
305 #define CONFIG_CONS_INDEX 1
306 #define CONFIG_SYS_NS16550_SERIAL
307 #define CONFIG_SYS_NS16550_REG_SIZE 1
308 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
310 #define CONFIG_SYS_BAUDRATE_TABLE \
311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
315 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
316 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
319 #define CONFIG_SYS_I2C
320 #define CONFIG_SYS_I2C_FSL
321 #define CONFIG_SYS_FSL_I2C_SPEED 400000
322 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
323 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
324 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
325 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
326 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
331 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
332 #ifdef CONFIG_PHYS_64BIT
333 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
335 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
337 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
339 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
340 #ifdef CONFIG_PHYS_64BIT
341 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
343 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
345 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
348 * for slave u-boot IMAGE instored in master memory space,
349 * PHYS must be aligned based on the SIZE
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
354 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
356 * for slave UCODE and ENV instored in master memory space,
357 * PHYS must be aligned based on the SIZE
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
361 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
363 /* slave core release by master*/
364 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
365 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
368 * SRIO_PCIE_BOOT - SLAVE
370 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
372 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
373 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
377 * eSPI - Enhanced SPI
379 #define CONFIG_SF_DEFAULT_SPEED 10000000
380 #define CONFIG_SF_DEFAULT_MODE 0
384 * Memory space is mapped 1-1, but I/O space must start from 0.
387 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
388 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
389 #ifdef CONFIG_PHYS_64BIT
390 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
391 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
393 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
394 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
396 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
397 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
398 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
399 #ifdef CONFIG_PHYS_64BIT
400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
402 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
404 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
406 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
407 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
410 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
415 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
416 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
417 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
421 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
423 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
425 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
426 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
429 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
431 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
432 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
434 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
440 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
442 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
445 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
446 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
447 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
448 #ifdef CONFIG_PHYS_64BIT
449 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
451 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
453 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
454 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
455 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
456 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
457 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
458 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
459 CONFIG_SYS_BMAN_CENA_SIZE)
460 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
461 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
462 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
463 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
464 #ifdef CONFIG_PHYS_64BIT
465 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
467 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
469 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
470 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
471 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
472 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
473 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
474 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
475 CONFIG_SYS_QMAN_CENA_SIZE)
476 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
477 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
479 #define CONFIG_SYS_DPAA_FMAN
480 #define CONFIG_SYS_DPAA_PME
481 /* Default address of microcode for the Linux Fman driver */
482 #if defined(CONFIG_SPIFLASH)
484 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
485 * env, so we got 0x110000.
487 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
488 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
489 #elif defined(CONFIG_SDCARD)
491 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
492 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
493 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
495 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
496 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
497 #elif defined(CONFIG_NAND)
498 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
499 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
500 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
502 * Slave has no ucode locally, it can fetch this from remote. When implementing
503 * in two corenet boards, slave's ucode could be stored in master's memory
504 * space, the address can be mapped from slave TLB->slave LAW->
505 * slave SRIO or PCIE outbound window->master inbound window->
506 * master LAW->the ucode address in master's memory space.
508 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
509 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
511 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
512 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
514 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
515 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
517 #ifdef CONFIG_SYS_DPAA_FMAN
518 #define CONFIG_FMAN_ENET
519 #define CONFIG_PHYLIB_10G
520 #define CONFIG_PHY_VITESSE
521 #define CONFIG_PHY_TERANETICS
525 #define CONFIG_PCI_INDIRECT_BRIDGE
527 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
528 #endif /* CONFIG_PCI */
531 #define CONFIG_FSL_SATA_V2
533 #ifdef CONFIG_FSL_SATA_V2
534 #define CONFIG_FSL_SATA
535 #define CONFIG_LIBATA
537 #define CONFIG_SYS_SATA_MAX_DEVICE 2
539 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
540 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
542 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
543 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
548 #ifdef CONFIG_FMAN_ENET
549 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
550 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
551 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
552 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
553 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
555 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
556 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
557 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
558 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
560 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
562 #define CONFIG_SYS_TBIPA_VALUE 8
563 #define CONFIG_MII /* MII PHY management */
564 #define CONFIG_ETHPRIME "FM1@DTSEC1"
565 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
571 #define CONFIG_LOADS_ECHO /* echo on for serial download */
572 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
575 * Command line configuration.
579 #define CONFIG_CMD_PCI
585 #define CONFIG_HAS_FSL_DR_USB
586 #define CONFIG_HAS_FSL_MPH_USB
588 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
589 #define CONFIG_USB_EHCI_FSL
590 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
594 #define CONFIG_FSL_ESDHC
595 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
596 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
600 * Miscellaneous configurable options
602 #define CONFIG_SYS_LONGHELP /* undef to save memory */
603 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
604 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
605 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
606 #ifdef CONFIG_CMD_KGDB
607 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
609 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
611 /* Print Buffer Size */
612 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
613 sizeof(CONFIG_SYS_PROMPT)+16)
614 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
615 /* Boot Argument Buffer Size */
616 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
619 * For booting Linux, the board info and command line data
620 * have to be in the first 64 MB of memory, since this is
621 * the maximum mapped by the Linux kernel during initialization.
623 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
624 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
626 #ifdef CONFIG_CMD_KGDB
627 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
631 * Environment Configuration
633 #define CONFIG_ROOTPATH "/opt/nfsroot"
634 #define CONFIG_BOOTFILE "uImage"
635 #define CONFIG_UBOOTPATH u-boot.bin
637 /* default location for tftp and bootm */
638 #define CONFIG_LOADADDR 1000000
640 #define __USB_PHY_TYPE utmi
642 #define CONFIG_EXTRA_ENV_SETTINGS \
643 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
644 "bank_intlv=cs0_cs1\0" \
646 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
647 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
648 "tftpflash=tftpboot $loadaddr $uboot && " \
649 "protect off $ubootaddr +$filesize && " \
650 "erase $ubootaddr +$filesize && " \
651 "cp.b $loadaddr $ubootaddr $filesize && " \
652 "protect on $ubootaddr +$filesize && " \
653 "cmp.b $loadaddr $ubootaddr $filesize\0" \
654 "consoledev=ttyS0\0" \
655 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
656 "usb_dr_mode=host\0" \
657 "ramdiskaddr=2000000\0" \
658 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
659 "fdtaddr=1e00000\0" \
660 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
663 #define CONFIG_HDBOOT \
664 "setenv bootargs root=/dev/$bdev rw " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "tftp $loadaddr $bootfile;" \
667 "tftp $fdtaddr $fdtfile;" \
668 "bootm $loadaddr - $fdtaddr"
670 #define CONFIG_NFSBOOTCOMMAND \
671 "setenv bootargs root=/dev/nfs rw " \
672 "nfsroot=$serverip:$rootpath " \
673 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
674 "console=$consoledev,$baudrate $othbootargs;" \
675 "tftp $loadaddr $bootfile;" \
676 "tftp $fdtaddr $fdtfile;" \
677 "bootm $loadaddr - $fdtaddr"
679 #define CONFIG_RAMBOOTCOMMAND \
680 "setenv bootargs root=/dev/ram rw " \
681 "console=$consoledev,$baudrate $othbootargs;" \
682 "tftp $ramdiskaddr $ramdiskfile;" \
683 "tftp $loadaddr $bootfile;" \
684 "tftp $fdtaddr $fdtfile;" \
685 "bootm $loadaddr $ramdiskaddr $fdtaddr"
687 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
689 #include <asm/fsl_secure_boot.h>
691 #endif /* __CONFIG_H */