include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation,
  21  */
  22
  23 /*
  24  * File:                PATI.h
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  */
  33
  34 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  35 #define CONFIG_PATI             1               /* ...On a PATI board   */
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  38
  39 /* Serial Console Configuration */
  40 #define CONFIG_5xx_CONS_SCI1
  41 #undef  CONFIG_5xx_CONS_SCI2
  42
  43 #define CONFIG_BAUDRATE         9600
  44
  45
  46 /*
  47  * BOOTP options
  48  */
  49 #define CONFIG_BOOTP_BOOTFILESIZE
  50 #define CONFIG_BOOTP_BOOTPATH
  51 #define CONFIG_BOOTP_GATEWAY
  52 #define CONFIG_BOOTP_HOSTNAME
  53
  54
  55 /*
  56  * Command line configuration.
  57  */
  58 #define CONFIG_CMD_MEMORY
  59 #define CONFIG_CMD_LOADB
  60 #define CONFIG_CMD_REGINFO
  61 #define CONFIG_CMD_FLASH
  62 #define CONFIG_CMD_LOADS
  63 #define CONFIG_CMD_SAVEENV
  64 #define CONFIG_CMD_REGINFO
  65 #define CONFIG_CMD_BDI
  66 #define CONFIG_CMD_CONSOLE
  67 #define CONFIG_CMD_RUN
  68 #define CONFIG_CMD_BSP
  69 #define CONFIG_CMD_IMI
  70 #define CONFIG_CMD_EEPROM
  71 #define CONFIG_CMD_IRQ
  72 #define CONFIG_CMD_MISC
  73
  74
  75 #if 0
  76 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  77 #else
  78 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  79 #endif
  80 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  81
  82 #define CONFIG_BOOTARGS         ""              /* */
  83
  84 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  85
  86 /*#define CONFIG_STATUS_LED     1               */ /* Enable status led */
  87
  88 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  89
  90 /*
  91  * Miscellaneous configurable options
  92  */
  93 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
  94 #define CONFIG_PREBOOT
  95
  96 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  97 #define CONFIG_SYS_PROMPT               "pati=> "               /* Monitor Command Prompt       */
  98 #if defined(CONFIG_CMD_KGDB)
  99 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 100 #else
 101 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 102 #endif
 103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 104 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
 105 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 106
 107 #define CONFIG_SYS_MEMTEST_START        0x00010000      /* memtest works on             */
 108 #define CONFIG_SYS_MEMTEST_END          0x00A00000      /* 10 MB in SRAM                        */
 109
 110 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
 111
 112 #define CONFIG_SYS_HZ                   1000            /* Decrementer freq: 1 ms ticks */
 113
 114 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
 115
 116
 117 /***********************************************************************
 118  * Last Stage Init
 119  ***********************************************************************/
 120 #define CONFIG_LAST_STAGE_INIT
 121
 122 /*
 123  * Low Level Configuration Settings
 124  */
 125
 126 /*
 127  * Internal Memory Mapped (This is not the IMMR content)
 128  */
 129 #define CONFIG_SYS_IMMR         0x01C00000              /* Physical start adress of internal memory map */
 130
 131 /*
 132  * Definitions for initial stack pointer and data area
 133  */
 134 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
 135 #define CONFIG_SYS_INIT_RAM_SIZE        (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
 136 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 137 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000)   /* Physical start adress of inital stack */
 138 /*
 139  * Start addresses for the final memory configuration
 140  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 141  */
 142 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
 143 #define CONFIG_SYS_FLASH_BASE           0xffC00000      /* External flash */
 144 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 145 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 146 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 147
 148 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 149 /* CONFIG_SYS_FLASH_BASE        */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.      */
 150                                                 /* This adress is given to the linker with -Ttext to    */
 151                                                 /* locate the text section at this adress.              */
 152 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 192 kB for Monitor                           */
 153 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()                          */
 154
 155 #define CONFIG_SYS_RESET_ADDRESS        (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 156
 157 /*
 158  * For booting Linux, the board info and command line data
 159  * have to be in the first 8 MB of memory, since this is
 160  * the maximum mapped by the Linux kernel during initialization.
 161  */
 162 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 163
 164
 165 /*-----------------------------------------------------------------------
 166  * FLASH organization
 167  *-----------------------------------------------------------------------
 168  *
 169  */
 170
 171 #define CONFIG_SYS_MAX_FLASH_BANKS              1               /* Max number of memory banks           */
 172 #define CONFIG_SYS_MAX_FLASH_SECT               128             /* Max number of sectors on one chip    */
 173 #define CONFIG_SYS_FLASH_ERASE_TOUT     180000          /* Timeout for Flash Erase (in ms)      */
 174 #define CONFIG_SYS_FLASH_WRITE_TOUT     600             /* Timeout for Flash Write (in ms)      */
 175
 176
 177 #define CONFIG_ENV_IS_IN_EEPROM
 178 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 179 #define CONFIG_ENV_OFFSET               0
 180 #define CONFIG_ENV_SIZE         2048
 181 #endif
 182
 183 #undef  CONFIG_ENV_IS_IN_FLASH
 184 #ifdef  CONFIG_ENV_IS_IN_FLASH
 185 #define CONFIG_ENV_SIZE         0x00002000              /* Set whole sector as env              */
 186 #define CONFIG_ENV_OFFSET               ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)         /* Environment starts at this adress    */
 187 #endif
 188
 189
 190 #define CONFIG_SPI              1
 191 #define CONFIG_SYS_SPI_CS_USED  0x09 /* CS0 and CS3 are used */
 192 #define CONFIG_SYS_SPI_CS_BASE  0x08 /* CS3 is active low */
 193 #define CONFIG_SYS_SPI_CS_ACT   0x00 /* CS3 is active low */
 194 /*-----------------------------------------------------------------------
 195  * SYPCR - System Protection Control
 196  * SYPCR can only be written once after reset!
 197  *-----------------------------------------------------------------------
 198  * SW Watchdog freeze
 199  */
 200 #undef CONFIG_WATCHDOG
 201 #if defined(CONFIG_WATCHDOG)
 202 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 203                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 204 #else
 205 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 206                          SYPCR_SWP)
 207 #endif  /* CONFIG_WATCHDOG */
 208
 209 /*-----------------------------------------------------------------------
 210  * TBSCR - Time Base Status and Control
 211  *-----------------------------------------------------------------------
 212  * Clear Reference Interrupt Status, Timebase freezing enabled
 213  */
 214 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 215
 216 /*-----------------------------------------------------------------------
 217  * PISCR - Periodic Interrupt Status and Control
 218  *-----------------------------------------------------------------------
 219  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 220  */
 221 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 222
 223 /*-----------------------------------------------------------------------
 224  * SCCR - System Clock and reset Control Register
 225  *-----------------------------------------------------------------------
 226  * Set clock output, timebase and RTC source and divider,
 227  * power management and some other internal clocks
 228  */
 229 #define SCCR_MASK       SCCR_EBDF00
 230 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 231                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 232
 233 /*-----------------------------------------------------------------------
 234  * SIUMCR - SIU Module Configuration
 235  *-----------------------------------------------------------------------
 236  * Data show cycle
 237  */
 238 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
 239
 240 /*-----------------------------------------------------------------------
 241  * PLPRCR - PLL, Low-Power, and Reset Control Register
 242  *-----------------------------------------------------------------------
 243  * Set all bits to 40 Mhz
 244  *
 245  */
 246 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 247
 248
 249 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 250
 251 /*-----------------------------------------------------------------------
 252  * UMCR - UIMB Module Configuration Register
 253  *-----------------------------------------------------------------------
 254  *
 255  */
 256 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 257
 258 /*-----------------------------------------------------------------------
 259  * ICTRL - I-Bus Support Control Register
 260  */
 261 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 262
 263 /*-----------------------------------------------------------------------
 264  * USIU - Memory Controller Register
 265  *-----------------------------------------------------------------------
 266  */
 267 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 268 #define CONFIG_SYS_OR0_PRELIM           (0xffc00000) /* SCY is not used if external TA is set */
 269 /* SDRAM */
 270 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 271 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 272 /* PCI */
 273 #define CONFIG_SYS_BR2_PRELIM           (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 274 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 275 /* config registers: */
 276 #define CONFIG_SYS_BR3_PRELIM           (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 277 #define CONFIG_SYS_OR3_PRELIM           (0xffff0000)
 278
 279 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 280
 281 /*-----------------------------------------------------------------------
 282  * DER - Timer Decrementer
 283  *-----------------------------------------------------------------------
 284  * Initialise to zero
 285  */
 286 #define CONFIG_SYS_DER                  0x00000000
 287
 288 #define VERSION_TAG "released"
 289 #define CONFIG_ISO_STRING "MEV-10084-001"
 290
 291 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 292
 293 #endif  /* __CONFIG_H */