include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * File:                PATI.h
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18
  19 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  20 #define CONFIG_PATI             1               /* ...On a PATI board   */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  23
  24 /* Serial Console Configuration */
  25 #define CONFIG_5xx_CONS_SCI1
  26 #undef  CONFIG_5xx_CONS_SCI2
  27
  28 #define CONFIG_BAUDRATE         9600
  29
  30
  31 /*
  32  * BOOTP options
  33  */
  34 #define CONFIG_BOOTP_BOOTFILESIZE
  35 #define CONFIG_BOOTP_BOOTPATH
  36 #define CONFIG_BOOTP_GATEWAY
  37 #define CONFIG_BOOTP_HOSTNAME
  38
  39
  40 /*
  41  * Command line configuration.
  42  */
  43 #define CONFIG_CMD_MEMORY
  44 #define CONFIG_CMD_LOADB
  45 #define CONFIG_CMD_REGINFO
  46 #define CONFIG_CMD_FLASH
  47 #define CONFIG_CMD_LOADS
  48 #define CONFIG_CMD_SAVEENV
  49 #define CONFIG_CMD_REGINFO
  50 #define CONFIG_CMD_BDI
  51 #define CONFIG_CMD_CONSOLE
  52 #define CONFIG_CMD_RUN
  53 #define CONFIG_CMD_BSP
  54 #define CONFIG_CMD_IMI
  55 #define CONFIG_CMD_EEPROM
  56 #define CONFIG_CMD_IRQ
  57 #define CONFIG_CMD_MISC
  58
  59
  60 #if 0
  61 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  62 #else
  63 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  64 #endif
  65 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  66
  67 #define CONFIG_BOOTARGS         ""              /* */
  68
  69 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  70
  71 /*#define CONFIG_STATUS_LED     1               */ /* Enable status led */
  72
  73 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  74
  75 /*
  76  * Miscellaneous configurable options
  77  */
  78 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
  79 #define CONFIG_PREBOOT
  80
  81 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  82 #define CONFIG_SYS_PROMPT               "pati=> "               /* Monitor Command Prompt       */
  83 #if defined(CONFIG_CMD_KGDB)
  84 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  85 #else
  86 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  87 #endif
  88 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  89 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
  90 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  91
  92 #define CONFIG_SYS_MEMTEST_START        0x00010000      /* memtest works on             */
  93 #define CONFIG_SYS_MEMTEST_END          0x00A00000      /* 10 MB in SRAM                        */
  94
  95 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
  96
  97 #define CONFIG_SYS_HZ                   1000            /* Decrementer freq: 1 ms ticks */
  98
  99 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
 100
 101
 102 /***********************************************************************
 103  * Last Stage Init
 104  ***********************************************************************/
 105 #define CONFIG_LAST_STAGE_INIT
 106
 107 /*
 108  * Low Level Configuration Settings
 109  */
 110
 111 /*
 112  * Internal Memory Mapped (This is not the IMMR content)
 113  */
 114 #define CONFIG_SYS_IMMR         0x01C00000              /* Physical start adress of internal memory map */
 115
 116 /*
 117  * Definitions for initial stack pointer and data area
 118  */
 119 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
 120 #define CONFIG_SYS_INIT_RAM_SIZE        (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
 121 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 122 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000)   /* Physical start adress of inital stack */
 123 /*
 124  * Start addresses for the final memory configuration
 125  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 126  */
 127 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
 128 #define CONFIG_SYS_FLASH_BASE           0xffC00000      /* External flash */
 129 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 130 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 131 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 132
 133 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 134 /* CONFIG_SYS_FLASH_BASE        */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.      */
 135                                                 /* This adress is given to the linker with -Ttext to    */
 136                                                 /* locate the text section at this adress.              */
 137 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 192 kB for Monitor                           */
 138 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()                          */
 139
 140 #define CONFIG_SYS_RESET_ADDRESS        (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 141
 142 /*
 143  * For booting Linux, the board info and command line data
 144  * have to be in the first 8 MB of memory, since this is
 145  * the maximum mapped by the Linux kernel during initialization.
 146  */
 147 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 148
 149
 150 /*-----------------------------------------------------------------------
 151  * FLASH organization
 152  *-----------------------------------------------------------------------
 153  *
 154  */
 155
 156 #define CONFIG_SYS_FLASH_PROTECTION
 157 #define CONFIG_SYS_FLASH_EMPTY_INFO
 158
 159 #define CONFIG_SYS_FLASH_CFI
 160 #define CONFIG_FLASH_CFI_DRIVER
 161
 162 #define CONFIG_FLASH_SHOW_PROGRESS      45
 163
 164 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 165 #define CONFIG_SYS_MAX_FLASH_SECT       128
 166
 167 #define CONFIG_ENV_IS_IN_EEPROM
 168 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 169 #define CONFIG_ENV_OFFSET               0
 170 #define CONFIG_ENV_SIZE         2048
 171 #endif
 172
 173 #undef  CONFIG_ENV_IS_IN_FLASH
 174 #ifdef  CONFIG_ENV_IS_IN_FLASH
 175 #define CONFIG_ENV_SIZE         0x00002000              /* Set whole sector as env              */
 176 #define CONFIG_ENV_OFFSET               ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)         /* Environment starts at this adress    */
 177 #endif
 178
 179
 180 #define CONFIG_SPI              1
 181 #define CONFIG_SYS_SPI_CS_USED  0x09 /* CS0 and CS3 are used */
 182 #define CONFIG_SYS_SPI_CS_BASE  0x08 /* CS3 is active low */
 183 #define CONFIG_SYS_SPI_CS_ACT   0x00 /* CS3 is active low */
 184 /*-----------------------------------------------------------------------
 185  * SYPCR - System Protection Control
 186  * SYPCR can only be written once after reset!
 187  *-----------------------------------------------------------------------
 188  * SW Watchdog freeze
 189  */
 190 #undef CONFIG_WATCHDOG
 191 #if defined(CONFIG_WATCHDOG)
 192 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 193                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 194 #else
 195 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 196                          SYPCR_SWP)
 197 #endif  /* CONFIG_WATCHDOG */
 198
 199 /*-----------------------------------------------------------------------
 200  * TBSCR - Time Base Status and Control
 201  *-----------------------------------------------------------------------
 202  * Clear Reference Interrupt Status, Timebase freezing enabled
 203  */
 204 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 205
 206 /*-----------------------------------------------------------------------
 207  * PISCR - Periodic Interrupt Status and Control
 208  *-----------------------------------------------------------------------
 209  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 210  */
 211 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 212
 213 /*-----------------------------------------------------------------------
 214  * SCCR - System Clock and reset Control Register
 215  *-----------------------------------------------------------------------
 216  * Set clock output, timebase and RTC source and divider,
 217  * power management and some other internal clocks
 218  */
 219 #define SCCR_MASK       SCCR_EBDF00
 220 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 221                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 222
 223 /*-----------------------------------------------------------------------
 224  * SIUMCR - SIU Module Configuration
 225  *-----------------------------------------------------------------------
 226  * Data show cycle
 227  */
 228 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
 229
 230 /*-----------------------------------------------------------------------
 231  * PLPRCR - PLL, Low-Power, and Reset Control Register
 232  *-----------------------------------------------------------------------
 233  * Set all bits to 40 Mhz
 234  *
 235  */
 236 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 237
 238
 239 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 240
 241 /*-----------------------------------------------------------------------
 242  * UMCR - UIMB Module Configuration Register
 243  *-----------------------------------------------------------------------
 244  *
 245  */
 246 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 247
 248 /*-----------------------------------------------------------------------
 249  * ICTRL - I-Bus Support Control Register
 250  */
 251 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 252
 253 /*-----------------------------------------------------------------------
 254  * USIU - Memory Controller Register
 255  *-----------------------------------------------------------------------
 256  */
 257 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 258 #define CONFIG_SYS_OR0_PRELIM           (0xffc00000) /* SCY is not used if external TA is set */
 259 /* SDRAM */
 260 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 261 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 262 /* PCI */
 263 #define CONFIG_SYS_BR2_PRELIM           (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 264 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 265 /* config registers: */
 266 #define CONFIG_SYS_BR3_PRELIM           (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 267 #define CONFIG_SYS_OR3_PRELIM           (0xffff0000)
 268
 269 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 270
 271 /*-----------------------------------------------------------------------
 272  * DER - Timer Decrementer
 273  *-----------------------------------------------------------------------
 274  * Initialise to zero
 275  */
 276 #define CONFIG_SYS_DER                  0x00000000
 277
 278 #define VERSION_TAG "released"
 279 #define CONFIG_ISO_STRING "MEV-10084-001"
 280
 281 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 282
 283 #endif  /* __CONFIG_H */