include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * File:                PATI.h
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18
  19 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  20 #define CONFIG_PATI             1               /* ...On a PATI board   */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  23
  24 /* Serial Console Configuration */
  25 #define CONFIG_5xx_CONS_SCI1
  26 #undef  CONFIG_5xx_CONS_SCI2
  27
  28 #define CONFIG_BAUDRATE         9600
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 /*
  39  * Command line configuration.
  40  */
  41 #define CONFIG_CMD_REGINFO
  42 #define CONFIG_CMD_REGINFO
  43 #define CONFIG_CMD_BSP
  44 #define CONFIG_CMD_EEPROM
  45 #define CONFIG_CMD_IRQ
  46
  47 #if 0
  48 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  49 #else
  50 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  51 #endif
  52 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  53
  54 #define CONFIG_BOOTARGS         ""              /* */
  55
  56 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  57
  58 /*#define CONFIG_STATUS_LED     1               */ /* Enable status led */
  59
  60 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  61
  62 /*
  63  * Miscellaneous configurable options
  64  */
  65 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
  66 #define CONFIG_PREBOOT
  67
  68 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  69 #if defined(CONFIG_CMD_KGDB)
  70 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  71 #else
  72 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  73 #endif
  74 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  75 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
  76 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  77
  78 #define CONFIG_SYS_MEMTEST_START        0x00010000      /* memtest works on             */
  79 #define CONFIG_SYS_MEMTEST_END          0x00A00000      /* 10 MB in SRAM                        */
  80
  81 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
  82
  83 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
  84
  85 #define CONFIG_BOARD_EARLY_INIT_F
  86
  87 /***********************************************************************
  88  * Last Stage Init
  89  ***********************************************************************/
  90 #define CONFIG_LAST_STAGE_INIT
  91
  92 /*
  93  * Low Level Configuration Settings
  94  */
  95
  96 /*
  97  * Internal Memory Mapped (This is not the IMMR content)
  98  */
  99 #define CONFIG_SYS_IMMR         0x01C00000              /* Physical start adress of internal memory map */
 100
 101 /*
 102  * Definitions for initial stack pointer and data area
 103  */
 104 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
 105 #define CONFIG_SYS_INIT_RAM_SIZE        (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
 106 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 107 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000)   /* Physical start adress of inital stack */
 108 /*
 109  * Start addresses for the final memory configuration
 110  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 111  */
 112 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
 113 #define CONFIG_SYS_FLASH_BASE           0xffC00000      /* External flash */
 114 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 115 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 116 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 117
 118 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 119 /* CONFIG_SYS_FLASH_BASE        */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.      */
 120                                                 /* This adress is given to the linker with -Ttext to    */
 121                                                 /* locate the text section at this adress.              */
 122 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 192 kB for Monitor                           */
 123 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()                          */
 124
 125 #define CONFIG_SYS_RESET_ADDRESS        (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 126
 127 /*
 128  * For booting Linux, the board info and command line data
 129  * have to be in the first 8 MB of memory, since this is
 130  * the maximum mapped by the Linux kernel during initialization.
 131  */
 132 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 133
 134 /*-----------------------------------------------------------------------
 135  * FLASH organization
 136  *-----------------------------------------------------------------------
 137  *
 138  */
 139
 140 #define CONFIG_SYS_FLASH_PROTECTION
 141 #define CONFIG_SYS_FLASH_EMPTY_INFO
 142
 143 #define CONFIG_SYS_FLASH_CFI
 144 #define CONFIG_FLASH_CFI_DRIVER
 145
 146 #define CONFIG_FLASH_SHOW_PROGRESS      45
 147
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 149 #define CONFIG_SYS_MAX_FLASH_SECT       128
 150
 151 #define CONFIG_ENV_IS_IN_EEPROM
 152 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 153 #define CONFIG_ENV_OFFSET               0
 154 #define CONFIG_ENV_SIZE         2048
 155 #endif
 156
 157 #undef  CONFIG_ENV_IS_IN_FLASH
 158 #ifdef  CONFIG_ENV_IS_IN_FLASH
 159 #define CONFIG_ENV_SIZE         0x00002000              /* Set whole sector as env              */
 160 #define CONFIG_ENV_OFFSET               ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)         /* Environment starts at this adress    */
 161 #endif
 162
 163 #define CONFIG_SPI              1
 164 #define CONFIG_SYS_SPI_CS_USED  0x09 /* CS0 and CS3 are used */
 165 #define CONFIG_SYS_SPI_CS_BASE  0x08 /* CS3 is active low */
 166 #define CONFIG_SYS_SPI_CS_ACT   0x00 /* CS3 is active low */
 167 /*-----------------------------------------------------------------------
 168  * SYPCR - System Protection Control
 169  * SYPCR can only be written once after reset!
 170  *-----------------------------------------------------------------------
 171  * SW Watchdog freeze
 172  */
 173 #undef CONFIG_WATCHDOG
 174 #if defined(CONFIG_WATCHDOG)
 175 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 176                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 177 #else
 178 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 179                          SYPCR_SWP)
 180 #endif  /* CONFIG_WATCHDOG */
 181
 182 /*-----------------------------------------------------------------------
 183  * TBSCR - Time Base Status and Control
 184  *-----------------------------------------------------------------------
 185  * Clear Reference Interrupt Status, Timebase freezing enabled
 186  */
 187 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 188
 189 /*-----------------------------------------------------------------------
 190  * PISCR - Periodic Interrupt Status and Control
 191  *-----------------------------------------------------------------------
 192  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 193  */
 194 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 195
 196 /*-----------------------------------------------------------------------
 197  * SCCR - System Clock and reset Control Register
 198  *-----------------------------------------------------------------------
 199  * Set clock output, timebase and RTC source and divider,
 200  * power management and some other internal clocks
 201  */
 202 #define SCCR_MASK       SCCR_EBDF00
 203 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 204                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 205
 206 /*-----------------------------------------------------------------------
 207  * SIUMCR - SIU Module Configuration
 208  *-----------------------------------------------------------------------
 209  * Data show cycle
 210  */
 211 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
 212
 213 /*-----------------------------------------------------------------------
 214  * PLPRCR - PLL, Low-Power, and Reset Control Register
 215  *-----------------------------------------------------------------------
 216  * Set all bits to 40 Mhz
 217  *
 218  */
 219 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 220
 221 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 222
 223 /*-----------------------------------------------------------------------
 224  * UMCR - UIMB Module Configuration Register
 225  *-----------------------------------------------------------------------
 226  *
 227  */
 228 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 229
 230 /*-----------------------------------------------------------------------
 231  * ICTRL - I-Bus Support Control Register
 232  */
 233 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 234
 235 /*-----------------------------------------------------------------------
 236  * USIU - Memory Controller Register
 237  *-----------------------------------------------------------------------
 238  */
 239 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 240 #define CONFIG_SYS_OR0_PRELIM           (0xffc00000) /* SCY is not used if external TA is set */
 241 /* SDRAM */
 242 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 243 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 244 /* PCI */
 245 #define CONFIG_SYS_BR2_PRELIM           (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 246 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 247 /* config registers: */
 248 #define CONFIG_SYS_BR3_PRELIM           (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 249 #define CONFIG_SYS_OR3_PRELIM           (0xffff0000)
 250
 251 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 252
 253 /*-----------------------------------------------------------------------
 254  * DER - Timer Decrementer
 255  *-----------------------------------------------------------------------
 256  * Initialise to zero
 257  */
 258 #define CONFIG_SYS_DER                  0x00000000
 259
 260 #define VERSION_TAG "released"
 261 #define CONFIG_ISO_STRING "MEV-10084-001"
 262
 263 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 264
 265 #endif  /* __CONFIG_H */