include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation,
  21  */
  22
  23 /*
  24  * File:                PATI.h
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  */
  33
  34 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  35 #define CONFIG_PATI             1               /* ...On a PATI board   */
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  38
  39 /* Serial Console Configuration */
  40 #define CONFIG_5xx_CONS_SCI1
  41 #undef  CONFIG_5xx_CONS_SCI2
  42
  43 #define CONFIG_BAUDRATE         9600
  44
  45
  46 /*
  47  * BOOTP options
  48  */
  49 #define CONFIG_BOOTP_BOOTFILESIZE
  50 #define CONFIG_BOOTP_BOOTPATH
  51 #define CONFIG_BOOTP_GATEWAY
  52 #define CONFIG_BOOTP_HOSTNAME
  53
  54
  55 /*
  56  * Command line configuration.
  57  */
  58 #define CONFIG_CMD_MEMORY
  59 #define CONFIG_CMD_LOADB
  60 #define CONFIG_CMD_REGINFO
  61 #define CONFIG_CMD_FLASH
  62 #define CONFIG_CMD_LOADS
  63 #define CONFIG_CMD_SAVEENV
  64 #define CONFIG_CMD_REGINFO
  65 #define CONFIG_CMD_BDI
  66 #define CONFIG_CMD_CONSOLE
  67 #define CONFIG_CMD_RUN
  68 #define CONFIG_CMD_BSP
  69 #define CONFIG_CMD_IMI
  70 #define CONFIG_CMD_EEPROM
  71 #define CONFIG_CMD_IRQ
  72 #define CONFIG_CMD_MISC
  73
  74
  75 #if 0
  76 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  77 #else
  78 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  79 #endif
  80 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  81
  82 #define CONFIG_BOOTARGS         ""              /* */
  83
  84 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  85
  86 /*#define CONFIG_STATUS_LED     1               */ /* Enable status led */
  87
  88 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  89
  90 /*
  91  * Miscellaneous configurable options
  92  */
  93 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
  94 #define CONFIG_PREBOOT
  95
  96 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  97 #define CONFIG_SYS_PROMPT               "pati=> "               /* Monitor Command Prompt       */
  98 #if defined(CONFIG_CMD_KGDB)
  99 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 100 #else
 101 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 102 #endif
 103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 104 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
 105 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 106
 107 #define CONFIG_SYS_MEMTEST_START        0x00010000      /* memtest works on             */
 108 #define CONFIG_SYS_MEMTEST_END          0x00A00000      /* 10 MB in SRAM                        */
 109
 110 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
 111
 112 #define CONFIG_SYS_HZ                   1000            /* Decrementer freq: 1 ms ticks */
 113
 114 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
 115
 116
 117 /***********************************************************************
 118  * Last Stage Init
 119  ***********************************************************************/
 120 #define CONFIG_LAST_STAGE_INIT
 121
 122 /*
 123  * Low Level Configuration Settings
 124  */
 125
 126 /*
 127  * Internal Memory Mapped (This is not the IMMR content)
 128  */
 129 #define CONFIG_SYS_IMMR         0x01C00000              /* Physical start adress of internal memory map */
 130
 131 /*
 132  * Definitions for initial stack pointer and data area
 133  */
 134 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
 135 #define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
 136 #define CONFIG_SYS_GBL_DATA_SIZE        128                     /* Size in bytes reserved for initial global data */
 137 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 138 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000)   /* Physical start adress of inital stack */
 139 /*
 140  * Start addresses for the final memory configuration
 141  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 142  */
 143 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
 144 #define CONFIG_SYS_FLASH_BASE           0xffC00000      /* External flash */
 145 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 146 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 147 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 148
 149 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 150 /* CONFIG_SYS_FLASH_BASE        */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.      */
 151                                                 /* This adress is given to the linker with -Ttext to    */
 152                                                 /* locate the text section at this adress.              */
 153 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 192 kB for Monitor                           */
 154 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()                          */
 155
 156 #define CONFIG_SYS_RESET_ADDRESS        (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 157
 158 /*
 159  * For booting Linux, the board info and command line data
 160  * have to be in the first 8 MB of memory, since this is
 161  * the maximum mapped by the Linux kernel during initialization.
 162  */
 163 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 164
 165
 166 /*-----------------------------------------------------------------------
 167  * FLASH organization
 168  *-----------------------------------------------------------------------
 169  *
 170  */
 171
 172 #define CONFIG_SYS_MAX_FLASH_BANKS              1               /* Max number of memory banks           */
 173 #define CONFIG_SYS_MAX_FLASH_SECT               128             /* Max number of sectors on one chip    */
 174 #define CONFIG_SYS_FLASH_ERASE_TOUT     180000          /* Timeout for Flash Erase (in ms)      */
 175 #define CONFIG_SYS_FLASH_WRITE_TOUT     600             /* Timeout for Flash Write (in ms)      */
 176
 177
 178 #define CONFIG_ENV_IS_IN_EEPROM
 179 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 180 #define CONFIG_ENV_OFFSET               0
 181 #define CONFIG_ENV_SIZE         2048
 182 #endif
 183
 184 #undef  CONFIG_ENV_IS_IN_FLASH
 185 #ifdef  CONFIG_ENV_IS_IN_FLASH
 186 #define CONFIG_ENV_SIZE         0x00002000              /* Set whole sector as env              */
 187 #define CONFIG_ENV_OFFSET               ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)         /* Environment starts at this adress    */
 188 #endif
 189
 190
 191 #define CONFIG_SPI              1
 192 #define CONFIG_SYS_SPI_CS_USED  0x09 /* CS0 and CS3 are used */
 193 #define CONFIG_SYS_SPI_CS_BASE  0x08 /* CS3 is active low */
 194 #define CONFIG_SYS_SPI_CS_ACT   0x00 /* CS3 is active low */
 195 /*-----------------------------------------------------------------------
 196  * SYPCR - System Protection Control
 197  * SYPCR can only be written once after reset!
 198  *-----------------------------------------------------------------------
 199  * SW Watchdog freeze
 200  */
 201 #undef CONFIG_WATCHDOG
 202 #if defined(CONFIG_WATCHDOG)
 203 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 204                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 205 #else
 206 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 207                          SYPCR_SWP)
 208 #endif  /* CONFIG_WATCHDOG */
 209
 210 /*-----------------------------------------------------------------------
 211  * TBSCR - Time Base Status and Control
 212  *-----------------------------------------------------------------------
 213  * Clear Reference Interrupt Status, Timebase freezing enabled
 214  */
 215 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 216
 217 /*-----------------------------------------------------------------------
 218  * PISCR - Periodic Interrupt Status and Control
 219  *-----------------------------------------------------------------------
 220  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 221  */
 222 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 223
 224 /*-----------------------------------------------------------------------
 225  * SCCR - System Clock and reset Control Register
 226  *-----------------------------------------------------------------------
 227  * Set clock output, timebase and RTC source and divider,
 228  * power management and some other internal clocks
 229  */
 230 #define SCCR_MASK       SCCR_EBDF00
 231 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 232                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 233
 234 /*-----------------------------------------------------------------------
 235  * SIUMCR - SIU Module Configuration
 236  *-----------------------------------------------------------------------
 237  * Data show cycle
 238  */
 239 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
 240
 241 /*-----------------------------------------------------------------------
 242  * PLPRCR - PLL, Low-Power, and Reset Control Register
 243  *-----------------------------------------------------------------------
 244  * Set all bits to 40 Mhz
 245  *
 246  */
 247 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 248
 249
 250 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 251
 252 /*-----------------------------------------------------------------------
 253  * UMCR - UIMB Module Configuration Register
 254  *-----------------------------------------------------------------------
 255  *
 256  */
 257 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 258
 259 /*-----------------------------------------------------------------------
 260  * ICTRL - I-Bus Support Control Register
 261  */
 262 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 263
 264 /*-----------------------------------------------------------------------
 265  * USIU - Memory Controller Register
 266  *-----------------------------------------------------------------------
 267  */
 268 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 269 #define CONFIG_SYS_OR0_PRELIM           (0xffc00000) /* SCY is not used if external TA is set */
 270 /* SDRAM */
 271 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 272 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 273 /* PCI */
 274 #define CONFIG_SYS_BR2_PRELIM           (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 275 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 276 /* config registers: */
 277 #define CONFIG_SYS_BR3_PRELIM           (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 278 #define CONFIG_SYS_OR3_PRELIM           (0xffff0000)
 279
 280 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 281
 282 /*-----------------------------------------------------------------------
 283  * DER - Timer Decrementer
 284  *-----------------------------------------------------------------------
 285  * Initialise to zero
 286  */
 287 #define CONFIG_SYS_DER                  0x00000000
 288
 289
 290 /*
 291  * Internal Definitions
 292  *
 293  * Boot Flags
 294  */
 295 #define BOOTFLAG_COLD   0x01                    /* Normal Power-On: Boot from FLASH     */
 296 #define BOOTFLAG_WARM   0x02                    /* Software reboot                      */
 297
 298
 299 #define VERSION_TAG "released"
 300 #define CONFIG_ISO_STRING "MEV-10084-001"
 301
 302 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 303
 304 #endif  /* __CONFIG_H */