include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * File:                PATI.h
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18
  19 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  20 #define CONFIG_PATI             1               /* ...On a PATI board   */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  23
  24 #define CONFIG_SYS_GENERIC_BOARD
  25
  26 /* Serial Console Configuration */
  27 #define CONFIG_5xx_CONS_SCI1
  28 #undef  CONFIG_5xx_CONS_SCI2
  29
  30 #define CONFIG_BAUDRATE         9600
  31
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41
  42 /*
  43  * Command line configuration.
  44  */
  45 #define CONFIG_CMD_REGINFO
  46 #define CONFIG_CMD_REGINFO
  47 #define CONFIG_CMD_BSP
  48 #define CONFIG_CMD_EEPROM
  49 #define CONFIG_CMD_IRQ
  50
  51
  52 #if 0
  53 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  54 #else
  55 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  56 #endif
  57 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  58
  59 #define CONFIG_BOOTARGS         ""              /* */
  60
  61 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  62
  63 /*#define CONFIG_STATUS_LED     1               */ /* Enable status led */
  64
  65 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  66
  67 /*
  68  * Miscellaneous configurable options
  69  */
  70 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
  71 #define CONFIG_PREBOOT
  72
  73 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  74 #define CONFIG_SYS_PROMPT               "pati=> "               /* Monitor Command Prompt       */
  75 #if defined(CONFIG_CMD_KGDB)
  76 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  77 #else
  78 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  79 #endif
  80 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  81 #define CONFIG_SYS_MAXARGS              16             /* max number of command args    */
  82 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  83
  84 #define CONFIG_SYS_MEMTEST_START        0x00010000      /* memtest works on             */
  85 #define CONFIG_SYS_MEMTEST_END          0x00A00000      /* 10 MB in SRAM                        */
  86
  87 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
  88
  89 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 1250000 }
  90
  91 #define CONFIG_BOARD_EARLY_INIT_F
  92
  93 /***********************************************************************
  94  * Last Stage Init
  95  ***********************************************************************/
  96 #define CONFIG_LAST_STAGE_INIT
  97
  98 /*
  99  * Low Level Configuration Settings
 100  */
 101
 102 /*
 103  * Internal Memory Mapped (This is not the IMMR content)
 104  */
 105 #define CONFIG_SYS_IMMR         0x01C00000              /* Physical start adress of internal memory map */
 106
 107 /*
 108  * Definitions for initial stack pointer and data area
 109  */
 110 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_IMMR + 0x003f9800)  /* Physical start adress of internal MPC555 writable RAM */
 111 #define CONFIG_SYS_INIT_RAM_SIZE        (CONFIG_SYS_IMMR + 0x003fffff)  /* Physical end adress of internal MPC555 used RAM area */
 112 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 113 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000)   /* Physical start adress of inital stack */
 114 /*
 115  * Start addresses for the final memory configuration
 116  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 117  */
 118 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* Monitor won't change memory map                      */
 119 #define CONFIG_SYS_FLASH_BASE           0xffC00000      /* External flash */
 120 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 121 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 122 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 123
 124 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 125 /* CONFIG_SYS_FLASH_BASE        */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.      */
 126                                                 /* This adress is given to the linker with -Ttext to    */
 127                                                 /* locate the text section at this adress.              */
 128 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 192 kB for Monitor                           */
 129 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()                          */
 130
 131 #define CONFIG_SYS_RESET_ADDRESS        (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 132
 133 /*
 134  * For booting Linux, the board info and command line data
 135  * have to be in the first 8 MB of memory, since this is
 136  * the maximum mapped by the Linux kernel during initialization.
 137  */
 138 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux         */
 139
 140
 141 /*-----------------------------------------------------------------------
 142  * FLASH organization
 143  *-----------------------------------------------------------------------
 144  *
 145  */
 146
 147 #define CONFIG_SYS_FLASH_PROTECTION
 148 #define CONFIG_SYS_FLASH_EMPTY_INFO
 149
 150 #define CONFIG_SYS_FLASH_CFI
 151 #define CONFIG_FLASH_CFI_DRIVER
 152
 153 #define CONFIG_FLASH_SHOW_PROGRESS      45
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 156 #define CONFIG_SYS_MAX_FLASH_SECT       128
 157
 158 #define CONFIG_ENV_IS_IN_EEPROM
 159 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 160 #define CONFIG_ENV_OFFSET               0
 161 #define CONFIG_ENV_SIZE         2048
 162 #endif
 163
 164 #undef  CONFIG_ENV_IS_IN_FLASH
 165 #ifdef  CONFIG_ENV_IS_IN_FLASH
 166 #define CONFIG_ENV_SIZE         0x00002000              /* Set whole sector as env              */
 167 #define CONFIG_ENV_OFFSET               ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)         /* Environment starts at this adress    */
 168 #endif
 169
 170
 171 #define CONFIG_SPI              1
 172 #define CONFIG_SYS_SPI_CS_USED  0x09 /* CS0 and CS3 are used */
 173 #define CONFIG_SYS_SPI_CS_BASE  0x08 /* CS3 is active low */
 174 #define CONFIG_SYS_SPI_CS_ACT   0x00 /* CS3 is active low */
 175 /*-----------------------------------------------------------------------
 176  * SYPCR - System Protection Control
 177  * SYPCR can only be written once after reset!
 178  *-----------------------------------------------------------------------
 179  * SW Watchdog freeze
 180  */
 181 #undef CONFIG_WATCHDOG
 182 #if defined(CONFIG_WATCHDOG)
 183 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 184                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 185 #else
 186 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 187                          SYPCR_SWP)
 188 #endif  /* CONFIG_WATCHDOG */
 189
 190 /*-----------------------------------------------------------------------
 191  * TBSCR - Time Base Status and Control
 192  *-----------------------------------------------------------------------
 193  * Clear Reference Interrupt Status, Timebase freezing enabled
 194  */
 195 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 196
 197 /*-----------------------------------------------------------------------
 198  * PISCR - Periodic Interrupt Status and Control
 199  *-----------------------------------------------------------------------
 200  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 201  */
 202 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 203
 204 /*-----------------------------------------------------------------------
 205  * SCCR - System Clock and reset Control Register
 206  *-----------------------------------------------------------------------
 207  * Set clock output, timebase and RTC source and divider,
 208  * power management and some other internal clocks
 209  */
 210 #define SCCR_MASK       SCCR_EBDF00
 211 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 212                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 213
 214 /*-----------------------------------------------------------------------
 215  * SIUMCR - SIU Module Configuration
 216  *-----------------------------------------------------------------------
 217  * Data show cycle
 218  */
 219 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
 220
 221 /*-----------------------------------------------------------------------
 222  * PLPRCR - PLL, Low-Power, and Reset Control Register
 223  *-----------------------------------------------------------------------
 224  * Set all bits to 40 Mhz
 225  *
 226  */
 227 #define CONFIG_SYS_OSC_CLK      ((uint)4000000)         /* Oscillator clock is 4MHz     */
 228
 229
 230 #define CONFIG_SYS_PLPRCR       (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 231
 232 /*-----------------------------------------------------------------------
 233  * UMCR - UIMB Module Configuration Register
 234  *-----------------------------------------------------------------------
 235  *
 236  */
 237 #define CONFIG_SYS_UMCR (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 238
 239 /*-----------------------------------------------------------------------
 240  * ICTRL - I-Bus Support Control Register
 241  */
 242 #define CONFIG_SYS_ICTRL        (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 243
 244 /*-----------------------------------------------------------------------
 245  * USIU - Memory Controller Register
 246  *-----------------------------------------------------------------------
 247  */
 248 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 249 #define CONFIG_SYS_OR0_PRELIM           (0xffc00000) /* SCY is not used if external TA is set */
 250 /* SDRAM */
 251 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 252 #define CONFIG_SYS_OR1_PRELIM           (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 253 /* PCI */
 254 #define CONFIG_SYS_BR2_PRELIM           (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 255 #define CONFIG_SYS_OR2_PRELIM           (OR_ADDR_MK_FF)
 256 /* config registers: */
 257 #define CONFIG_SYS_BR3_PRELIM           (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 258 #define CONFIG_SYS_OR3_PRELIM           (0xffff0000)
 259
 260 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* We don't realign the flash   */
 261
 262 /*-----------------------------------------------------------------------
 263  * DER - Timer Decrementer
 264  *-----------------------------------------------------------------------
 265  * Initialise to zero
 266  */
 267 #define CONFIG_SYS_DER                  0x00000000
 268
 269 #define VERSION_TAG "released"
 270 #define CONFIG_ISO_STRING "MEV-10084-001"
 271
 272 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 273
 274 #endif  /* __CONFIG_H */