include/configs/PCI405.h

   1 /*
   2  * (C) Copyright 2007
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2004
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  39 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  40 #define CONFIG_PCI405           1       /* ...on a PCI405 board         */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r() on init   */
  44
  45 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  46
  47 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  48
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_BOOTDELAY        0       /* autoboot after 0 seconds     */
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  54         "mem_linux=14336k\0"                                            \
  55         "optargs=panic=0\0"                                             \
  56         "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"     \
  57         "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
  58         ""
  59 #define CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"
  60
  61 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  62
  63 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  64 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  65
  66 #define CONFIG_MII              1       /* MII PHY management           */
  67 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  68
  69 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  70
  71
  72 /*
  73  * BOOTP options
  74  */
  75 #define CONFIG_BOOTP_BOOTFILESIZE
  76 #define CONFIG_BOOTP_BOOTPATH
  77 #define CONFIG_BOOTP_GATEWAY
  78 #define CONFIG_BOOTP_HOSTNAME
  79
  80
  81 /*
  82  * Command line configuration.
  83  */
  84 #include <config_cmd_default.h>
  85
  86 #define CONFIG_CMD_PCI
  87 #define CONFIG_CMD_IRQ
  88 #define CONFIG_CMD_ELF
  89 #define CONFIG_CMD_DATE
  90 #define CONFIG_CMD_I2C
  91 #define CONFIG_CMD_BSP
  92 #define CONFIG_CMD_EEPROM
  93
  94
  95 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  96
  97 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  98
  99 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
 100
 101 /*
 102  * Miscellaneous configurable options
 103  */
 104 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 105 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 106
 107 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 108 #ifdef  CONFIG_SYS_HUSH_PARSER
 109 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 110 #endif
 111
 112 #if defined(CONFIG_CMD_KGDB)
 113 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 114 #else
 115 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 116 #endif
 117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 118 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 119 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 120
 121 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 122
 123 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 124
 125 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 126 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 127
 128 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 129 #define CONFIG_SYS_IGNORE_405_UART_ERRATA_59    /* ignore ppc405gp errata #59   */
 130 #define CONFIG_SYS_BASE_BAUD        691200
 131
 132 /* The following table includes the supported baudrates */
 133 #define CONFIG_SYS_BAUDRATE_TABLE       \
 134         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 135          57600, 115200, 230400, 460800, 921600 }
 136
 137 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 138 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 139
 140 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 141
 142 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* check for keypress on bootdelay==0 */
 143
 144 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 145
 146 /*-----------------------------------------------------------------------
 147  * PCI stuff
 148  *-----------------------------------------------------------------------
 149  */
 150 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 151 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 152 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 153
 154 #define CONFIG_PCI                      /* include pci support          */
 155 #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function    */
 156 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
 157                                         /* resource configuration       */
 158
 159 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 160
 161 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 162 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407   /* PCI Device ID: PCI-405       */
 163 #define CONFIG_SYS_PCI_CLASSCODE        0x0280  /* PCI Class Code: Network/Other*/
 164 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 165 #define CONFIG_SYS_PCI_PTM1MS   0xff000001      /* 16MB, enable hard-wired to 1 */
 166 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 167
 168 #if 0 /* test-only */
 169 #define CONFIG_SYS_PCI_PTM2LA   0xffc00000      /* point to flash               */
 170 #define CONFIG_SYS_PCI_PTM2MS   0xffc00001      /* 4MB, enable                  */
 171 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 172 #else
 173 #define CONFIG_SYS_PCI_PTM2LA   0xef600000      /* point to internal regs       */
 174 #define CONFIG_SYS_PCI_PTM2MS   0xffe00001      /* 2MB, enable                  */
 175 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000       /* Host: use this pci address   */
 176 #endif
 177
 178 /*-----------------------------------------------------------------------
 179  * Start addresses for the final memory configuration
 180  * (Set up by the startup code)
 181  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 182  */
 183 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 184 #define CONFIG_SYS_FLASH_BASE           0xFFFD0000
 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 186 #define CONFIG_SYS_MONITOR_LEN          (192 * 1024)    /* Reserve 196 kB for Monitor   */
 187 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 188
 189 /*
 190  * For booting Linux, the board info and command line data
 191  * have to be in the first 8 MB of memory, since this is
 192  * the maximum mapped by the Linux kernel during initialization.
 193  */
 194 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 195 /*-----------------------------------------------------------------------
 196  * FLASH organization
 197  */
 198 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 199 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 200
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 203
 204 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 205 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 206 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 207 /*
 208  * The following defines are added for buggy IOP480 byte interface.
 209  * All other boards should use the standard values (CPCI405 etc.)
 210  */
 211 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 212 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 213 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 214
 215 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 216
 217 #if 0 /* Use NVRAM for environment variables */
 218 /*-----------------------------------------------------------------------
 219  * NVRAM organization
 220  */
 221 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
 222 #define CONFIG_ENV_SIZE         0x0ff8          /* Size of Environment vars     */
 223 #define CONFIG_ENV_ADDR         \
 224         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))  /* Env  */
 225
 226 #else /* Use EEPROM for environment variables */
 227
 228 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 229 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 230 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars*/
 231                                    /* total size of a CAT24WC08 is 1024 bytes */
 232 #endif
 233
 234 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0200000              /* NVRAM base address   */
 235 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 236
 237 /*-----------------------------------------------------------------------
 238  * I2C EEPROM (CAT24WC16) for environment
 239  */
 240 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 241 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 242 #define CONFIG_SYS_I2C_SLAVE            0x7F
 243
 244 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 246 /* mask of address bits that overflow into the "EEPROM chip address"    */
 247 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 249                                         /* 16 byte page write mode using*/
 250                                         /* last 4 bits of the address   */
 251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 252
 253 /*
 254  * Init Memory Controller:
 255  *
 256  * BR0/1 and OR0/1 (FLASH)
 257  */
 258
 259 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 260
 261 /*-----------------------------------------------------------------------
 262  * External Bus Controller (EBC) Setup
 263  */
 264
 265 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 266 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 267 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 268
 269 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 270 #define CONFIG_SYS_EBC_PB1AP            0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
 271 #define CONFIG_SYS_EBC_PB1CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 272
 273 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 274 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 275 /*#define CONFIG_SYS_EBC_PB2AP            0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 276 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 277
 278 /* Memory Bank 3 (FPGA internal) initialization                                 */
 279 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 280 #define CONFIG_SYS_EBC_PB3CR            0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 281 #define CONFIG_SYS_FPGA_BASE_ADDR       0xF0400000
 282
 283 /*-----------------------------------------------------------------------
 284  * FPGA stuff
 285  */
 286 /* FPGA internal regs */
 287 #define CONFIG_SYS_FPGA_MODE            0x00
 288 #define CONFIG_SYS_FPGA_STATUS          0x02
 289 #define CONFIG_SYS_FPGA_TS              0x04
 290 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 291 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 292 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 293 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 294 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 295 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 296 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 297 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 298 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 299
 300 /* FPGA Mode Reg */
 301 #define CONFIG_SYS_FPGA_MODE_CF_RESET   0x0001
 302 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 303 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 304 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR   0x2000
 305
 306 /* FPGA Status Reg */
 307 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 308 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 309 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 310 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 311 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 312
 313 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 314 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024     /* 32kByte is enough for XC2S15  */
 315
 316 /* FPGA program pin configuration */
 317 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 318 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 319 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 320 #define CONFIG_SYS_FPGA_INIT            0x00400000  /* FPGA init pin (ppc input)     */
 321 #define CONFIG_SYS_FPGA_DONE            0x00800000  /* FPGA done pin (ppc input)     */
 322 /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
 323 #define CONFIG_SYS_FPGA_INIT_V12        0x00008000  /* FPGA init pin (ppc input)     */
 324 #define CONFIG_SYS_FPGA_DONE_V12        0x00010000  /* FPGA done pin (ppc input)     */
 325
 326 /*-----------------------------------------------------------------------
 327  * Definitions for initial stack pointer and data area (in data cache)
 328  */
 329 #if 0 /* test-only */
 330 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 331 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 332 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in RAM             */
 333 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 334 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 335 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 336 #else
 337 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 338 #define CONFIG_SYS_TEMP_STACK_OCM         1
 339 /* On Chip Memory location */
 340 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 341 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 342 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 343 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 344
 345 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 346 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 347 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 348 #endif
 349
 350 /*
 351  * Internal Definitions
 352  *
 353  * Boot Flags
 354  */
 355 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 356 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 357
 358 #endif  /* __CONFIG_H */